TW466575B - Improvement of silicon nodule problem for manufacturing gate - Google Patents

Abstract

This invention discloses the formation method of gate for integrated circuit, which solves the silicon nodule problem occurred during manufacturing gate. The method mainly consists of the following steps. A substrate is given and an oxide layer is formed on the substrate. A first conductor layer is deposited on top of the oxide layer and then a first barrier layer is formed onto the first conductor layer. A second conductor layer is deposited onto the first barrier layer and subsequently a second barrier layer is formed onto the second conductor layer. The second conductor layer is formed by rapid thermal process. A bottom anti-reflection layer is formed on top of the second barrier layer and an insulation layer formed onto the bottom anti-reflection layer. A photo resist layer is then formed onto the insulation layer and a gate area pattern is created on the photo resist layer. Using the patterned photo resist layer as mask, etching is carried out on the insulation layer, the bottom anti-reflection layer, the second barrier layer, the second conductor layer, the first barrier layer and the first conductor layer. Finally, the photo resist layer is removed.

Description

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DESCRIPTION OF THE INVENTION (1) 5-1 Field of the Invention: The present invention relates to an idle method in a method of manufacturing an integrated circuit, a method of manufacturing an integrated circuit. In particular, the background of the invention of 5-2: The gates of the integrated circuit are produced in the "pass", mainly by the following method-see the figure "First, a multi-groove isolation 11 is formed on a substrate 10, Isolate each active area on the substrate. 'It can be done by any conventional standard procedure. The appropriate ionions are then incorporated into the active area of the substrate 10 to form a well ( Support 1) u, can be formed by ion implantation (10n implantati) or other traditional methods: then = gate 〇xide layer (gate 〇xide layer) 3 on the substrate ^: then 'deposit a polycrystalline silicon Layers "Ya" and "Yi" are created on this gate oxide layer 13. After some necessary ion doping procedures (doopi process), titanium nitride (TiN) is deposited. Layer 15 is on polycrystalline silicon On the layer η, the thickness of the titanium nitride layer 15 is about 50 to 400 Angstroms, which can be used as a barrier layer or a glue layer. Then, an amorphous A titanium silicide (7 ^ 5 dagger) layer 16 is formed on the titanium nitride 15 layer. This titanium silicide has a low resistance. After characteristics, straight

657 5 V. Description of the invention (2) Depositing a silicon oxynitride (si 0N) layer 丨 7 on this titanium silicide layer 丨 6 as a bottom anti-reflective coating (B0tt〇m anti-reflective coating, BARC) ). In order to isolate the gate electrode (gate electrode) from other unrelated components, a silicon nitride layer 18 is formed on the titanium silicide layer 18 °, and then a pattern with a gate (pattern a gate) is formed. A photoresist layer 19 is formed on the silicon nitride layer is; then the photoresist layer 19 is used as a mask to perform an etch process. After the photoresist is removed, the gate electrode may be Formation, as shown in the second figure. 0 After forming the gate electrode by the above-mentioned manufacturing process, particles 20 will appear on the surface of the substrate 10 near the gate electrode region, which is due to t: 2 tf 2 In the interface with the lice emulsified silicon layer 17, two kinds of compounds will be formed: 仃 and 应 will form the product silicon dioxide (Si0 2) and dioxygen tl · μ X ^ i ", and this generation It is easy to drop the object on the surface of the substrate 10, and the situation of "Shi Xi Tuo" "Ulcon nodule lssue" will cause severe yields in subsequent processes. In order to solve this problem, the quality and rate of the products are not good and cannot be saved. The cost of time. It ’s really necessary to develop a table-method to make the poles more efficient, i ::; enough to reduce or eliminate the 'other - side of the semiconductor manufacturing process is concerned, it can be; cost ._ future trend of high-precision said Tony Shu guilty of consistent quality contribution!.

$ 5 pages

5-3 Purpose and Summary of the Invention: In view of the above-mentioned background of the invention, the disadvantages caused by the traditional fabrication of the gate of the integrated circuit t are described. The purpose of the present invention is to prevent unnecessary particles from falling on the surface of the substrate and solve the problem. Siloma problem. 'Another object of the present invention is to increase the efficiency of the process' and to save the time cost when manufacturing the integrated circuit gate. — According to the above-mentioned object, the present invention provides a method for manufacturing a gate electrode. The method mainly includes the following steps. A substrate is provided, and an emulsified layer is formed on the substrate. Then, a polycrystalline debris layer is formed on the oxide layer, and a first titanium nitride layer is formed on the polycrystalline silicon layer. Next, a titanite layer is formed on the first titanium nitride layer; a second titanium nitride layer is formed on the titanium silicide layer; the titanium silicide layer is formed by a rapid heating process; formation-nitrogen A silicon oxide layer is formed on the second titanium nitride layer; a silicon nitride layer is formed on the silicon oxynitride layer. Next, a photoresist layer is formed on the silicon nitride layer, and the photoresist layer has a pattern of a gate region; and then the silicon nitride layer, the silicon oxynitride layer, the second titanium nitride layer, and the titanium silicide are etched. Layer, the first titanium nitride layer, and the polycrystalline silicon layer 'and the photoresist layer is used as a mask. Finally, the photoresist layer is removed.

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4 6 657 5 V. Description of the invention (4) 5-4 Schematic illustration: The first diagram is a cross-sectional view of a step in the gate process of a traditional integrated circuit. The second picture shows the gates formed in the traditional way and the "$ xi tumor problem". The third to fifth figures show the representative symbols of the cross-sections of the steps of manufacturing the gate electrode of the present invention: 10 substrate 11 shallow trench isolation 12 well 13 gate oxide layer 14 polycrystalline silicon layer 15 nitride layer 16 nitrogen silicide layer 17 silicon oxynitride layer 18 silicon nitride layer 19 photoresist layer 20 particles 100 substrate 101 shallow trench isolation 102 wells

466575 V. Description of the invention ¢ 5) 10 3 Gate oxide layer 10 4 Polycrystalline silicon layer 10 5 Titanium nitride layer 10 6 Nitrogen silicide layer 10 7 Titanium nitride layer 10 8 Silicon oxynitride layer 10 9 Nitridation layer 11 0 Photoresist layer 5-5 Detailed description of the invention: The present invention provides a method for manufacturing an improved integrated circuit gate. This method mainly uses a rapid heating process to form a titanium nitride layer to prevent the oxynitride layer and silicon silicide. The direct contact and reaction of the material layer; and the rapid heating procedure can also save the time cost of this process ◎ This method is described below. Referring to the third figure, first, a substrate 100 is provided, and a shallow trench isolation (STI) 101 is formed thereon. The substrate 100 can be used for photolithography, etching, oxide deposition, And chemical mechanical polishing (chemical mechanical pol ishing, CMP). This shallow trench isolation 101 is used to isolate each active area on the substrate 100, and then, by ion implantation or other appropriate conventional methods

Page 8 466575 V. Description of the invention (6) Method Doping ions into the substrate 100 to form a well (we 11) 102. Referring to the fourth figure, an oxide layer 103 is formed on the substrate 100 by a thermal oxidation method or another suitable method as a gate oxide layer. A polycrystalline silicon layer 104 or other suitable conductor is formed on the oxide layer 103 with a thickness of about 1500 angstroms, and ions are usually implanted into the polycrystalline silicon layer 104 by implantation or diffusion. To increase its conductivity. Next, a titanium nitride (TiN) layer 105 is deposited on the polycrystalline silicon layer 104, and can be completed by a deposition process such as chemical vapor deposition (CVD) or other appropriate methods. The titanium nitride layer 105 is used as a barrier layer or a glue layer, and has a thickness of about 50 to 400 angstroms. An amorphous titanium silicide (TiSix) layer 1 06 is deposited on the titanium nitride layer 105, which can be completed by sputtering deposit ion or other appropriate methods, and the thickness is approximately 500 to 2000 Angstroms. Titanium silicide has a good conductivity of more crystalline silicon, and the titanium silicide layer 106 here and the aforementioned polycrystalline silicon layer 104 are used together as a gate electrode. After that, a rapid thermal oxidation (RT0) process is performed with the addition of nitrogen (n2) or ammonia (NH3) to form a gas having a thickness of about 50 to 200 on the titanium silicide layer 106. The titaniumized layer 10 7 ′ is used as a barrier layer. The temperature of this rapid heating program is about 5 50 to 6 50 ° C, and the heating is about 30 seconds, nitrogen or ammonia gas.

4 S 657 5 V. Description of the invention (7) The flow rate is about 30 SLM (standard liter per minute). The next step is to deposit a titanium nitride (Si ON) layer 108 on the titanium nitride layer 107, which can be completed by a chemical vapor deposition method. The titanium oxynitride layer 108 serves as a bottom anti-reflective coating (barc) and has a thickness of about 200 to 500 angstroms. The above-mentioned titanium nitride layer 107 can isolate direct contact between titanium oxynitride (SiON) and titanium silicide (TiSix) and prevent the reaction of these two substances, so that titanium dioxide (T i 〇2) and silicon dioxide are not generated. (Si 〇2) and other materials, there will be no such particles fall on the substrate 100, so the problem of silicoma generated in the traditional process has been eliminated. Furthermore, the titanium nitride layer 107 is formed by a rapid thermal process in a very short time (about 30 seconds), the production efficiency is improved, and time and cost can be saved.

Next, to form a cap insulating layer for the gate, a silicon nitride (siN) 1 09 is formed on the silicon oxynitride layer by a deposition method or other conventional methods for protection. The top of the gate electrode. Next, a photoresist layer 11 is formed on the silicon nitride layer 10, and a gate region pattern (pa 11 er η) can be formed thereon by using conventional standard procedures such as photolithography and etching. ). Using the patterned photoresist layer 110 as a mask, a silicon nitride layer 109, a silicon oxynitride layer 108, a titanium nitride layer 107, and a titanium silicide layer are formed by an anisotropic etching process.丨, the titanium nitride layer 105 and polycrystalline stone layer 104 are etched. After that, the photoresist layer 11 0 is removed by a stripping method (stroipin g).

Page ii) 4 6 65 7 5 V. Description of the invention (8) Refer to the fifth figure. The gate has been completed. Subsequent productions need to be performed such as spacers, hghtiy doped drain (LDD), source / 'and pole regions (source / drain regions) and other necessary components' to form integrated circuits ( integrated circuits). And there will be no siliconoma problem (s 丨 丨 ic〇nn〇du je issue) encountered in the traditional process. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention. ; All other equivalent changes or modifications made without departing from the spirit disclosed in the present invention shall be included in the following patents &

Claims (1)

) 657 5 VI. Application Patent Scope 1. A method for forming a gate in an integrated circuit, at least comprising: providing a substrate; forming a shape into a shape on a material bottom = & The upper layer guide is layered on the upper and upper layer barriers 1 ί The first Hai Hai- ^ 5 ^ 5 The Yu Yu barrier blocks one or two, the second layer, the second layer, the second layer, and the second layer. ， = ° The layered barrier blocks the order of the second pass, the first heat, the addition, the speed, the rapid formation, and the bottom layer of the resistive layer should be formed. The upper layer is formed into a shaped upper layer; Yu gate bottom gate-there is an upper layer to block the light and the upper barrier 衾 > ιφ to block the light and block the light layer and the barrier to block the second layer, the first layer of the body, the first layer of the first reflection The barriers of each layer > 1. The first layer of the layer must not block the barrier, and the layer of the light case. The remaining guide cover of the block inscription of the figure is shifted to the second layer of the zone. ° Applying the forming method to oxygenate 2. The hot item in its method 1J Section 巳 A. Couli specializes in the description of layered oxygen = β Shen Ruyi's layered oxygen electrode gate L is 3 y As the method of layered oxygen in the description I-^ Article Fan Zhuan Layer body guide \ The above description of its legal terms i-Fan Li, please apply for 4 Page 12 466575 6. Scope of patent application At least polycrystalline silicon is included. 5 The method of accessing the appropriate V? 7 "item 4 above" of which the above ... method of 6 to 2 of the scope of the patent application has been applied to item 1 "wherein the above-mentioned barrier layer Wang Shao contains titanium nitride, the thickness of about For 50 to 4 0 0 Angstroms. 7. I The method according to item 丨 of the scope of patent application, wherein the second conductor layer includes at least titanium silicide (TiSix) and has a thickness of about 500 to 2000 angstroms. 8. The method according to item 7 of the patent application range, wherein the above titanium silicide is formed by a professional plating deposition method. 9. The method according to item 7 of the patent application range, wherein the titanium silicide to the above includes an amorphous chinite. 10. The method according to item 1 of the scope of patent application, wherein said second barrier layer contains at least titanium nitride 'and has a thickness of about 50 to 200 angstroms. Π · The method according to item 1 of the patent application range, wherein the temperature of the above rapid heating process is about 550 to 650 t. 12. The method according to the scope of application for patent item i, wherein the above-mentioned rapid heating agriculture Page 13 1: Revision-Called Year, Month, and Month Revision ^ ^, \, ^ / 6 ^^ 8 ^ 3158 d 谞 Special Han—The time taken by the process is about 30 seconds. 13. The method according to item 10 of the scope of patent application, wherein the above-mentioned titanium nitride is formed by passing ammonia (NH3) or nitrogen (N2) in a rapid heating process. 14. The method according to item 1 of the patent application range, wherein the bottom anti-reflective layer includes at least oxynitride. 15. The method according to item 1 of the scope of patent application, wherein the thickness of the above-mentioned bottom anti-reflection layer is about 2000 to 500 Angstroms. 16. The method according to item 1 of the patent application range, wherein the bottom anti-reflection layer is formed by a deposition method. 17. The method according to item 1 of the scope of patent application, wherein the above-mentioned insulating layer includes at least silicon nitride and has a thickness of about 500 to 2000 angstroms. 1 8. The method according to item 1 of the patent application range, wherein the above-mentioned insulation layer is formed by a deposition method. It includes at least 19. A method for forming a gate in an integrated circuit, providing a substrate, forming an oxide layer on the substrate, and forming a polycrystalline silicon layer on the oxide layer; Page 14 2001. G5. 01. 015 46 657 5 Forming a first titanium nitride layer, forming a titanium silicide layer, forming a second titanium nitride layer layer, forming a silicon oxynitride layer by a rapid heating process, forming a nitrided sand layer, and forming a photoresist layer A pattern on the nitrogen electrode region; on the polycrystalline silicon layer; on the first titanium nitride layer; on the titanium silicide layer, the titanium is formed; on the second nitride layer; on the oxynitride layer ; On the photoresist layer, the photoresist layer is engraved with the nitrided second layer, the vermiculite layer, and the first resist layer is a mask; and the photoresist layer is removed. The silicon oxynitride layer, the second titanium nitride nitride layer, and the polycrystalline silicon layer, and the method of forming D by thermal oxidation method according to the 19th item of the patent application scope, wherein the method of the above oxygen item ... upper ... 2 2. The method of scope item 19, wherein the thickness of said first Chin layer is about 50 to 400 Angstroms. 23'As in the method of claim 19, the thickness of the compound layer is about 500 to 2000 angstroms. / 、 The fifth compound of Zhongda has a gate titanium layer, and the photochemical layer is a crystalline hard layer. Nitriding —jiiv ^ 6. Scope of patent application 24. The method according to item 19 of the scope of patent application, wherein the above titanium silicide layer is formed by a sputtering deposition method. 25. The method according to item 19 of the patent application scope, wherein the titanium silicide layer includes at least amorphous titanite. 26. The method of claim 19, wherein the thickness of the second titanium nitride layer is about 50 to 200 angstroms. 2 7. The method according to item 19 of the scope of patent application, wherein the temperature of the rapid heating system described above is about 550 to 650 ° C. 28. For the method of claim 19 in the scope of patent application, the time for the rapid heating process mentioned above is about 30 seconds. 29. The method according to item 19 of the patent application scope, wherein the rapid heating process described above uses ammonia (NH3) or nitrogen (N2) to form the second titanium nitride layer. 30. The method according to item 19 of the patent application, wherein the thickness of the silicon oxynitride layer is about 2000 to 500 angstroms. 31. The method according to item 19 of the claims, wherein the silicon nitride layer described above Page 16 ^ b 6 5 7 5 The thickness of the patent application range is approximately 500 to 2000 Angstroms. 32. The method according to claim 19, wherein the silicon nitride layer is formed by a deposition method. Page 17