TW495911B - Method of using inorganic antireflection coating layer to manufacture contact window and reduce device damage - Google Patents

Method of using inorganic antireflection coating layer to manufacture contact window and reduce device damage Download PDF

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TW495911B
TW495911B TW88122994A TW88122994A TW495911B TW 495911 B TW495911 B TW 495911B TW 88122994 A TW88122994 A TW 88122994A TW 88122994 A TW88122994 A TW 88122994A TW 495911 B TW495911 B TW 495911B
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layer
dielectric
forming
opening
darc
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TW88122994A
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Chinese (zh)
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Jen-Hua Yu
Syun-Ming Jang
Tsu Shih
Anthony Yen
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Taiwan Semiconductor Mfg
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Abstract

A forming method of silicon-oxynitride dielectric antireflection coating (DARC) layer or silicon oxide layer for passivation is disclosed in the present invention. The invented method is suitable for use after the dielectric layer is treated by a planarization polishing process (CMP process) and before a planarization process is conducted onto the conducting layer to form a contact window structure. At first, micro-scratch is generated after the dielectric layer on the semiconductor substrate is undergone with a polishing treatment. In the invention, a silicon-oxynitride DARC layer or silicon oxide layer for passivation is formed on the dielectric layer in order to fill up the micro-scratch. Then, by using a selective etching procedure, the first opening is fabricated in the passivation layer and the dielectric layer. After a conducting layer is formed and undergone with a planarization polishing procedure, interconnects can be formed inside the first opening, in which the passivation silicon-oxynitride DARC layer or silicon oxide layer is used as the stop layer of CMP process such that it is capable of avoiding the generation of micro-scratch in the dielectric layer.

Description

495911 五、發明說明(1) ~—- 【發明的領域】 ,本發明係有關於在半導體元件中使用抗反射塗佈層和 化學性機械研磨程序以製造接觸窗構造的方法,且特別是 有關於一種在層間介電層(ILD)或金屬層間介電層(IMD) 中’利用氮氧化矽或氧化矽形成之抗反射塗佈層和化學性 機械研磨程序來製造接觸窗構造的方法。 【習知技術】 化學性機械研磨(CMP)平坦化程序,係用來弄平半導 體元件中的介電層和磨低金屬層高度的。然而,這些CMp 私序會使"電層產生微刮痕(m i c r 〇 s c r a t c h e s ),造成光學 微影效能的降低並產生元件缺陷。本案發明人即已發現後 繽在第8 A至8 D圖所示的各項缺點。 第8A圖顯示對基底10上金屬線211上方的介電層214施 行一化學性機械研磨(CMP)程序2〇9。第8B圖則顯示曰在^ 程序之後’本案發明人所發現的微刮痕216。 其次,在介電層214和微刮痕216上,形成一有機物底 部抗反射塗佈(organic BARC)層218和一光阻層224。然 後,對organic BARC層218和光阻層224施行一曝光程g, 用以定義出一光阻開口y5(如虛線所示者)。其"中,1本案 發明人所發現的一個問題即在於,微刮痕所造成的反射效 應會使光阻圖案劣化。 接著,在介電層214中蝕刻出一接觸開口 226。然後, 去除上述的光阻層224。 、495911 V. Description of the invention (1) ~-[Field of the invention] The present invention relates to a method for manufacturing a contact window structure using an anti-reflection coating layer and a chemical mechanical polishing process in a semiconductor device, and particularly there is A method for manufacturing a contact window structure in an interlayer dielectric layer (ILD) or a metal interlayer dielectric layer (IMD) using an anti-reflective coating layer formed of silicon oxynitride or silicon oxide and a chemical mechanical polishing process. [Known Technology] A chemical mechanical polishing (CMP) planarization process is used to flatten the dielectric layer and reduce the height of metal layers in semiconductor devices. However, these CMP private sequences will cause micro scratches (m i c r 0 s c r a t c h e s) in the electrical layer, resulting in a reduction in optical lithography performance and component defects. The inventors of this case have discovered the shortcomings of Houbin in Figures 8A to 8D. FIG. 8A shows a chemical mechanical polishing (CMP) process 209 performed on the dielectric layer 214 over the metal line 211 on the substrate 10. FIG. 8B shows the micro scratches 216 discovered by the inventor of the present invention after the procedure. Next, on the dielectric layer 214 and the micro-scratch 216, an organic bottom anti-reflection coating (organic BARC) layer 218 and a photoresist layer 224 are formed. Then, an exposure range g is performed on the organic BARC layer 218 and the photoresist layer 224 to define a photoresist opening y5 (shown as a dotted line). Among them, one of the problems found by the inventors of this case is that the reflection effect caused by the micro-scratch can deteriorate the photoresist pattern. Next, a contact opening 226 is etched into the dielectric layer 214. Then, the photoresist layer 224 is removed. ,

495911 五、發明說明(2) 230 中 序 如第8C圖中所示者,形成一阻障層2 28和一金屬層 ’覆於介電層214表面上並填入接觸開口226中。其 阻障層2 2 8和金屬層2 3 0會填入部分的微刮痕2丨6中。 第8D圖係顯示對金屬層2 3 0和阻障層2 28施行一 CMP移 用以形成金屬插塞3 2 3。然而,微刮痕2 1 β中仍填有金 屬層2 3 0和阻障層2 2 8。這些被填滿的微刮痕2 1 6便可能產 生元件缺陷(defect)、與重疊的金屬導線發生短路、以及 產生光學缺陷。 甚者,對於金屬層所施行的CMP處理也會產生新的微 刮痕’這些新的微刮痕也會導致類似的問題。 因此,有必要發展一種新的製程方法,以避免在製作 半導體元件接觸窗構造的C Μ P程序時,產生非期望的微刹 痕於介電層中。 必須克服上述諸多不足的重要性可由有關此一課題的 大量技術研發得到明證,其發表於相關的專利和技術文獻 上。在專利方面最為接近且顯然相關的技術研發可見於美 國專利第5,766,974 號(Sardella) - Method of making a dielectric structure for facilitating overetching of metal without damage to inter-level dielectric,其揭示一種在層間介電層頂端具有一薄氮氧 化矽層的積體電路,以提供一餘刻終止層而阻止金屬層被 過度蝕刻。美國專利第5, 767, 0 1 8號(Bel 1)揭示了 一種使 用抗反射塗佈(ARC)層的複晶矽蝕刻製程。美國專利第 5,354,712 號(Ho)-Method for forming interconnect495911 V. Description of the invention (2) 230 Preface As shown in FIG. 8C, a barrier layer 2 28 and a metal layer are formed on the surface of the dielectric layer 214 and filled into the contact opening 226. The barrier layer 2 2 8 and the metal layer 2 3 0 will fill part of the micro scratches 2 丨 6. FIG. 8D shows that a CMP process is performed on the metal layer 230 and the barrier layer 28 to form a metal plug 3 2 3. However, the micro-scratch 2 1 β is still filled with the metal layer 2 3 0 and the barrier layer 2 2 8. These filled micro scratches 2 1 6 may cause component defects, short circuits with overlapping metal wires, and optical defects. In addition, the CMP process applied to the metal layer also generates new micro-scratches. These new micro-scratches also cause similar problems. Therefore, it is necessary to develop a new process method to avoid the occurrence of undesired micro-brake marks in the dielectric layer when the CMP process of the semiconductor device contact window structure is fabricated. The importance of overcoming many of the above-mentioned deficiencies can be confirmed by a large number of technological developments on this subject, which are published in relevant patents and technical literature. The closest and obviously related technology development in patents can be found in US Patent No. 5,766,974 (Sardella)-Method of making a dielectric structure for facilitating overetching of metal without damage to inter-level dielectric, which reveals an inter-layer dielectric The integrated circuit with a thin silicon oxynitride layer on top of the dielectric layer provides a stop layer for a while and prevents the metal layer from being over-etched. U.S. Patent No. 5,767,018 (Bel 1) discloses a polycrystalline silicon etching process using an anti-reflection coating (ARC) layer. US Patent No. 5,354,712 (Ho)-Method for forming interconnect

495911 五、發明說明(3) structures for integrated circuits 則教導了使用經化 學性機械研磨的介電層。美國專利第5,6 74,784號(了31^等 人)揭示一種形成研磨終止層以用於CMp程序的方法。 【發明的概述】 有鑑於此,本發明之一個目的,在提供一種使用氮氧 化矽(Si ON)層以覆蓋介電層上經化學性機械研磨處理後所 產生微刮痕的方法。 本發明另一個目的,在提供一種使用介電質抗反射塗 佈(DARC)氮氧化矽層,以避免在形成接觸窗 構造的製程中因為利用化學性機械研磨處 理¥電層而在介電層中產生微刮痕。 成上述和其他目的,本發明提出一種在化學性機 二以妒成=2 ί理之後且在施行平坦化研磨處理導電層而 石夕芦或J構造之前,於介電層上形成保護用氮氧化 祖i =奋妒^ S的方法。本發明具有兩個適用於保護層20 來(1)氮氧化矽(Si〇N)和(2)氧化矽。本發明 層以用於ί 2化:介電質抗反射塗佈(DARC)㈣氧化石夕 曰々二作接觸窗(con tact/via)開口的方法如下。 ^ 介電層14覆於一半導體構造10上,此一介雷展 ie。/ ;1電層14上,藉以填滿介電層14中的微刮1 ί二程序 厅形成者。形成一光阻層24覆於前述DARC層 495911 五、發明說明(4) 上。對光阻層24施行曝光和顯影程序,以製作出一第一光 阻開口26。然後,、經由第一光阻開口26而依序敍 化 矽DARC層20和介電層14,以形成一第一開口28。此第一開 口可顯露出基底上的接觸區域或基底上的導線。接著,I ^光阻層24。形成-導電層3〇(例如是—金屬層)覆蓋在氮 氧L石夕DARC層20上並填滿第-開口28。然後對導電層別施 行化學性機械研磨(CMP)處理,以去除氮氧化梦以…層⑼ 電層30,而留下其填在第一開口28中的部分形成 =連=線(interconnect)32,其中,氮氧化石夕darc42〇係 、以作為CMP處理之終止層,藉此該氮氧化石夕darc層可用 ί ΐ i在ΐ電層14中產生微刮痕。在發明概述中的參考標 =非用來限制本發明的專利範g,*僅係為了更加明瞭 ^明之内涵。如前所述者,本發明的保護層2〇可以電聚 化甲乳相沈積程序形成的氧化矽層代替之。495911 V. Description of the invention (3) Structures for integrated circuits teaches the use of chemically mechanically polished dielectric layers. U.S. Patent No. 5,6,74,784 (31, et al.) Discloses a method for forming a grinding stop layer for use in CMP procedures. [Summary of the Invention] In view of this, it is an object of the present invention to provide a method for using a silicon oxynitride (Si ON) layer to cover a micro scratch generated by a chemical mechanical polishing process on a dielectric layer. Another object of the present invention is to provide a dielectric anti-reflective coating (DARC) silicon oxynitride layer to avoid the use of chemical mechanical polishing treatment on the dielectric layer in the process of forming the contact window structure. Micro scratches occur. To achieve the above and other objectives, the present invention proposes a method for forming protective nitrogen on a dielectric layer after chemically treating the energetic layer = 2 and before performing a planarization polishing treatment on the conductive layer and before Shi Xilu or J structure. Oxidation ancestor i = envy ^ S method. The present invention has two (1) silicon oxynitride (SiON) and (2) silicon oxide suitable for the protective layer 20. The method of the present invention is as follows: A method for making a dielectric layer anti-reflection coating (DARC), oxidized stone, or a contact opening (con tact / via) is as follows. ^ A dielectric layer 14 is overlaid on a semiconductor structure 10, which is a dielectric layer. /; 1 on the electrical layer 14, so as to fill the micro-scratch in the dielectric layer 14. A photoresist layer 24 is formed to cover the aforementioned DARC layer 495911 V. Invention description (4). An exposure and development process is performed on the photoresist layer 24 to form a first photoresist opening 26. Then, the silicon DARC layer 20 and the dielectric layer 14 are sequentially described through the first photoresist opening 26 to form a first opening 28. This first opening may expose a contact area on the substrate or a wire on the substrate. Next, I ^ photoresist layer 24. A conductive layer 30 (for example, a metal layer) is formed to cover the nitrogen oxide L stone layer DARC layer 20 and fill the first opening 28. Then, a chemical mechanical polishing (CMP) process is performed on the conductive layer to remove the oxynitride dream and to form a layer ⑼ of the electrical layer 30 while leaving a portion filled in the first opening 28 to form an interconnect 32 Among them, the oxynitride darcan 42c is used as a termination layer of the CMP process, whereby the oxynitride darcan can be used to generate micro scratches in the galvanic layer 14. The reference mark in the summary of the invention = is not used to limit the patent scope of the present invention, * is only for better understanding of the connotation. As mentioned above, the protective layer 20 of the present invention may be replaced by a silicon oxide layer formed by an electropolymerization of a methyl emulsion phase deposition process.

本發明了提供下列的優點。本發明的保護用氮氧化矽 、(或PE-氧化矽)層2〇提供了極隹的抗反射特性,特別 =μ用於冰I外線(DUV)光學微影製程時。本發明的DARC 二I免除使用有機物BARC的需要。與SIN ARC層相比較, 本I明具有較佳的抗反射特性。 m &再者,本發明的氮氧化矽層可填滿先前之化學性機械 研磨平坦化處f程序在介電層中造成的微刮痕。. 本發明的氮氧化矽DARC層更是對金屬層施行CMp處理 M: f佳的研磨終止層。該氮氧化矽DARC層可避免因為化學 性機械研磨程序而產生微刮痕。The present invention provides the following advantages. The protective silicon oxynitride (or PE-silicon oxide) layer 20 of the present invention provides extremely high anti-reflection characteristics, especially when used in the ice lithography (DUV) optical lithography process. The DARC II of the present invention eliminates the need to use organic BARC. Compared with the SIN ARC layer, the present invention has better anti-reflection characteristics. m & Furthermore, the silicon oxynitride layer of the present invention can fill the micro-scratches caused by the previous chemical mechanical polishing planarization process in the dielectric layer. The silicon oxynitride DARC layer of the present invention is a CMP treatment applied to the metal layer. The polishing termination layer is excellent at M: f. This silicon oxynitride DARC layer avoids micro-scratching due to chemical mechanical polishing procedures.

第7頁 五 發明說明(5) 層 ,,個方面,本發明的氮氧化 Rc 或鼠化石夕/氮氧化石夕疊層。 μ於鼠化石夕 ^γ\. rjt t :;已知的製程技術本發明可獲致這些 了解本發明』點和所附的圖式,可以更進-步 【圖式之簡單說明】 為了讓本發明之上述和 明顯易懂,下文特舉出若干 詳細說明如下,其中相同的 區域、和部分: 其他目的、特徵、及優點能更 實施例,並配合所附圖式,作 參考標號代表著相ί§1的單元、Page 7 5 Description of the invention (5) Layers, in one aspect, the oxynitride Rc or rat fossil / nitroxite stack of the present invention. μ 于 Mouse fossil evening ^ γ \. rjt t:; Known process technology The present invention can achieve these understanding of the present invention "points and attached drawings, can be further-step [Simplified description of the drawings] In order to make this The above-mentioned invention of the invention is obvious and easy to understand. Here are some detailed descriptions as follows, among which the same areas, and parts: other purposes, features, and advantages can be further embodiment, and in conjunction with the attached drawings, reference numerals represent phases §1 unit,

第1至6圖為一系列剖面圖,係繪示根據本發明製造氮 氧化矽DARC層和接觸窗開口的方法; 第7圖係一剖面圖,顯示根據本發明一個較佳實施 例’其中第一開口係一雙鑲崁式(dual damascene)構造; 以及 第8A至8D圖為一系列剖面圖,係繪示以習知方法形成 接觸窗開口’其中因為化學性機械研磨處理所產生的微刮 痕會使得光學效能(Photo performance)劣化。 【較佳實施例的詳細說明】 在下面的說明中’將提供許多明確而詳細的數值,像 是流速、壓力設定、厚度等,以更完善地了解本發明。然 而很明顯地,熟悉此技藝人士並不需要這些細節即可成功Figures 1 to 6 are a series of cross-sectional views showing a method for manufacturing a silicon oxynitride DARC layer and a contact window opening according to the present invention; Figure 7 is a cross-sectional view showing a preferred embodiment according to the present invention, wherein One opening is a pair of dual damascene structures; and Figures 8A to 8D are a series of cross-sectional views showing the formation of contact window openings in a conventional manner. Among them, micro-scratching due to chemical mechanical polishing treatment The marks may deteriorate the photo performance. [Detailed description of the preferred embodiment] In the following description, a number of clear and detailed values will be provided, such as flow rate, pressure setting, thickness, etc. to better understand the present invention. However, it is clear that those skilled in the art do not need these details to succeed

495911 五、發明說明(6) 施行本發明。另一方面,為了不至於模糊了本發 點’已經廣為周知的製程即不再予 熟悉此技藝人士所知者,說明書中 兄::二’: 保持:同的莫耳百分比,以適應於不同尺; = 來 如下用於接觸窗開口之氮氧化物Rc層的形成方法將說明 如第1圖所示者,形成—介電層14覆於一半 10上。該介電層係一層間介電(ILD)層屬岸2 電UMD)層。亦即,ILD層可形成於一晶圓或/他屬層^ FETs上。並且,若當作IMD層,該介電層可^、 牛像疋 上。本案發明人發現,使用〇3_TE〇s程序形成之氧L 低介電常數(l〇w-k)之介電材料特別容易在介電声 或 層施行化學性機械研磨處理步驟時產生刮痕。Β σ金屬 對介電層“施行化學性機械研磨處理。 機;Η二_ ♦本案發明人注意到了一個問題:上述的化與祕 機械研磨處理常常會使介電層“中產生微刮痕i :性 刮痕16的深度可能介於300至500A。 石二微 ,:關鍵步驟中,第2圖顯示了本發明的保護 Φ 所制Ϊ,明的第一個實施例中,該保護層係由氮氧介。 所衣成。此一氮氧化矽^眈層2〇係形成在介電層"^化矽 PF --另/卜在本發明的第二個實施例中,該保護層係^495911 V. Description of the invention (6) The invention is implemented. On the other hand, in order not to obscure the point of origin, 'the already well-known process is no longer known to those skilled in the art, the brother in the description :: two': keep: the same mole percentage to adapt to Different scales; = The method for forming the oxynitride Rc layer used for the contact window opening will be described below. As shown in FIG. 1, a dielectric layer 14 is formed on a half 10. The dielectric layer is an interlayer dielectric (ILD) layer and is a shore 2 electric UMD layer. That is, the ILD layer may be formed on a wafer or / other layer ^ FETs. In addition, if used as an IMD layer, the dielectric layer can be placed on a bull's head. The inventors of the present case have found that the dielectric material using the low dielectric constant (10w-k) of oxygen L formed by the 03_TEOS procedure is particularly prone to generate scratches when the dielectric acoustic or layer is subjected to a chemical mechanical polishing treatment step. Β σ metal performs a chemical mechanical polishing treatment on the dielectric layer. Machine; Η 二 _ ♦ The inventor of this case noticed a problem: the above-mentioned chemical and mechanical polishing treatment often causes micro-scratches in the dielectric layer. : The depth of the sexual scratch 16 may be between 300 and 500A. Shi Erwei: In the key step, Figure 2 shows the protection of the present invention. In the first embodiment of the invention, the protective layer is mediated by nitrogen and oxygen. Dressed. The silicon oxynitride layer 20 is formed on the dielectric layer " siliconized silicon PF-In addition, in the second embodiment of the present invention, the protective layer is formed ^

化H石夕Λ製成。在後面的說明中將針對保護層為氣^ 曰者,但應知該保護層也可以是PE_氧化矽屉虱 此一氮氧化矽DARC層或PE_氧化矽層2〇填滿前迷^。 495911 五、發明說明(7) 中因為化學性機械研磨處理而產生的微刮痕。其中,該氮 氧化石夕DARC層係利用電漿加強化學氣相沈積(PECVD)程序 所形成者。 此氮氧化矽DARC層20具有若干重要的性質。第一、氮 氧化石夕層可填進微刮痕中。第二、利用本發明方法所形成 的氮氧化矽層2 0具有優異的抗反射特性。第三、此氮氧化 矽層是一極佳的CMP程序終止層,其可避免CMP程序施行過 頭而刮傷下面的介電層。Made of fossil stone Xi Λ. In the following description, the protective layer is referred to as gas, but it should be understood that the protective layer may also be PE_silicon oxide, a silicon oxynitride DARC layer or a PE_silicon oxide layer. . 495911 V. Description of the invention (7) Micro scratches due to chemical mechanical grinding. Among them, the oxynitride DARC layer was formed by a plasma enhanced chemical vapor deposition (PECVD) process. This silicon oxynitride DARC layer 20 has several important properties. First, the oxynitride layer can be filled into the micro-scratch. Second, the silicon oxynitride layer 20 formed by the method of the present invention has excellent anti-reflection characteristics. Third, this silicon oxynitride layer is an excellent CMP process termination layer, which can prevent the CMP process from being performed too much and scratching the underlying dielectric layer.

該氮氧化矽DARC層的厚度最好係介於3〇〇至1400 A (tgt = 600A),於波長248nm條件下的折射率最好係介於 2至2 · 3 ’並且消光係數係介於〇 · 6至〇 · 7,而莫耳濃度係分 別為45% Si 、 38% 0 、 7% N 、和1〇% η 。The thickness of the silicon oxynitride DARC layer is preferably between 300 and 1400 A (tgt = 600A), and the refractive index at a wavelength of 248 nm is preferably between 2 and 2 · 3 'and the extinction coefficient is between 0.6 to 0.7, and the Mohr concentrations are 45% Si, 38% 0, 7% N, and 10% η, respectively.

在本發明的第一個實施例中,係利用一電漿加強化學 氣相沈積(PECVD)程序來形成此一氮氧化矽^以層“,其 ,意調整反應參數來降低沈積速率,以獲得薄而均勻的氮 氧化石夕層而提供較佳的光學微影特徵尺寸控制,例如,係 在溫度介於300至400〇C,壓力介於5至6Torr,以及反應氣 體々丨 l 速分別為 SiH4 :60 至 80 seem、N20 :90 至 11〇 sccm、 He : 1900至2300 seem條件下進行的。 本發明第二個貫施例的p E —氧化矽層的厚度則最好係 介於500 至200 0 A。 ' 第3圖顯示一形成在氮氧化矽DARC層上的光阻層24。 此一光阻層24的厚度最好是介於600〇至1〇〇〇()人,且 最好是一深紫外線(DUV)光阻層。 第10頁 495911 五、發明說明(8) 仍請參見第3圖’對光阻層2 4施行曝光和顯影程序, 以製作出一第一光阻開口 2 6,該光阻層2 4最好係使用波長 介於245至264nm的I-線深紫外光源(卜line DUV Hght)來 進行曝光的。 如第4圖所示者,經由第一光阻開口 2 6而依序蝕刻氮 氧化矽DARC層20和介電層14,以形成一第一開口28。此第 一開口 28的尺寸係介於〇· 2至〇. 4mm。 上述弟一開口可以有許多種型式,例如,如第7圖所 示者,第一開口可以是雙鑲崁式(dual damascene shaped)構造開口128,且内連導線132是雙鑲崁式内連導 線。該第一開口可利用多階段蝕刻/微影程序來製作,且 5亥第一開口可顯露出該基底上的接觸區域或該基底上的導 線。 如第5圖所示者,接著去除光阻層24。 其a ’形成一導電層(例如是一金屬層)3〇覆蓋在該氮 氧化矽DARC層20上,並填滿該第一開口。此一金屬層可以 是單獨的鎢層’或者是像阻障/黏著層(例如TiN)與導電層 (例如鎢層)所構成的多層構造。基本上,導電層3 〇的組成 (composition)可依該層究竟係IDL層中與基底連接的接觸 窗(contact) ’或係IMD層中與金屬線連接的接觸插塞(viaIn the first embodiment of the present invention, a plasma enhanced chemical vapor deposition (PECVD) process is used to form the silicon oxynitride layer. The reaction parameters are adjusted to reduce the deposition rate to obtain A thin and uniform layer of oxynitride provides better optical lithography feature size control. For example, the temperature is between 300 and 400 ° C, the pressure is between 5 and 6 Torr, and the reaction gas velocity is SiH4: 60 to 80 seem, N20: 90 to 110 cm, He: 1900 to 2300 seem. The thickness of the p E-silicon oxide layer in the second embodiment of the present invention is preferably between 500 and 500. To 200 A. 'FIG. 3 shows a photoresist layer 24 formed on a silicon oxynitride DARC layer. The thickness of this photoresist layer 24 is preferably between 600 and 1,000 (100), and Preferably, a deep ultraviolet (DUV) photoresist layer. Page 10 495911 V. Description of the invention (8) Still referring to FIG. 3 'Exposing and developing the photoresist layer 2 4 to produce a first light Blocking opening 26, the photoresist layer 2 4 is preferably an I-line deep ultraviolet light source with a wavelength between 245 and 264 nm (line DU V Hght) for exposure. As shown in FIG. 4, the silicon oxynitride DARC layer 20 and the dielectric layer 14 are sequentially etched through the first photoresist opening 26 to form a first opening 28. This first The size of an opening 28 is between 0.2 and 0.4 mm. The above-mentioned one opening can have many types, for example, as shown in FIG. 7, the first opening can be a dual damascene shaped The opening 128 is structured, and the interconnecting wire 132 is a double inlay-type interconnecting wire. The first opening can be made by a multi-stage etching / lithography process, and the first opening can expose a contact area on the substrate or The wires on the substrate. As shown in FIG. 5, the photoresist layer 24 is removed. A ′ forms a conductive layer (for example, a metal layer) 30 and covers the silicon oxynitride DARC layer 20 and fills it. The first opening is filled. The metal layer may be a single tungsten layer or a multilayer structure composed of a barrier / adhesive layer (such as TiN) and a conductive layer (such as a tungsten layer). Basically, the conductive layer 3 〇 The composition can be determined by whether the layer is a contact window (c ontact) ’or the contact plug (via

Plug)而變化。 第5圖顯示對導電層30施行化學性機械研磨(CMP)處 理’以去除氮氧化矽D ARC層20上方的導電層30,而留下其 填在第一開口28中的部分形成内連導線32 (亦即con tact或Plug). FIG. 5 shows that a chemical mechanical polishing (CMP) process is performed on the conductive layer 30 to remove the conductive layer 30 above the silicon oxynitride D ARC layer 20 while leaving a portion filled in the first opening 28 to form interconnecting wires. 32 (i.e. con tact or

第11頁 495911 五、發明說明(9) via plug)。其中,氮氧化矽DARC層20係用以作為CMP處理 之終止層,藉此該氮氧化矽D ARC層20可用以避免在介電層 1 4中產生微刮痕。 第7圖則顯示另外的實施例,其中第一開口係雙鑲崁 式開口。導電層形成了雙鑲崁式内連導線丨32。其中,本 發明的氮氧化矽DARC層120提供了如前所述的功能。 吾人均知,許多文獻已敘述了應用於積體電路元件製 造程序中通用技術的詳細内 用到製造本發明構造的製程 驟可利用商業上可獲得的積 體了解本發明内容所需,例 術來作說明的。然隨著製程 條件做熟悉此技藝人士顯而 容,那些技術一般而言均可應 中。再者,這些製程的個別步 體電路製造機台來完成。為具 子中的技術資料係基於現有技 技術未來的發展,仍可對上述 易見且適當的調整。Page 11 495911 V. Description of the invention (9) via plug). Among them, the silicon oxynitride DARC layer 20 is used as a termination layer of the CMP process, whereby the silicon oxynitride D ARC layer 20 can be used to avoid micro scratches in the dielectric layer 14. Fig. 7 shows another embodiment, in which the first opening is a double inlay opening. The conductive layer forms a double inlay-type interconnecting wire. Among them, the silicon oxynitride DARC layer 120 of the present invention provides the functions described above. As everyone knows, many documents have described the detailed application of general technology used in the manufacturing process of integrated circuit components. The manufacturing steps used to manufacture the structure of the present invention can be obtained by using commercially available products to understand the content of the present invention. For illustration. However, as process conditions become apparent to those skilled in the art, those techniques are generally applicable. Furthermore, the individual steps of these processes are performed by the body circuit manufacturing equipment. For the technical information in this example is based on the future development of existing technology, the above-mentioned visible and appropriate adjustments can still be made.

个I叨雖然已以若+鉍 用以限定本發明,任何心::;=如上’然其並非 精珅和範圍内,當可作此 π者在不脫離本發明之 保護範圍當視後附之申動與潤飾,因此本發明之 τ印專利範圍所界定者為準。 <1Although I have used if + bismuth to define the present invention, any intention ::; = as above, but it is not within the scope and scope, and those who can do this without departing from the scope of the present invention should be attached Application and retouching, therefore, the scope of the τ India patent scope of the present invention shall prevail. < 1

Claims (2)

495911 六、申請專利範圍 1 · 一種形成氮氧化矽(Si ON)介電質抗反射塗佈(DARC) 層而用於製作接觸窗(contact/via)的方法,包括下列步 驟: (a) 形成一介電層覆於一半導體構造上; (b) 形成一氮氧化矽之介電質抗反射(dARC)層覆於該 介電層上,該氮氧化矽DARC層係使用電漿加強化學氣相沈 積(PECVD)程序所形成者; (c) 形成一光阻層覆於該DARC層上; (d )對該光阻層施行曝光和顯影程序,以製作出一第 一光阻開口; (e)經由該第一光阻開口而依序蝕刻該氮氧化矽^人^^ 層和該介電層,以形成一第一開口; (f )去除該光阻層; (g) 形成一導電層覆蓋在該氮氧化矽DARC層上並填滿 該第一開口;以及 、 (h) 對該導電層施行化學性機械研磨(CMp)處理,以去 除該氮氧化矽DARC層上方的該導電層,而留下其填在該第 一開口中的部分形成内連導線(interc〇nnect),其中5 氧化矽DARC層係用以作為CMP處理之終止層,藉此該氮^ 化矽DARC層可用以避免在該介電層中產生微刮痕氧 (microscratches) 〇 2.如申請專利範圍第丨項所述一種形成氮氧化矽 質抗反射塗佈層而用於製作接觸窗的方法,其中: 步驟⑻更包括對該介電層施行一化學性機械研κ495911 VI. Application Patent Scope 1 · A method for forming a silicon nitride oxide (Si ON) dielectric anti-reflection coating (DARC) layer for making contact / via, including the following steps: (a) forming A dielectric layer covers a semiconductor structure; (b) a dielectric anti-reflection (dARC) layer forming a silicon oxynitride is formed on the dielectric layer; the silicon oxynitride DARC layer uses a plasma to strengthen the chemical gas Formed by a phase deposition (PECVD) process; (c) forming a photoresist layer overlying the DARC layer; (d) performing exposure and development procedures on the photoresist layer to make a first photoresist opening; ( e) sequentially etching the silicon oxynitride layer and the dielectric layer through the first photoresist opening to form a first opening; (f) removing the photoresist layer; (g) forming a conductive A layer covering the silicon oxynitride DARC layer and filling the first opening; and, (h) performing a chemical mechanical polishing (CMp) treatment on the conductive layer to remove the conductive layer above the silicon oxynitride DARC layer While leaving a portion filled in the first opening to form an interconnecting wire (interc〇nnect), of which 5 The siliconized DARC layer is used as a termination layer for the CMP process, so that the silicon nitrided DARC layer can be used to avoid the generation of microscratches in the dielectric layer. 2. As described in the patent application No. 丨The method for forming a silicon oxynitride anti-reflective coating layer for fabricating a contact window, wherein: step ⑻ further includes performing a chemical mechanical research on the dielectric layer 第13頁 495911 六、申請專利範圍 理,其中該化學性機械研磨處理造成在該介電層 刮痕;並且 座生微 步驟(C )更包括填在該介電層之微刮痕中的該 矽DARC層。 Μ氣乳化 3·如申請專利範圍第1項所述一種形成氮氧化矽介 質抗反射塗佈層而用於製作接觸窗的方法,其中該開1口'一 雙鑲崁式(dual damascene)開口且該内連導線係等二=係 内連導線。 ’、議坎式 4·如申請專利範圍第1項所述一種形成氮氧化石夕介 質抗反射塗佈層而用於製作接觸窗的方法,其中該介;1雷' 係一層間介電層(interlevel dielectric)或是_金屬展曰 間介電層(inter metal dielectgric)。 ” ’層 5·如申請專利範圍第丨項所述一種形成氮氧化矽介 質抗反射塗佈層而用於製作接觸窗的方法,其中該第一电 口係顯露出該基底上的接觸區域或該基底上的導線。崎 6·如申請專利範圍第1項所述一種形成氮氧化碎介 質抗反射塗佈層而用於製作接觸窗的方法,其中該氮&电 石夕DARC層的厚度係介於3〇〇至1 400 A,於波長248ηϋ: =, 射率係介於2至2· 3,消光係數則係介於〇· 6至〇· 7,且莫斤 濃度係分別為45% Si、38% 0、7% Ν、1 〇% η。 、耳 7·如申請專利範圍第1項所述一種形成氮氧化石夕介 質抗反射塗佈層而用於製作接觸窗的方法,其中該光阻 的厚度係介於60 00至1 000 0 Α。 ~ &層 8·如申請專利範圍第1項所述一種形成氮氧化石夕介電Page 13 495911 6. The scope of the patent application, in which the chemical mechanical polishing treatment causes scratches in the dielectric layer; and the micro-step (C) of the formation further includes the filling in the micro-scratch of the dielectric layer. Silicon DARC layer. M gas emulsification 3. A method for forming a contact window by forming an anti-reflection coating layer of a silicon oxynitride medium as described in item 1 of the scope of the patent application, wherein the opening is a double damascene opening And the interconnected wires are equal to two = are interconnected wires. ', Yikan type 4. · A method for forming a contact window by forming an anti-reflection coating layer of oxynitride dielectric as described in item 1 of the scope of the patent application, wherein the dielectric; 1 thunder' is an interlayer dielectric layer (Interlevel dielectric) or _ metal exhibition called inter metal dielectgric. "Layer 5 · A method for forming a contact window by forming an anti-reflection coating layer of a silicon oxynitride dielectric as described in item 丨 of the patent application range, wherein the first electrical port exposes a contact area on the substrate or The wire on the substrate. Qi 6. A method for forming a contact window by forming an anti-reflection coating layer of a nitrogen oxide crushing medium as described in item 1 of the scope of patent application, wherein the thickness of the nitrogen & calcium carbide DARC layer is Between 300 and 1 400 A, at a wavelength of 248ηϋ: =, the emissivity is between 2 and 2.3, the extinction coefficient is between 0.6 and 0.7, and the concentration of Mojin is 45%, respectively. Si, 38% 0, 7% N, 10% η, ear 7. A method for forming a contact window by forming an anti-reflection coating layer of a oxynitride dielectric as described in item 1 of the patent application scope, wherein The thickness of the photoresist is between 60,000 and 1 000 0 A. ~ & Layer 8 · A dielectric forming oxynitride as described in item 1 of the scope of patent application 495911495911 質抗反射塗佈層而用於製作接觸窗的方法,其中使用波長 介於245至264ηιη的I-線深紫外光源(I —line DUV light)^ 該光阻層進行曝光程序的。 併上9 ·如申明專利範圍第1項所述一種形成氮氧化石夕介電 質抗反射塗佈層而用於製作接觸窗的方法,其中該第一光 阻開口的尺寸係介於0· 2至〇. 4mm。 1 〇. 一種形成氮氧化矽介電質抗反射塗佈層而用於製 作接觸窗的方法,包括下列步驟: (a) 形成一介電層覆於一半導體構造上; (b) 對該介電層施行一化學性機械研磨處理,其中該 4 化學性機械研磨處理造成在該介電層中產生微刮痕; 八。(c)形成+—氣氧化矽之介電質抗反射(DARC)層覆於該 二電層上,藉此該氮氧化矽DARC層填滿了步驟(b)化學性 $械研磨處理後於該介電層中產生的微刮痕,該氮氧化矽 RC層係使用電聚加強化學氣相沈積(pEcvD)程序所形 者; (d)形成一光阻層覆於該DARC層上;A method for fabricating a contact window by using an anti-reflective coating layer, wherein the photoresist layer is subjected to an exposure process using an I-line DUV light having a wavelength between 245 and 264 nm. A method for forming a contact window by forming a dielectric anti-reflective coating layer of oxynitride as described in item 1 of the declared patent scope, wherein the size of the first photoresist opening is between 0 · 2 to 0.4 mm. 10. A method for forming a silicon nitride oxide dielectric anti-reflective coating layer for fabricating a contact window, comprising the following steps: (a) forming a dielectric layer overlying a semiconductor structure; (b) forming a dielectric layer on the semiconductor structure; The electrical layer is subjected to a chemical mechanical polishing process, wherein the 4 chemical mechanical polishing process causes micro-scratches in the dielectric layer; eight. (C) forming a dielectric anti-reflection (DARC) layer of silicon oxide gas on the two electrical layers, thereby filling the silicon oxynitride DARC layer with step (b) after chemical polishing The micro-scratch generated in the dielectric layer, the silicon oxynitride RC layer is formed using an electro-enhanced chemical vapor deposition (pEcvD) procedure; (d) forming a photoresist layer overlying the DARC layer; 一、(e)對該光阻層施行曝光和顯影程序,以製作出一第 ”光阻開口 ’該光阻層係使用波長介於245至264nm的I-線 沬紫外光源(I-line Duv light)來進行曝光的; (g) 去除該光阻層; (h) 形成一導電層覆蓋在該氮氧化矽DARC層上並填滿 (f )經由該第一光阻開口而依序蝕刻該氮氧化矽DARC 層和該介電層,以形成一第一開口;1. (e) Perform exposure and development procedures on the photoresist layer to make a "photoresist opening". The photoresist layer uses an I-line Duv light source (I-line Duv) with a wavelength of 245 to 264 nm. light) for exposure; (g) removing the photoresist layer; (h) forming a conductive layer covering the silicon oxynitride DARC layer and filling (f) sequentially etching the through the first photoresist opening A silicon oxynitride DARC layer and the dielectric layer to form a first opening; 第15頁 495911 六、申請專利範圍 該第一開口;以及 (i)對該導電層施行化學性機械研磨(CMP)處理,以去 除該氮氧化矽DARC層上方的該導電層,而留下其填在該第 一開口中的部分形成内連導線,其中該氮氧化矽DARC層係 用以作為CMP處理之終止層,藉此該氮氧化矽DARC層可用 以避免在該介電層中產生微刮痕。 11 ·如申請專利範圍第1 0項所述一種形成氮氧化石夕介 電質抗反射塗佈層而用於製作接觸窗的方法,其中該氮氧 化矽DARC層的厚度係介於30 0至1 40 0 A,於波長248nm下的 折射率係介於2至2 · 3,消光係數則係介於〇 · 6至0 · 7,且莫 耳濃度係分別為45% Si、38% 0、7% N、10% Η。 1 2·如申請專利範圍第1 〇項所述一種形成氮氧化石夕介 電質抗反射塗佈層而用於製作接觸窗的方法,其中該第一 光阻開口的尺寸係介於0.2至〇.4mm。 1 3·如申請專利範圍第1 〇項所述一種形成氮氧化石夕介 電質抗反射塗佈層而用於製作接觸窗的方法,其中該開口 係雙鑲崁式開口且該内連導線係雙鑲崁式内連導線。 lj·如申請專利範圍第10項所述一種形成氮氧化矽介 電質抗反射塗佈層而用於製作接觸窗的方法,其中該介電 層係一層間介電層(interlevel dieiectric)或是一金屬❶ 層間介電層(inter metal dielectgric),其係使用Page 15 495911 6. The first opening in the scope of patent application; and (i) performing a chemical mechanical polishing (CMP) treatment on the conductive layer to remove the conductive layer above the silicon oxynitride DARC layer and leave it A portion filled in the first opening forms an interconnecting wire, wherein the silicon oxynitride DARC layer is used as a termination layer of the CMP process, whereby the silicon oxynitride DARC layer can be used to avoid microscopic formation in the dielectric layer. Scratches. 11 · A method for forming a contact window by forming a dielectric anti-reflective coating layer of oxynitride as described in item 10 of the scope of patent application, wherein the thickness of the silicon oxynitride DARC layer is between 300 and 300 1 40 0 A, the refractive index at a wavelength of 248 nm is between 2 and 2 · 3, the extinction coefficient is between 0.6 and 0 · 7, and the Mohr concentration is 45% Si, 38% 0, 7% N, 10% Η. 1 2. A method for forming a contact window by forming a dielectric anti-reflective coating layer of oxynitride as described in Item 10 of the scope of patent application, wherein the size of the first photoresist opening is between 0.2 and 〇4mm. 1 3. A method for forming a contact window by forming a dielectric anti-reflective coating layer of oxynitride as described in item 10 of the scope of patent application, wherein the opening is a double inlay opening and the interconnecting wire It is a double inlay stub-type interconnecting wire. lj. A method for forming a contact window by forming a silicon oxynitride dielectric anti-reflective coating layer as described in item 10 of the scope of patent application, wherein the dielectric layer is an interlevel dieiectric or An intermetallic dielectric layer (inter metal dielectgric), which is used 03-TEOS程序形成之氧化物或低介電常數(1〇w — 料所製成。 晃材 15·如申請專利範圍第10項所述一種形成氮氧化矽介03-TEOS process to form oxides or low dielectric constant (10w-made of materials. Rock material 15 · A kind of silicon oxynitride formation as described in item 10 of the scope of patent application 第16頁 495911 六、申請專利範圍 電質抗反射塗佈層而用於製 開口係顯露出該基底上的;的方法,其中該第- -種形成氧化石夕介電質塗或/基底上的導線。 的方法,包括下列步驟··負塗佈層而用於製作接觸窗 (a) 形成一介電層覆於一半 (b) 對該介電層施行一化媳^仏上, 化學性機械研磨處 機居械研磨處理’其令該 ⑷形成一氧化石夕層覆於該介電電層二產生Λ刮痕' 使用電漿加強化學氣相沈積( ‘ ::石夕層係 氧化石夕層填滿該介電層中的微刮痕);…形成者,且該 (d)形成一光阻層覆於該氧化矽層上. (Ο對該光阻層施行曝光和顯二’ 一光阻開口; 尤才頌〜耘序,以製作出一第 (f)經由該第一光阻開口而依 介電層,以形成一第一開口· X彳該氧化石夕層和該 (g )去除該光阻層; (h)形成一導電層覆蓋在該氧 開口;以及 乳化石夕層上並填滿該第一 (〇對該導電層施行化學性 :該氧化矽層上方的該導電層,:=ρ)處理’以去 ::部分形成内連導線,其中該氧化矽;=該第-開口 處理之終止層,藉此該氧化 以作為CMP 產生微刮痕。 用以避免在該介電層中 17.如中請專利範圍第16項所述—種形成氧化石夕介電 mi 第17頁 495911 六、申請專利範圍 質塗佈層而用於製作接觸窗的方法,其中該介電層係一層 間介電層(interlevel dielectric)或是一金屬層間介電 層(inter metal dielectgric),其係使用 〇3 - TEOS 程序形 成之氧化物或低介電常數(1〇w — k)之介電材料所製成。 1 8 ·如申請專利範圍第1 6頊所述一種形成氧化矽介電 質塗佈層而用於製作接觸窗的万法,其中該氧化矽層的厚 度係介於500至2000 A。Page 16 495911 VI. Application for a patent range Electrostatic anti-reflection coating layer for making an opening to expose the substrate; a method in which the -th-forming an oxide stone dielectric coating or / on the substrate Of wires. The method includes the following steps: a negative coating layer is used to make a contact window (a) forming a dielectric layer and covering half (b) applying a chemical treatment to the dielectric layer; chemical mechanical polishing The mechanical polishing process' which causes the gadolinium to form a monolithic oxide layer overlying the dielectric layer and produces a Λ scratch '. Plasma is used to enhance chemical vapor deposition (' :: Shixi layered oxide layer is filled up) A micro-scratch in the dielectric layer); ... the former, and the (d) forms a photoresist layer overlying the silicon oxide layer. (0) exposes the photoresist layer and displays two photoresist openings You Caisong ~ Yun Xu, to make a (f) dielectric layer through the first photoresist opening to form a first opening. X 彳 the oxide layer and the (g) remove the A photoresist layer; (h) forming a conductive layer covering the oxygen opening; and an emulsified stone layer and filling the first (0) the conductive layer chemically: the conductive layer above the silicon oxide layer: = ρ) treatment to remove :: partially forming interconnecting wires, wherein the silicon oxide; = the termination layer of the-opening treatment, whereby the oxidation is performed as CMP produces micro-scratch. To avoid the dielectric layer 17. As described in the patent application No. 16-a kind of formation of oxidized stone dielectric dielectric p. 17 495911 6. Application of patent-quality coating layer and A method for making a contact window, wherein the dielectric layer is an interlevel dielectric or an inter metal diegric, which is an oxide or Made of a low dielectric constant (10w-k) dielectric material. 1 8 · A kind of silicon oxide dielectric coating layer for forming contact windows as described in the patent application No. 16 顼. Method, wherein the thickness of the silicon oxide layer is between 500 and 2000 A. 第18頁Page 18
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7183200B2 (en) 2003-04-28 2007-02-27 Fujitsu Limited Method for fabricating a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7183200B2 (en) 2003-04-28 2007-02-27 Fujitsu Limited Method for fabricating a semiconductor device

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