TW465034B - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- TW465034B TW465034B TW89117207A TW89117207A TW465034B TW 465034 B TW465034 B TW 465034B TW 89117207 A TW89117207 A TW 89117207A TW 89117207 A TW89117207 A TW 89117207A TW 465034 B TW465034 B TW 465034B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
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Abstract
Description
d 5 Ο 3飞案號891172(17__年月曰 修正____ 五、發明說明（1) [發明所屬之技術領域] 本發明有關於半導體裝置之製造方法，尤其有關於多層 配線之形成技術。 [習知之技術] 下面將參照圖1 1〜圖1 4用來說明作為習知之半導體裝置 之製造方法之形成多層化之配線和形成用以進行其間之電 連接之導電層（所謂之接觸插頭或插頭：plug)之形成方 法。圊1 1〜圖1 4之各圊是用以說明此種製造方法之縱向剖 面圖。另外，此處所說明之情況是圖1 4所示之半導體裝置 10P具有形成在矽基板1P上之MOS電晶體（圖中未顯示），用 以形成該MOS電晶體之源極/汲極區域之擴散層2P連接到形 成在該擴散層2 P之上方之配線層或配線5 p。因此，在圖j i 等之矽基板IP ’上述之MOS電晶體之詳細圖示加以省略， 圖中只顯示擴散層2 p。 首先’準備和製作為M〇S電晶體之矽基板1P(參照圖 11)。在矽基板1P之主面1SP内之指定區域形成擴散層2P。 其次’在矽基板1P之主面1SP之全面，形成厚度H31P之 層間絕緣層3 1 p。然後’形成從層間絕緣層31 P之露出表面 31SP到達上述之擴散層2p之接觸孔3〇?。 然後’如圖12所示，在接觸孔3〇p内和層間絕緣層31 p之 露出表面3 1 SP之全面’堆積導電性材料，藉以形成插頭形_ 成層41AP。 然後’如圖1 3所示’對層間絕緣層3丨p之上述表面3丨SP 上之插頭形成層4 1 AP進行蝕刻或深蝕刻，用來使上述之表d 5 Ο 3 Flying case number 891172 (17__year month and month revision ____) V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a technology for forming multilayer wiring. [Conventional Technology] The following will explain the formation of multilayer wiring and the formation of a conductive layer (so-called contact plug or (Plug: plug) formation method. Each of 11 to 14 is a longitudinal cross-sectional view for explaining such a manufacturing method. In addition, the case described here is that the semiconductor device 10P shown in FIG. 14 has a formation. A MOS transistor (not shown) on a silicon substrate 1P. A diffusion layer 2P for forming a source / drain region of the MOS transistor is connected to a wiring layer or wiring formed above the diffusion layer 2P. 5 p. Therefore, the detailed illustration of the above-mentioned MOS transistor in the silicon substrate IP of FIG. Ji and the like is omitted, and only the diffusion layer 2 p is shown in the figure. First, the silicon substrate 1P of the MOS transistor is prepared and fabricated. (Refer to Figure 11). A diffused layer 2P is formed in a designated area within the main surface 1SP of the plate 1P. Next, 'an interlayer insulating layer 3 1 p with a thickness of H31P is formed on the entire surface of the main surface 1SP of the silicon substrate 1P. Then, an exposure from the interlayer insulating layer 31 P is formed The surface 31SP reaches the contact hole 30 of the above-mentioned diffusion layer 2p. Then, as shown in FIG. 12, a conductive material is deposited in the contact hole 30p and the entire surface of the interlayer insulation layer 31p exposed surface 3 1 SP, Thereby, a plug-shaped layer 41AP is formed. Then, as shown in FIG. 13, the plug-forming layer 4 1 AP on the above-mentioned surface 3 丨 SP of the interlayer insulating layer 3 丨 p is etched or deeply etched to make the above table
89117207.ptc 第7頁 4 6 5 0 c / --塞號 89117207___年月日 修正____ 五、發明說明（2) 面3 1 SP露出。在該深蝕刻後使殘留在接觸孔3 〇 p内之上述 導電性材料成為插頭41p(厚度或高度為H41p) ^另外，在 上述之深#刻時’因為接觸孔3 〇p内之上述導電性材料之 一部份亦被蚀刻，所以插頭41p之頂部41Tp變成低於層間 絕緣層31Ρ之表面31SP。換言之，插頭4Ρ變成比層間絕緣 層31Ρ更薄（厚度Η41Ρ〈厚度Η31Ρ)。 其次’以覆蓋在層間絕緣層31 ρ和插頭4 1 ρ之全體之方式 堆積配線材料。然後’如圖丨4所示，使用平版印刷技術將 該配線材料圖型製作成指定之形狀，用來形成連接到插頭 41Ρ之配線層5Ρ。 [發明所欲解決之問題] 在習知之製造方法中’因為以上述方式對插頭形成層 4 1 A Ρ進行深敍刻用來形成插頭4 1 ρ，所以插頭41 ρ之頂部 4 1 TP變成低於層間絕緣層31 P之表面3 1 SP。因此，如圓】4 所示’不能獲得配線層5P之充分之涵蓋範圍，會在配線層 5P形成達到插頭41P之開口 5KP。 當形成有此種開口 5KP時，在與未形成有該開口 5KP之情 況比較時，插頭41P與配線層5P之接觸部份或接觸面積變月 小°因此’插頭41P和配線層5P之間容易產生斷線，而且 插頭41P和配線層5P之間之路徑之電阻會增大。 另外’在具有上述之開口 5KP之情況，當在配線層之 形成後於實施各個濕式處理時，藥液或溶液會進入上迷之 開口 5KP。例如在配線層5P之圖型製作時，作為遮罩之抗 银劑之除去液等會進入開口 5KP。此種藥液等會引起在^89117207.ptc Page 7 4 6 5 0 c / --Serial number 89117207 ___ month month day correction ____ 5. Description of the invention (2) The surface 3 1 SP is exposed. After this deep etching, the above-mentioned conductive material remaining in the contact hole 3 op is made into a plug 41p (thickness or height H41p) ^ In addition, at the time of the above-mentioned deep #etching, the above-mentioned conduction in the contact hole 3 op A part of the material is also etched, so the top 41Tp of the plug 41p becomes lower than the surface 31SP of the interlayer insulating layer 31P. In other words, the plug 4P becomes thinner than the interlayer insulating layer 31P (thickness Η41P <thickness Η31P). Next, the wiring material is deposited so as to cover the entirety of the interlayer insulating layer 31 ρ and the plug 4 1 ρ. Then, as shown in FIG. 4, the pattern of the wiring material is made into a specified shape using a lithographic technique to form a wiring layer 5P connected to the plug 41P. [Problems to be Solved by the Invention] In the conventional manufacturing method, 'because the plug formation layer 4 1 A P is deeply engraved in the above manner to form the plug 4 1 ρ, the top 4 1 TP of the plug 41 ρ becomes low. 3 1 SP on the surface of the interlayer insulating layer 31 P. Therefore, as indicated by circle] 4, the full coverage of the wiring layer 5P cannot be obtained, and an opening 5KP reaching the plug 41P will be formed in the wiring layer 5P. When such an opening 5KP is formed, the contact portion or contact area between the plug 41P and the wiring layer 5P becomes smaller when compared with the case where the opening 5KP is not formed. Therefore, it is easy to 'plug 41P and the wiring layer 5P A disconnection occurs, and the resistance of the path between the plug 41P and the wiring layer 5P increases. In addition, in the case of having the above-mentioned opening 5KP, when each wet process is performed after the formation of the wiring layer, the medicinal solution or solution will enter the opening 5KP of the fan. For example, when the pattern of the wiring layer 5P is made, the removal solution of the silver-resistant agent used as a mask will enter the opening 5KP. This medicinal solution will cause ^
891]7207.ptc 第8頁 4 6 50./; --ι案號89117207__年月..曰 铬；f.____ 五、發明說明⑶ ' 頭41P和配線層5p之上述接觸部份產生斷線。另外，上述 之藥液等會溶解插頭41P造成插頭41P之電阻變高。 如同圖15之縱向剖面圖所示之半導體裝置lip之方式， 當接觸孔3 0 P之直徑比較小時，構成插頭之上述導電性材 料會有不能完全充填到接觸孔3〇p内之情況。亦即，所# 成之插頭4 2 P在接觸孔3 0之中心部會有空洞4 2 K P。在此種 情況更容易由於藥液等而發生上述之斷線或高電阻化。 本發明用來解決上述之問題’其目的是提供可以改善構 成上述配線層之導電層之涵蓋範圍，減少斷線等問題之高 可靠度之半導體裝置之製造方法。 阿 [解決問題之手段] (1) 本發明之申請專利範圍第1項是一種半導體裝置之製 造方法，其特徵是所包含之製程有：（a)在基板上形成具有 接觸孔之電介質層；（b)在上述之接觸孔内形成接合上述 基板之第1導電層；和（c)利用濕式蝕刻’對上述之第i導 電層選擇性的除去從上述電介質層之與上述基板相反側之 表面起之指定厚度之部份。 (2) 本發明之申請專利範圍第2項之半導體裝置之製造方 法是在申請專利範圍第i項之半導體裝置之製造方法中， 在上述之製程（c )’將上述之濕式钱刻後所獲得之上述電 介質層之表面，設定成為與上述第】導電層之上述基板相 反側之頂部具有相同之高度位準。 (3) 本發明之申請專利範圍第3項之半導體裝置之製造方. 法是在申請專利範圍第1項之半導體裝置之製造方法中，891] 7207.ptc Page 8 4 6 50./; --ι Case No. 89117207__year month: chrome; f .____ 5. Description of the invention ⑶ 'The above-mentioned contact part of the head 41P and the wiring layer 5p breaks line. In addition, the above-mentioned chemical solution or the like will dissolve the plug 41P and increase the resistance of the plug 41P. As in the manner of the semiconductor device lip shown in the longitudinal sectional view of Fig. 15, when the diameter of the contact hole 30 P is relatively small, the conductive material constituting the plug may not be completely filled in the contact hole 30 p. That is to say, the plug 4 2 P of Cheng Cheng will have a hole 4 2 K P in the center of the contact hole 30. In this case, the above-mentioned disconnection or higher resistance is more likely to occur due to a chemical solution or the like. The present invention is intended to solve the above-mentioned problems, and an object thereof is to provide a method for manufacturing a semiconductor device with high reliability that can improve the coverage of the conductive layer constituting the wiring layer and reduce problems such as disconnection. [Means for solving problems] (1) The first item of the patent application scope of the present invention is a method for manufacturing a semiconductor device, which is characterized by the following processes: (a) forming a dielectric layer with a contact hole on a substrate; (B) forming a first conductive layer bonded to the substrate in the contact hole; and (c) selectively removing the i-th conductive layer from the dielectric layer on the opposite side of the substrate by wet etching. A portion of a specified thickness from the surface. (2) The method for manufacturing a semiconductor device according to item 2 of the scope of patent application of the present invention is the method for manufacturing a semiconductor device according to item i of the scope of patent application. In the above-mentioned process (c) ', the above-mentioned wet money is carved The surface of the obtained dielectric layer is set to have the same height level as the top of the opposite side of the substrate of the conductive layer. (3) The method for manufacturing a semiconductor device according to item 3 of the scope of patent application of the present invention. The method is in the method for manufacturing a semiconductor device according to item 1 of the scope of patent application,
89117207.ptc 第9頁 46503 · _ _案號891Π207_年月日 修正_ 五 '發明說明（4) 在上述之製程（C )’對於上述濕式蝕刻後所獲得之上述介 質層之表面’上述第1導電層之與上述基板相反側之頂部 從該表面突出。 (4)本發明之申請專利範圍第4項之半導體裝置之製造方 法是在申請專利範圍第1至3項中任一項之半導體裝置之製 造方法中，更具備有製程（d)，在上述之濕式蝕刻後所獲 得之上述電介質層上，形成與上述第1導電層接合之第2導 電層。 [發明之實施形態] <實施形態1 > 圖1表示實施形態1之半導體裝置1〇之模式方式之縱向剖 面圖。另外’半導體裝置1〇具有1個或多個之MOS電晶體等 之元件（圖中未顯示），但是在圖1和後面所述之各個圖面 中’上述之M0S電晶體等之詳細之圖示被省略’只顯示以 下之說明所需要之構成元件。 如圖1所示，半導體裝置1 〇具備有例如由矽晶圓等構成 之基板1。在基板1之主面1S内之指定區域’形成有例如上 述之MOS電晶體之擴散層2。另外，在基板1之主面1S上’ 形成厚度Η 31之層間絕緣層（電介質層）3 1。作為層間絕緣 層31者，可以使用各種介質體材料，在此處所說明之情況 是由矽氧化物（S i 02 )構成層間絕緣層3 1。在層間絕緣層31 形成有孔或接觸孔3 〇，從該層間絕緣層3 1之與上述基板1 相反侧之表面3 1 S起到達上述之擴散層2。 另外，在接觸孔30内配置有例如由鎢（W)等之導電性材89117207.ptc Page 9 46503 · _ _Case No. 891Π207_ year, month, day, date, amendment _ 5 Description of the invention (4) In the above-mentioned process (C) 'for the surface of the above-mentioned dielectric layer obtained after the above-mentioned wet etching' above The top of the first conductive layer on the side opposite to the substrate protrudes from the surface. (4) The method for manufacturing a semiconductor device according to item 4 of the scope of patent application of the present invention is further provided with a manufacturing process (d) in the method for manufacturing a semiconductor device according to any one of claims 1 to 3 of the scope of patent application. A second conductive layer bonded to the first conductive layer is formed on the dielectric layer obtained after wet etching. [Embodiment of the invention] < Embodiment 1 > Fig. 1 shows a longitudinal sectional view of a mode of a semiconductor device 10 of Embodiment 1. In addition, the 'semiconductor device 10 has one or more MOS transistors and the like (not shown in the figure), but in each of the drawings described below and FIG. The description is omitted 'only the constituent elements necessary for the following description are shown. As shown in FIG. 1, the semiconductor device 10 includes a substrate 1 made of, for example, a silicon wafer. A diffusion region 2 of, for example, the MOS transistor described above is formed in a designated region 'within the main surface 1S of the substrate 1. In addition, on the main surface 1S of the substrate 1, an interlayer insulating layer (dielectric layer) 31 having a thickness of 31 is formed. As the interlayer insulating layer 31, various dielectric materials can be used. In the case described here, the interlayer insulating layer 31 is made of silicon oxide (Si02). A hole or a contact hole 30 is formed in the interlayer insulating layer 31, and reaches the above-mentioned diffusion layer 2 from the surface 3 1S of the interlayer insulating layer 31 opposite to the substrate 1. A conductive material such as tungsten (W) is disposed in the contact hole 30.
89117207.ptc 第10頁 46503489117207.ptc Page 10 465034
曰 修正 導電層)41成為接合在擴散層2，因此被 之特別是插頭41之與上述基板1相反側 ”或頂點41T具有與層間絕緣層31之表面3ls相同程度 位準。換言之，插頭41之厚度或高度㈣與層間絕 =31之厚度H31大致相等。另外，在圖i中所示之情況是 觸孔30内未具有空洞等，完成被上述之導電性材料充 填。 另外，在層間絕緣層31之上述表面31$上，形成有連接 到插頭41之配線層或配線（第2導電層）5。利用此種構造， 可以以插頭41電連接擴散層2和配線層5。 下面將參照圖2〜圖7之縱向剖面圖用來說明半導體置 1〇之製造方法。 首先_’如圖2所示’準備具有擴散層2之基板1 ^然後如 圖3所不，在基板2之主面】s上堆積矽氧化物藉以形成厚 度H31A之層間絕緣層（電介質層）31A。特別是使層間絕緣 層31A形成比圖丄之層間絕緣層31厚（厚度H3U >厚度 H31) °然後使用平版印刷技術形成接觸孔3〇使其從層間絕 緣層31 A之與上述基板1相反側之表面3 1 AS到達擴散層2。 其次’如圖4所示’在層間絕緣層31A之露出之表面31AS 上和在接觸孔30内堆積上述之導電性材料，藉以形成由該 導電性材料構成之插頭形成層41 A。此種導電性材料之堆 積例如可以以濺散法進行。 然後’對插頭形成層41 A進行深蝕刻。利用這種方式用 來除去插頭形成層41A内之層間絕緣層31A之表面31AS上之The modified conductive layer 41 is bonded to the diffusion layer 2. Therefore, especially the plug 41 on the opposite side of the substrate 1 or the vertex 41T has the same level as the surface 3ls of the interlayer insulating layer 31. In other words, the plug 41 The thickness or height 大致 is approximately equal to the thickness H31 of the interlayer insulation = 31. In addition, in the case shown in FIG. I, there is no cavity or the like in the contact hole 30, and the filling with the conductive material is completed. In addition, the interlayer insulation On the above surface 31 of 31, a wiring layer or wiring (second conductive layer) 5 connected to the plug 41 is formed. With this structure, the diffusion layer 2 and the wiring layer 5 can be electrically connected by the plug 41. The following will refer to the drawings 2 to 7 are used to explain the manufacturing method of the semiconductor device 10. First, _'as shown in FIG. 2 'to prepare a substrate 1 having a diffusion layer 2 ^ Then as shown in FIG. 3, on the main surface of the substrate 2 】 S is deposited on the silicon oxide to form an interlayer insulating layer (dielectric layer) 31A with a thickness of H31A. In particular, the interlayer insulating layer 31A is formed to be thicker than the interlayer insulating layer 31 in FIG. Printing technology The contact hole 30 allows it to reach the diffusion layer 2 from the surface 3 1 AS of the interlayer insulating layer 31 A on the opposite side of the above-mentioned substrate 1. Next, as shown in FIG. 4, on the exposed surface 31AS of the interlayer insulating layer 31A and on The above-mentioned conductive material is deposited in the contact hole 30 to form a plug-forming layer 41 A made of the conductive material. Such conductive material can be deposited, for example, by a sputtering method. Then, the plug-forming layer 41 A is performed. Deep etching. This method is used to remove the surface of the interlayer insulating layer 31A in the plug forming layer 41A from the surface 31AS.
465034 Λ -89117207__年月 曰 修正 五、發明說明（6) -〜一 !!份，藉以使上述之表面31AS露出。如圖5所示，在此種 深蝕刻後，於接觸孔30内殘留插頭形成層4 u之一部份， 該殘留之插頭形成層成為上述之插頭4〗。這時，插頭4〗之 頂部41T低於層間絕緣層3ia之表面31AS(厚度H41〈厚度 H31A)。 特別疋在本製造方法中，於插頭4丨之形成後，相對於插 頭4 1，對層間絕緣層31 a進行選擇性之濕式蝕刻❶亦即’ 利用包含氟酸（HF)之溶液，進行濕式蝕刻從層間絕緣層 3 1A之露出表面3 1 A S起之指定厚度之部份。利用此種濕式 蝕刻，在上述之層間絕緣層31A形成具有圖6所示之厚度 H3 1之層間絕緣層3 1 ^這時，將深蝕刻後所獲得之層間絕 緣層31之表面31S設定成為具有高度位準與插頭41之頂部 4 1 T大致相同之程度。 然後，如圖7所示，以覆蓋在層間絕緣層3丨之表面3丨s之 全面和插頭41之頂部41T之方式，例如堆積鋁（A1)等之配 線材料，用來形成配線層（第2導電層）5A。然後，對該配 線層5 A進行圖型製作藉以獲得圖1之半導體裝置丨〇。 依照實施形態1之製造方法時可以獲得下面所述之效 果0 首先，利用上述之濕式蝕刻可以用來調整插頭4〗之頂部 41T和層間絕緣層3 1之表面3 1 S之相對之高度位準。特別是 在實施形態1 ’因為使層間絕緣層3 1之表面31 s形成在與插 頭41之頂部4 1T相同程度之咼度位準，所以可以使配線層 5 A (參照圖7)之全面形成良好之平坦性。亦即，當與習知465034 Λ -89117207__ year month said amendment 5. Description of the invention (6)-~ one !! copies, so that the above-mentioned surface 31AS is exposed. As shown in FIG. 5, after such deep etching, a part of the plug-forming layer 4u remains in the contact hole 30, and the remaining plug-forming layer becomes the plug 4 described above. At this time, the top 41T of the plug 4 is lower than the surface 31AS (thickness H41 <thickness H31A) of the interlayer insulating layer 3ia. In particular, in the present manufacturing method, after the plug 4 is formed, the interlayer insulating layer 31 a is selectively wet-etched with respect to the plug 41 1, that is, using a solution containing hydrofluoric acid (HF). Wet etching is performed to a portion of a specified thickness from the exposed surface 3 1 AS of the interlayer insulating layer 3 1A. With such wet etching, an interlayer insulating layer 3 1 having a thickness H3 1 shown in FIG. 6 is formed on the interlayer insulating layer 31A. At this time, the surface 31S of the interlayer insulating layer 31 obtained after deep etching is set to have The height level is approximately the same as the top 4 1 T of the plug 41. Then, as shown in FIG. 7, in order to cover the entire surface of the interlayer insulation layer 3 丨 s 3 丨 s and the top 41T of the plug 41, for example, a wiring material such as aluminum (A1) is deposited to form a wiring layer (No. 2 conductive layer) 5A. Then, patterning is performed on the wiring layer 5 A to obtain the semiconductor device of FIG. 1. According to the manufacturing method of Embodiment 1, the following effects can be obtained. First, the above wet etching can be used to adjust the relative height of the top 41T of the plug 4 and the surface 3 1 S of the interlayer insulating layer 31. quasi. In particular, in Embodiment 1, since the surface 31 s of the interlayer insulating layer 31 is formed at the same level as the top portion 41T of the plug 41, the wiring layer 5A (see FIG. 7) can be fully formed. Good flatness. That is, when and learning
465034 -Ά 89117207_年月 a 放 χ__ 五、發明說明（7) 之半導體裝置1 〇 P (參照圖1 4 )比較時，可以大幅的改善配 線層5對插頭41之涵蓋範圍。 因此’依照本製造方法時，可以大幅的抑制習知之半導 體裝置10P之配線層5P所具有之開口 5Kp之發生或使其不會 發生。其結果是可以大幅的減小由於涵蓋範圍之不足所造 成之插頭和配線層之間之斷線和插頭與配線層之間之路徑 之高電阻化。亦即，可以使配線層5和插頭4丨確實的電連 接。 另外’因為配線層S未具有上述之開口 5 κ ρ，所以在配線 層5Α之形成後’實施各種滿 插頭41。因此’可以防止由 頭41之斷線和由於溶解而造 其次’在本製造方法中， 刻用來形成層間絕緣層3 1。 刻時所產生之附著在層間絕 等之異物，可以利用濕式蝕 在清淨化之層間絕緣層3丨之 以可以減少由於上述之異物 5 A和配線層5之斷線之發生 式處理時，藥液等不會接觸到 於藥液等引起之配線層5和插 成之插頭之高電阻化。 對層間絕緣層31 A進行濕式蝕 因此’當插頭形成層41A之蝕 緣層3 1 A或基板1之蝕刻殘留物 刻將其除去。因此，因為可以 表面31S上堆積配線層5A，所 等所引起之問題，例如配線層 因此’依照本製造方、、表主 層2確實電連接到配線層ς 1 i 製造和提供能夠從擴傲 然而，當使半導體裝置1〇 :體裝置。 五1 u之接觸孔3 0之ΐ徑忐鱼“ 情況時，與習知之半導骰酤罢η Α 且也成為較小之 〜卞导趨裝置11 Ρ (參照圖丨5 )同 人 插頭41亦會形成空洞。t B ) J樣的，在465034 -Ά 89117207_Year a χ__ V. Semiconductor device 1 O P (see Figure 14) of the invention description (7) When compared, the coverage of the plug layer 41 on the wiring layer 5 can be greatly improved. Therefore, according to this manufacturing method, the occurrence of the opening 5Kp in the wiring layer 5P of the conventional semiconductor device 10P can be significantly suppressed or prevented from occurring. As a result, the disconnection between the plug and the wiring layer and the path between the plug and the wiring layer due to insufficient coverage can be greatly reduced. That is, the wiring layer 5 and the plug 4 can be reliably electrically connected. In addition, since the wiring layer S does not have the opening 5 κ ρ described above, various full plugs 41 are implemented after the wiring layer 5A is formed. Therefore, it is possible to prevent the disconnection of the head 41 and the formation due to dissolution. In this manufacturing method, the interlayer insulating layer 31 is formed. The foreign matter adhering to the interlayer insulation produced at the time of the engraving can be wet-etched to clean the interlayer insulation layer 3 丨, so as to reduce the occurrence of disconnection due to the foreign matter 5 A and the wiring layer 5, The chemical solution and the like do not come into contact with the wiring layer 5 caused by the chemical solution or the like and increase the resistance of the inserted plug. The interlayer insulating layer 31 A is wet-etched. Therefore, when the plug-forming layer 41A is etched by the edge layer 3 1 A or the etching residue of the substrate 1, it is removed. Therefore, because the wiring layer 5A can be stacked on the surface 31S, for example, the problems caused by the wiring layer, for example, the wiring layer, therefore, according to the manufacturer, the main surface layer 2 is indeed electrically connected to the wiring layer. However, when the semiconductor device 10 is a bulk device. Five 1 u contact holes 3 0 diameter catfish "In the case, it is the same as the conventional semi-conductor dice Α Α and also becomes smaller ~ the guide device 11 Ρ (refer to Figure 丨 5) the same person plug 41 also Will form a cavity. T B) J-like, in
珉洞亦即’如同圖8之縱向剖面圖所J珉 洞 是 ’As in the longitudinal section of Figure 8 J
第13頁 -1號 89117207___年月日__ 五、發明說明（8) 之第2半導體裝置n之方式，形成具有空洞42K之插頭42 ’ ^發生導電性材料不能完全埋入到接觸孔3 〇内之情況。但 疋’經由使用上述之製造方法製造半導體裝置丨丨時，配線 層5Α和配線層5可以平坦的形成未具有開口 5Κρ。其結果是 在半導體裝置11亦可以獲得上述之各種效果。 亦即’在上述之製造方法中’所說明之情況是將層間絕 緣層31之表面3 1 S和插頭41之頂部4 1Τ設定在相同程度之高 度位準。與此相對的’如同圖9之縱向剖面圖所示之第3半 導體裝置1 2之方式’亦可以使與上述之層間絕緣層31相同 之層間絕緣層（電介質層）32之與基板1相反側之表面32S， 成為低於插頭41之頂部4 IT(層間絕緣層之厚度H32〈厚度 H4 1)。亦即，亦可以將層間絕緣層3丨a之濕式蝕刻量設定 成為使插頭4 1之頂部4 1 T從層間絕緣層3 2之表面3 2S突出。 在此種情況’插頭41和配線層5之接觸部份或接觸面積因 為大於上述之圖1之半導體裝置1〇者，所以可以使插頭41 和配線層5之連接更確實。 另外，在接觸孔3 0之直徑較大之情況時，亦可以使插頭 41之頂部41 T比層間絕緣層3 1之表面3 1S低某種程度。 亦即’在本製造方法中，只有在可以平坦的形成配線層 5A和配線層5時’才根據接觸孔3〇之尺寸和插頭充填到接 觸孔30内之程度等’用來規定層間絕緣層31 a之濕式蝕刻 量。 另外，在上述之說明中所說明之情況層間絕緣層3丨，32 使用妙氧化物，但是層間絕緣層3丨，3 2亦可以使用其他之Page 13-1 No. 89117207 __ Month of the month __ V. Description of the invention (8) The second semiconductor device n method forms a plug 42 'with a hole 42K ^ The conductive material cannot be completely embedded in the contact hole 3 〇The situation within. However, when the semiconductor device is manufactured by using the above-mentioned manufacturing method, the wiring layer 5A and the wiring layer 5 can be formed flat without the opening 5Kρ. As a result, the various effects described above can also be obtained in the semiconductor device 11. That is, in the case described in "the above-mentioned manufacturing method", the surface 3 1 S of the interlayer insulating layer 31 and the top 4 1T of the plug 41 are set to the same high level. On the other hand, in the “method of the third semiconductor device 12 as shown in the longitudinal cross-sectional view of FIG. 9”, the interlayer insulating layer (dielectric layer) 32 which is the same as the interlayer insulating layer 31 described above can be made on the opposite side of the substrate 1 The surface 32S is lower than the top 4 IT of the plug 41 (thickness H32 of the interlayer insulation layer <thickness H4 1). That is, the wet etching amount of the interlayer insulating layer 3a can be set so that the top 4 1T of the plug 41 can protrude from the surface 3 2S of the interlayer insulating layer 32. In this case, since the contact portion or contact area between the plug 41 and the wiring layer 5 is larger than the semiconductor device 10 of FIG. 1 described above, the connection between the plug 41 and the wiring layer 5 can be made more reliable. In addition, when the diameter of the contact hole 30 is large, the top 41 T of the plug 41 may be made lower than the surface 31 S of the interlayer insulating layer 31 to some extent. That is, "in the present manufacturing method, only when the wiring layer 5A and the wiring layer 5 can be formed flatly," the interlayer insulation layer is specified according to the size of the contact hole 30 and the degree to which the plug is filled into the contact hole 30. 31 a wet etching amount. In addition, in the case described in the above description, the interlayer insulating layers 3 丨, 32 use a fine oxide, but the interlayer insulating layers 3 丨, 3 2 can also use other
89117207.ptc 第14頁 4650 3 — 案號 891172Q7 年 月_日修正 五、發明說明（9) 介質體材料’例如矽氮化物（SiN)或矽氮化氧化物（SiON) 等。這時，在矽氮化物之情況，例如使用熱磷酸（H3p〇4)之 溶液用來實施上述之濕式蝕刻。另外，在矽氮化氧化物之 情況，例如使用包含有氟酸之溶液或包含在熱磷酸之溶液 (敍刻率低於矽氧化物或矽氮化物）用來實施上述之濕式蝕 刻0 另外’例如亦可以將插頭4 1，4 2構建成為2層，其構成包 含有：氮化鈦（T i N )層’被配置成接合在層間絕緣層3〗，32 ;和鎢層’被配置成接合在該氮化鈦層。同樣的，亦可以 成為多層化，包含擴散層2，插頭4 1，4 2，配線層5和層間 絕緣層31, 32之各層。 另外’在使用矽晶圓以外之基板作為基板1之情況時， 或使插頭形成連接在M0S電晶體之閘極電極之情況時，亦 可以使用上述之製造方法。 <實施形態1之變化例1 > 圖10表示本變化例1之半導體裝置13之模式方式之縱向 剖面圖。半導體裝置13具有比上述之圖1之半導體裝置 更多層之多層配線化構造。 亦即’以覆蓋在半導體裝置1 〇之層間絕緣層31之表面 31 S和配線層5之方式，更形成有層間絕緣層丨3 i。在層間 絕緣層1 3 1形成有接觸孔1 30從該層間絕緣層丨3】之與上述 基板1相反側之表面1 31 S到達配線層5。另外，在接觸孔 130内配置有接合配線層5之插頭（第1導電層）141 ,在層間 絕緣層131之表面13Ϊ之上形成有配線層（第2導電層）ι〇5成89117207.ptc Page 14 4650 3 — Case No. 891172Q7 Amendment Month_Day V. Description of the invention (9) Dielectric material ’such as silicon nitride (SiN) or silicon nitride oxide (SiON). At this time, in the case of silicon nitride, for example, a solution of hot phosphoric acid (H3po4) is used to perform the above-mentioned wet etching. In addition, in the case of silicon nitride oxide, for example, a solution containing hydrofluoric acid or a solution containing hot phosphoric acid (the etch rate is lower than that of silicon oxide or silicon nitride) is used to perform the above-mentioned wet etching. 'For example, the plugs 4 1, 4 2 can also be constructed into two layers, and the structure includes: a titanium nitride (T i N) layer' configured to be bonded to the interlayer insulating layer 3, 32; and a tungsten layer 'configured. The component is bonded to the titanium nitride layer. Similarly, it may be multi-layered and include each layer of the diffusion layer 2, the plugs 4 and 4, 2, the wiring layer 5, and the interlayer insulating layers 31 and 32. In addition, when a substrate other than a silicon wafer is used as the substrate 1, or when a plug is formed as a gate electrode connected to a MOS transistor, the above-mentioned manufacturing method can also be used. < Modification 1 of Embodiment 1 > Fig. 10 is a longitudinal cross-sectional view showing a mode of a semiconductor device 13 according to Modification 1. The semiconductor device 13 has a multilayer wiring structure having more layers than the semiconductor device of FIG. 1 described above. That is, the interlayer insulating layer 3 i is further formed so as to cover the surface 31 S of the interlayer insulating layer 31 of the semiconductor device 10 and the wiring layer 5. A contact hole 1 30 is formed in the interlayer insulating layer 1 3 1 and reaches the wiring layer 5 from the surface 1 31 S on the opposite side of the interlayer insulating layer 1 to the substrate 1 described above. In addition, a plug (first conductive layer) 141 that joins the wiring layer 5 is disposed in the contact hole 130, and a wiring layer (second conductive layer) is formed on the surface 13 of the interlayer insulating layer 131.
89117207,ptc 第15頁 4 6 5 C 3 案號891Π207__年月日 修正 五、發明說明（10) 為連接到插頭1 4 1之與基板1相反侧之頂部1 41 T。 上述之實施形態1之製造方法亦可適於在層間絕緣層 1 3 1 ’插頭1 4 1和配線層1 〇 5之形成，可以獲得上之各種效 果。這時’對於層間絕緣層1 31等之形成，半導體裝置i 〇 相當於「基板」。另外，對於更多層之多層化配線之半導 體裝置，亦可以使用實施形態1之製造方法。 [發明之效果] (1) 依照本發明之申請專利範圍第1項時，利用製程（c) 之濕式蝕刻可以調整電介質層之表面，和第j導電層之與 基板相反側之頂部之相對之高度位準。因此，在製程 之實施前，即使第1導電層上之上述頂部比電介質層之表 面凹陷之情況時，換言之，即使電介質層之表面高於第1 導電層之上述頂部之情況時，亦可以以良好之涵蓋範圍在 介質體上形成接合第丨導層之層（例如配線層）。因此，可 以抑制上述之配線層和第丨導電層之斷線，和抑制上 配線層與第1導電層之間之高電阻。亦即，可以使 配線層和第1導電層確實的電連接。 製程(C)因為使用漏式餘刻，附 此，可以抑制由於上述之異物等;其除去。因 如可以抑制上述之配線層之斷之問題之發生，例 (2) 依照本發明之中請專利範圍^項時，將 進打濕式飯刻後所獲得之電介質. 、耘（C ) 叼度位準。因此，可以綠89117207, ptc Page 15 4 6 5 C 3 Case No. 891Π207__Year Month Day Amendment V. Description of the invention (10) is the top 1 41 T connected to the plug 1 4 1 on the side opposite to the base plate 1. The manufacturing method of the first embodiment described above can also be applied to the formation of the interlayer insulating layer 1 3 1 'plug 1 41 and the wiring layer 105, and various effects can be obtained. At this time, the semiconductor device i 0 corresponds to the "substrate" for the formation of the interlayer insulating layer 1 31 and the like. In addition, for a semiconductor device with multilayer wiring of more layers, the manufacturing method of the first embodiment can also be used. [Effects of the invention] (1) According to item 1 of the scope of patent application of the present invention, the wet etching of the process (c) can be used to adjust the surface of the dielectric layer and the top of the j-th conductive layer on the opposite side of the substrate. Height level. Therefore, before the implementation of the process, even if the above-mentioned top on the first conductive layer is recessed than the surface of the dielectric layer, in other words, even if the surface of the dielectric layer is higher than the above-mentioned top of the first conductive layer, the Good coverage forms a layer (such as a wiring layer) that joins the first conductive layer on the dielectric body. Therefore, it is possible to suppress the disconnection between the above-mentioned wiring layer and the first conductive layer, and to suppress high resistance between the upper wiring layer and the first conductive layer. That is, the wiring layer and the first conductive layer can be reliably electrically connected. In the process (C), since a leak type is used, the foreign matter or the like due to the above can be suppressed; its removal can be suppressed. Because the problem of the disconnection of the wiring layer described above can be suppressed, for example (2) According to the scope of the patent application of the present invention, the dielectric obtained after the wet-type meal is engraved. 、 (C) 叼Degree level. So it can be green
89117207.pt 第16頁 修正 曰 案號 89117207 五、發明說明（11) 實的獲得上述配線廣之良好之涵蓋範圍。所以可以大幅的 減少配線層和第1導電層之間之斷線和變成高電阻，可以 更確實的進行上述之配線層與第丨導電層之電連接。 (3) 依照本發明之申請專利範圍第3項時，在製程（c)使 第1導電層之頂部從居式姓刻後所獲得之電介質層之表面 突出。因此，上述之配線層和第1導電層可以更確實的電 連接。 (4) 依照本發明之申請專利範圍第4項時，可以形成與第 1導電層球實電連接之第2導電層。利用這種方式，經由接 觸孔可以使基板和第1導電層及第2導電層確實的電連接， 可以製造高可靠度之半導體裝置。 [元件編號之說明] 基板 主面 擴散層 配線層（第2導電層） 半導體裝置 接觸孔 層間絕緣層（電介質層） 表面 插頭（第1導電層） 插頭形成層 頂部 189117207.pt Page 16 Amendment Case No. 89117207 V. Description of the Invention (11) The above mentioned wiring has a wide and good coverage. Therefore, the disconnection between the wiring layer and the first conductive layer can be greatly reduced and the resistance becomes high, and the electrical connection between the wiring layer and the first conductive layer can be performed more reliably. (3) According to item 3 of the scope of patent application of the present invention, in the process (c), the top of the first conductive layer is protruded from the surface of the dielectric layer obtained after the nickname is engraved. Therefore, the above-mentioned wiring layer and the first conductive layer can be more reliably electrically connected. (4) According to item 4 of the patent application scope of the present invention, a second conductive layer that is electrically connected to the first conductive layer ball can be formed. In this way, the substrate can be reliably electrically connected to the first conductive layer and the second conductive layer through the contact holes, and a highly reliable semiconductor device can be manufactured. [Description of element number] Substrate Main surface Diffusion layer Wiring layer (second conductive layer) Semiconductor device Contact hole Interlayer insulating layer (dielectric layer) Surface Plug (first conductive layer) Plug forming layer Top 1
1S 2 5,5A, 1 0S 10 〜13 301S 2 5,5A, 1 0S 10 ～ 13 30
31,31A,32,131 31S,31 AS,32S, 131S 41,42,141 41A 41T，42T, 141T H31, H31A, H32, H41, H42 厚度31,31A, 32,131 31S, 31 AS, 32S, 131S 41,42,141 41A 41T, 42T, 141T H31, H31A, H32, H41, H42 thickness
89117207.ptc 第17頁 4 ϋ' ^_案號89117207_年月曰 修正_ 圖式簡單說明 圖1是實施形態1之半導體裝置之縱向剖面圖。 圖2是用以說明實施形態1之半導體裝置之製造方法之縱 向刹面圖。 圖3是用以說明實施形態1之半導體裝置之製造方法之縱 向剖面圖。 圖4是用以說明實施形態1之半導體裝置之製造方法之縱 向刹面圖。 圖5是用以說明實施形態1之半導體裝置之製造方法之縱 向剖面圖。 圖6是用以說明實施形態1之半導體裝置之製造方法之縱 向剖面圖。 圖7是用以說明實施形態1之半導體裝置之製造方法之縱 向剖面圖。 圖8是實施形態1之第2半導體裝置之縱向剖面圓。 圖9是實施形態1之第3半導體裝置之縱向剖面圖。 圖1 0是實施形態1之變化例1之半導體裝置之縱向剖面 圖。 圖11是用以說明習知技術之半導體裝置之製造方法之縱 向剖面圖。 圖1 2是用以說明習知技術之半導體裝置之製造方法之縱 向剖面圖。 — 圖1 3是用以說明習知技術之半導體裝置之製造方法之縱. 向剖面圖。 圖1 4是習知技術之半導體裝置之縱向剖面圖。89117207.ptc Page 17 4 ϋ '^ _ Case No. 89117207_ Modified _ Brief Description of Drawings FIG. 1 is a longitudinal sectional view of a semiconductor device according to the first embodiment. Fig. 2 is a longitudinal brake surface view for explaining a method for manufacturing a semiconductor device according to the first embodiment. Fig. 3 is a longitudinal sectional view for explaining a method for manufacturing a semiconductor device according to the first embodiment. Fig. 4 is a longitudinal brake surface view for explaining a method for manufacturing a semiconductor device according to the first embodiment. Fig. 5 is a longitudinal sectional view for explaining a method for manufacturing a semiconductor device according to the first embodiment. Fig. 6 is a longitudinal sectional view for explaining a method for manufacturing a semiconductor device according to the first embodiment. Fig. 7 is a longitudinal sectional view for explaining a method for manufacturing a semiconductor device according to the first embodiment. FIG. 8 is a vertical sectional circle of the second semiconductor device of the first embodiment. FIG. 9 is a longitudinal sectional view of a third semiconductor device according to the first embodiment. Fig. 10 is a longitudinal sectional view of a semiconductor device according to a first modification of the first embodiment. Fig. 11 is a longitudinal sectional view for explaining a method of manufacturing a semiconductor device according to a conventional technique. Fig. 12 is a longitudinal cross-sectional view for explaining a method of manufacturing a semiconductor device according to a conventional technique. — FIG. 13 is a longitudinal cross-sectional view for explaining a manufacturing method of a conventional semiconductor device. FIG. 14 is a longitudinal sectional view of a conventional semiconductor device.
89117207.ptc 第18頁 4 6 5 Ο > _案號89117207_年月曰 修正_ 圖式簡單說明 圖1 5是習知技術之另一半導體裝置之縱向剖面圖。89117207.ptc Page 18 4 6 5 Ο > _Case No. 89117207_ Year Modified _ Brief Description of Drawings Figure 15 is a longitudinal sectional view of another semiconductor device of conventional technology.
89117207.ptc 第19頁89117207.ptc Page 19
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000000796A JP2001196451A (en) | 2000-01-06 | 2000-01-06 | Method of manufacturing semiconductor device and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW465034B true TW465034B (en) | 2001-11-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW89117207A TW465034B (en) | 2000-01-06 | 2000-08-25 | Method of manufacturing semiconductor device |
Country Status (4)
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|---|---|
| JP (1) | JP2001196451A (en) |
| KR (1) | KR20010070062A (en) |
| DE (1) | DE10044470A1 (en) |
| TW (1) | TW465034B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100650811B1 (en) * | 2005-05-30 | 2006-11-27 | 주식회사 하이닉스반도체 | Method of forming a contact plug in semiconductordevice |
-
2000
- 2000-01-06 JP JP2000000796A patent/JP2001196451A/en active Pending
- 2000-08-25 TW TW89117207A patent/TW465034B/en not_active IP Right Cessation
- 2000-09-08 DE DE2000144470 patent/DE10044470A1/en not_active Ceased
- 2000-09-08 KR KR1020000053394A patent/KR20010070062A/en not_active Application Discontinuation
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| Publication number | Publication date |
|---|---|
| JP2001196451A (en) | 2001-07-19 |
| DE10044470A1 (en) | 2001-07-19 |
| KR20010070062A (en) | 2001-07-25 |
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