JPH04162421A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the defective leakage and defective bits due to the damage of a diffusion layer by forming a conductive film extending over the upper sections of an element isolation region and a diffusion layer region. CONSTITUTION:The surface of a semiconductor substrate (a silicon substrate 1) is oxidized selectively and an element forming region is partitioned by an element isolation region 3, and boron is implanted in energy of 30keV and dosage of 5X10<15>cm<-2> in order to form source-drain regions and a P<+> diffusion layer 2 is formed. A silicon oxide film is grown in approximately 400nm through a CVD method as an inter-layer insulating film 6, a polysilicon film is grown in approximately 250nm, and phosphorus ions are implanted in energy of 70keV and dosage of 1X10<16>cm<-2> and a conductive polysilicon film 5 (a conductive film) is shaped through patterning so as to leave the polysilicon film extending over the upper section of one part of the P<+> diffusion layer 2 from the upper section of the edge section of the element isolation region 3. A BPSG film is formed in approximately 700nm as an inter-layer insulating film 6', and a contact hole is shaped through wet etching and dry etching methods. Wet etching is conducted by buffer hydrofluoric acid (BHF) and dry etching by the mixed gas of CHF3, CF4 and Ar.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a connection structure between a diffusion layer portion and a wiring layer.

[Conventional technology]

The conventional method for forming this type of connection structure is as shown in Figure 3.
The surface of the semiconductor substrate 2 (silicon substrate 1) is selectively oxidized to form a field oxide film as an element isolation region to define an element formation region, and the silicon substrate 1 in the element formation region is exposed to boron energy of 30 keV and dose of 5. X 1
015cm-2, P in the source/drain region
+ Form the diffusion layer 2.

Next, an oxide film 4 of about 30 nm is formed by gate oxidation.

Then, as interlayer insulating films 6 and 6', a silicon oxide film and a BPSG film were formed by CVD to a thickness of 400 nm, respectively.
7 (] Onm is deposited, and then the contact hole 7 is etched by wet etching and dry etching methods, and then Af is deposited.
A P+ diffusion layer 2 is formed by sputter-depositing a fl film with a thickness of 1.1 μm and patterning it to form an A, f2 wiring layer 8.
and the Affl wiring layer 8 were directly connected.

[Problem to be solved by the invention]

In the conventional semiconductor device manufacturing method described above, when forming a contact hole, if the contact hole becomes large due to overexposure of the contact, overetching during contact etching, wet overetching during wiring pretreatment, etc., as shown in FIG. The edges and diffusion layers of the portions that should be element isolation regions are etched. After this, for example, P+
For contact with a diffusion layer, use contact boron at a dose of I x 10”cm-2 and an energy of 100ke.
When ions are implanted at V, the result is as shown in FIG. Since the element isolation region width is shortened by etching, the distance 13 between the P+ diffusion layer 2' made of boron for source/drain formation and the P+ layer 11 made of contact boron is shortened, and the threshold voltage of the field transistor is increased. There was a problem that the quality decreased and the product became defective. In addition, if the contact hole becomes large due to process variations, the hole in the element isolation region of the contact hole will be etched during Ar dry etching, resulting in a defect 10, which will damage the silicon substrate and cause leakage current defects and bits. There was a problem that it caused defects.

[Means to solve the problem]

A method of manufacturing a semiconductor device according to the present invention includes a step of selectively forming an element isolation region in a semiconductor substrate to partition an element formation region, and a diffusion layer of a predetermined conductivity type in the element formation region in contact with the element isolation region. a step of depositing an interlayer insulating film having a conductive film of a predetermined shape provided above a portion of the element isolation region and the diffusion layer; and a step of selectively removing the interlayer insulating film to The method includes a step of exposing a part of the surface of a conductive film and opening a contact hole, and a step of forming a wiring layer connected to the diffusion layer in the contact hole portion.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

The surface of the semiconductor substrate (silicon substrate 1) is selectively oxidized to partition element forming regions with element isolation regions 3, and boron is heated at an energy of 30 keV to form source/drain regions.
, P was implanted at a dose of 5 x 1015 cm-2.
+ Form the diffusion layer 2. Next, CVD was used as the interlayer insulating film 6.
A silicon oxide film was grown to a thickness of about 400 nm using the method, and then a polysilicon film was grown to a thickness of about 250 nm, with an energy of 70 k.
Phosphorus ions are implanted at a dose of 1 x 1018 cm-2 at a dose of 1 x 1018 cm-2.
``A conductive polysilicon film 5 (conductive film) is formed by patterning so that a polysilicon film remains partially above the diffusion layer 2, and a BPSG film of about 700 nm is formed as an interlayer insulating film 6, and then a contact hole is formed. Formed by wet etching and dry etching methods.

Wet etching uses buffered butic acid (BHF), and dry etching uses CHF3. CF4 and Ar
By mixed gas. In this case, since the conductive polysilicon film is not etched, the etching hole is prevented from progressing in that portion, and no defects are generated at the edge portion of the blocking isolation region.

Even if the end of the AI2 wiring layer 8 is located in the contact hole when patterning the Ar film by dry etching, it is blocked by the conductive polysilicon film 5, so no defects occur in the element isolation region 3. . Therefore, the distance between the P+ diffusion layers 2 and 2' in the source/drain region is not shortened during contact formation, and a drop in the threshold voltage of the field transistor is prevented, resulting in leakage current defects and bit failure (MOS) transistors. (poor characteristics)
can be reduced.

FIG. 2 is a sectional view for explaining a second embodiment of the present invention.

In this embodiment, the conductive polysilicon film 5 is formed before depositing the interlayer insulating films 6, 6', but it is also possible to deposit the conductive polysilicon film 5 at the same time as the polysilicon film for the gate electrode. Therefore, the photoresist process and the conductive polysilicon film growth process can be performed simultaneously with the formation of the gate electrode, which has the advantage that the process is simpler than in the first embodiment.

In the above embodiments, it is also possible to use a high melting point metal film instead of the conductive polysilicon film.

〔Effect of the invention〕

As explained above, the present invention forms a conductive film that spans over the element isolation region and the diffusion layer region, thereby making contact during the contact dry etching process for forming contact holes in the interlayer insulating film and the dry etching process for patterning the wiring layer. The conductive film in the hole acts as a stopper and prevents the element isolation region and the diffusion layer from being etched even when over-etched, which has the effect of reducing leakage defects and bit defects due to damage to the diffusion layer.

[Brief explanation of drawings]

FIGS. 1, 2, and 3 are cross-sectional views showing semiconductor devices according to a first embodiment, a second embodiment, and a conventional example of the present invention, respectively. ■... Silicon substrate, 2, 2'... P+ diffusion layer, 3... Element isolation region, 4... Oxide film, 5...
...Conductive polysilicon film, 6,6'...Interlayer insulating film, 7...Contact hole, 8...A
n wiring layer, 9... cover film, 10... defective part, 11... P+ layer made of contact boron, 12... P+ diffusion layers 2 and 2' interval, 13・
... Distance between P+ diffusion layer 2' and P'' layer 11. Agent: Susumu Uchihara, patent attorney

Claims (1)

[Claims] selectively forming an element isolation region in a semiconductor substrate to partition an element formation region; forming a diffusion layer of a predetermined conductivity type in the element formation region in contact with the element isolation region; and the element isolation region. a step of depositing an interlayer insulating film having a conductive film of a predetermined shape provided above a part of the diffusion layer; and selectively removing the interlayer insulating film to expose a part of the surface of the conductive film. a step of drilling a contact hole by
A method for manufacturing a semiconductor device, comprising the step of forming a wiring layer connected to the diffusion layer in the contact hole.