JP2004253572A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a resistor element composed of a polysilicon layer that is not exposed readily due to the effect of dishing and can maintain its shape, and to provide a method of manufacturing the device. <P>SOLUTION: On a semiconductor substrate, the resistor element 11 composed of the polysilicon layer is formed on, for example, an element separating insulating film 10. In both ends of the resistor element 11, silicide electrodes 12 are formed. The resistor element 11 is surrounded by the dummy pattern 13 of the polysilicon layer left in accordance with at least a flattened stopper film. The flattened stopper layer is composed of a silicon nitride film, but is removed in this case. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device including a step of flattening a flattening processing layer on a semiconductor wafer having a large-area resistive element formation region in a semiconductor integrated circuit by chemical mechanical polishing, and a method of manufacturing the same.
[0002]
[Prior art]
With miniaturization and high integration of semiconductor elements, gate electrodes and wirings are becoming finer and pitches are being reduced. The number of wiring layers increases, and chemical mechanical polishing, a so-called CMP (Chemical Mechanical Polishing) technique, is indispensable for a planarization process between formation layers. In order to form a resistive element having a large area, the influence of CMP must be considered. That is, there is a risk that the original shape of the resistance element may be damaged by the influence of dishing.
[0003]
FIGS. 5A and 5B are cross-sectional views for explaining a problem that an interlayer insulating film in a conventional resistance element portion is flattened. An interlayer insulating film is formed on the resistive element pattern made of polysilicon (FIG. 5A). Since this resistive element pattern has a large area, when CMP is performed up to the surrounding flattening end level (not shown), the vicinity of the center of the resistive element pattern is exposed due to dishing (FIG. 5B). In this case, there is a danger that the polysilicon exposed in a later etching step or the like is etched, the original thickness cannot be maintained, and the element does not function as a resistance element.
[0004]
[Problems to be solved by the invention]
The resistive element pattern as described above is sometimes used in a booster circuit of a memory or the like, and there is a problem that the pattern shape is damaged by the influence of dishing at the time of CMP.
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a semiconductor device having a resistive element made of a polysilicon layer which is not easily exposed due to dishing and can maintain its shape, and a method of manufacturing the same. Things.
[0005]
[Means for Solving the Problems]
The semiconductor device according to the present invention includes:
Having a resistance element made of a polysilicon layer in the semiconductor integrated circuit,
The resistive element is surrounded by a dummy pattern of the polysilicon layer left at least according to the planarization stopper film.
[0006]
According to the semiconductor device of the present invention, the dummy pattern is provided around the large-area resistance element. On this dummy pattern, a pattern of a planarization stopper film serving as a dishing barrier at the time of planarization by chemical mechanical polishing is formed.
The resistive element has a silicide electrode at an end thereof. By selectively forming a silicide electrode, both terminals of the resistor are formed.
[0007]
The method for manufacturing a semiconductor device according to the present invention includes:
Regarding formation of a resistance element formed of a polysilicon layer in a semiconductor integrated circuit,
Uniformly forming the polysilicon layer on a region including at least a portion where a resistance element is to be formed;
Patterning a planarization stopper film including a dummy pattern region around the portion where the resistance element is to be formed,
Patterning the polysilicon layer into a predetermined resistance element shape and forming a dummy pattern at a predetermined distance around the resistance element shape in accordance with the pattern of the planarization stopper film;
Forming an interlayer insulating film on the resistive element shape and the dummy pattern;
Flattening the insulating film to the level of the flattening stopper film by chemical mechanical polishing,
It is characterized by having.
[0008]
According to the method of manufacturing a semiconductor device according to the present invention, the upper portion of the dummy pattern is a flattening stopper film during chemical mechanical polishing, and serves as a barrier to prevent the influence of dishing on the surface of the resistive element shape.
The method further comprises a step of selectively silicifying a predetermined portion with respect to the resistance element shape.
The method may further include a step of removing the flattening stopper film after the flattening step.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a plan view showing a configuration of a main part of a semiconductor device according to an embodiment of the present invention, and showing a resistance element. In a semiconductor substrate, for example, a resistance element 11 made of a polysilicon layer is formed on an element isolation insulating film 10. Silicide electrodes 12 are formed at both ends of the resistance element 11. This resistance element 11 is surrounded by the dummy pattern 13 of the polysilicon layer left at least according to the planarization stopper film. The flattening stopper film is a silicon nitride film, but has been removed here.
[0010]
According to the above embodiment, the dummy pattern 13 is provided around the large-area resistance element 11. A pattern of a flattening stopper film is formed on the dummy pattern 13 and serves as a dishing barrier at the time of flattening by chemical mechanical polishing (CMP). Thereby, even after the CMP, the shape of the resistance element 11 is not exposed from the interlayer insulating film, and there is no problem in the subsequent etching process.
[0011]
2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention, in which the formation of the resistive element in the configuration of FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals. As shown in FIG. 2A, in a semiconductor substrate, for example, a polysilicon layer 11a and a silicon nitride film 13b are formed on a region including a portion where an element isolation insulating film 10 is to be formed with a resistance element. The silicon nitride film 13b is a planarization stopper film, and is patterned to include a dummy pattern region around a portion where a resistance element is to be formed.
[0012]
Next, as shown in FIG. 2B, the resist film 21 is patterned by a photoresist process. Then, the polysilicon layer 11a is etched according to the pattern of the resist film 21 and the pattern of the silicon nitride film 13b. Thereby, a predetermined shape of the resistance element 11 is formed. A dummy pattern 13 formed by laminating a polysilicon layer 13a and a silicon nitride film 13b is provided at a predetermined distance around the shape of the resistance element 11.
[0013]
Next, as shown in FIG. 2C, the resist film 21 is removed, and an oxide film 22 is formed by a CVD (Chemical Vapor Deposition) method. A resist layer (not shown) is patterned above the resistive element 11 except for the terminals. Thereafter, the side wall and the cap of the resistance element 11 are formed by the oxide film 22 by anisotropic etching. The oxide film 22 remains on at least the side wall of the polysilicon layer 13a of the dummy pattern 13. Next, the silicide electrode 12 is formed on the exposed portion of the polysilicon layer 13a through, for example, sputtering deposition of a cobalt film.
[0014]
Next, as shown in FIG. 2D, an interlayer insulating film 24 covering the resistance element 11 and the dummy pattern 13 is formed by a CVD method. After that, planarization is performed by using a CMP technique. At this time, polishing is performed to the level of the silicon nitride film 13b in the dummy pattern 13 to complete the planarization. At this time, dishing occurs in the large-area resistance element 11, but the silicon nitride film 13b in the dummy pattern 13 serves as a dishing barrier. Thereby, even after the CMP, the shape of the resistance element 11 is not exposed from the interlayer insulating film, and there is no problem in the subsequent etching process.
Thereafter, the silicon nitride film 13b in the dummy pattern 13 may be removed. As a result, as shown in FIG. 1, a resistor element 11 having a dummy pattern around it is formed.
[0015]
According to the above embodiment, the dummy pattern 13 is provided around the large-area resistance element 11. At the time of chemical mechanical polishing, the upper portion of the dummy pattern is a planarization stopper film of the silicon nitride film 13b, and serves as a barrier to prevent the influence of dishing on the surface of the resistive element shape.
[0016]
Note that the pattern shape of the resistance element 11 can be variously considered.
3 and 4 are plan views showing other pattern shapes of the resistance element 11, respectively. The same parts as those in FIG. 1 are denoted by the same reference numerals. As shown in FIG. 3, a shape for increasing the length is conceivable. Further, in FIG. 5, predetermined dummy patterns 13 are also scattered in the surrounding dummy patterns 13. This is advantageous as a mode for alleviating the influence of dishing when forming a resistive element with a larger area.
[0017]
As described above, according to the present invention, a dummy pattern having a predetermined height is formed around a large-area resistive element having a fear of dishing. The lower layer of the dummy pattern can be formed together when forming the resistive element, and the upper layer relates to the formation of other elements. As a result, it is possible to provide a semiconductor device having a resistive element made of a polysilicon layer that can maintain its shape without being easily exposed due to dishing, and a method of manufacturing the same.
[Brief description of the drawings]
FIG. 1 is a plan view of a resistance element in a main part configuration of a semiconductor device according to an embodiment.
FIG. 2 is a sectional view showing the formation of the resistance element in the configuration of FIG. 1 in the order of steps.
FIG. 3 is a first plan view showing another pattern shape of the resistance element.
FIG. 4 is a second plan view showing another pattern shape of the resistance element.
FIG. 5 is a cross-sectional view showing a conventional problem of flattening an interlayer insulating film in a resistance element portion.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... element isolation insulating film, 11 ... resistance element, 11a, 13a ... polysilicon layer, 12 ... silicide electrode, 13 ... dummy pattern, 13b ... silicon nitride film, 21 ... resist film, 22 ... oxide film, 24 ... interlayer insulation film.

Claims (5)

A semiconductor device having a resistor element made of a polysilicon layer in a semiconductor integrated circuit, wherein the resistor element is surrounded by a dummy pattern of the polysilicon layer left at least according to a planarization stopper film. 2. The semiconductor device according to claim 1, wherein said resistance element has a silicide electrode at an end thereof. Regarding formation of a resistance element formed of a polysilicon layer in a semiconductor integrated circuit,
Uniformly forming the polysilicon layer on a region including at least a portion where a resistance element is to be formed;
Patterning a planarization stopper film including a dummy pattern region around the portion where the resistance element is to be formed,
Patterning the polysilicon layer into a predetermined resistance element shape and forming a dummy pattern at a predetermined distance around the resistance element shape in accordance with the pattern of the planarization stopper film;
Forming an interlayer insulating film on the resistive element shape and the dummy pattern;
Flattening the insulating film to the level of the flattening stopper film by chemical mechanical polishing,
A method for manufacturing a semiconductor device, comprising: 4. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of selectively silicifying a predetermined portion with respect to the resistance element shape. 5. The method according to claim 3, further comprising a step of removing the planarization stopper film after the planarizing step.

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