JP2000058640A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a semiconductor device with a common contact and an ordinary contact by a small number of processes by simultaneously forming the common contact and the ordinary contact to penetrate through a first insulating layer. SOLUTION: Gate oxide films 2 and gate electrodes 3 are formed successively onto a semiconductor substrate 1, and diffusion layers 5 are formed. A first oxide film 6 and SiON 7 are formed onto the surface of the semiconductor substrate 1. SiON 7 and the first oxide film 6 are etched in succession, contacts are bored, and tungsten is buried, and tungsten plugs are shaped. The common contact 15 extending over the gate electrode 3 and the diffusion layer 5 and the ordinary contact 16 on the diffusion layer 5 are formed simultaneously at that time. Accordingly, since the ordinary contact 16 and the common contact 15 can be formed by the same process, the number of manufacturing processes can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a common contact not connected to an upper wiring and a normal contact connected to an upper wiring.

[0002]

2. Description of the Related Art A conventional semiconductor device will be described with reference to the drawings.

FIG. 9 is a sectional view of a conventional semiconductor device, and FIG.
Is a plan view thereof.

FIGS. 11 to 14 are sectional views showing respective steps of a conventional method for manufacturing a semiconductor device.

FIG. 11 (a) shows a gate oxide film 2 having a thickness of, for example, 60.degree.
The gate electrodes 3 made of polysilicon are sequentially formed.

FIG. 11B shows a gate electrode 3 according to a known method.
Is patterned, and using this as a mask, for example, 30 ke
V, 2 × 10 ¹³ atoms / cm ^{2 were} implanted to form a low concentration diffusion layer 5.

FIG. 11C shows that a side wall 4 is formed on the side wall of the gate electrode 3 by a known method. Further, using this as a mask, for example, arsenic is applied at 70 keV and 4 × 10 ¹⁵ atoms.
/ Cm ² to form a high concentration diffusion layer 5.

FIG. 12A shows a first oxide film 6 made of, for example, a BPSG film having a thickness of 5000 ° on the surface of a semiconductor substrate 1.
Is formed.

FIG. 12B shows a gate electrode 3 according to a known method.
After forming a hole to be a common contact so as to extend over the diffusion layer 5, tungsten is buried in the hole by a known method to form a common contact 12 made of a first tungsten plug. The common contact connects the gate electrode 3 and the diffusion layer 5, and is not connected to the upper wiring.

FIG. 13A shows a second oxide film 9 made of, for example, a 2000-nm-thick plasma oxide film.

FIG. 13B shows that the second oxide film 9 and the first oxide film 6 are sequentially etched by a known method to form a hole to be a normal contact on the diffusion layer 5, and Tungsten is buried in this hole by a known method to form a normal contact 13 made of a second tungsten plug. The normal contact is a contact that connects the upper wiring and the diffusion layer.

FIG. 14A shows a structure in which, for example, aluminum having a thickness of 4000 ° is sputtered and patterned to form a first aluminum wiring 18 as an upper wiring.

FIG. 14B shows a third oxide film 11 made of a plasma oxide film having a thickness of 4000 °, for example. This figure shows the completed semiconductor device and is the same as FIG.

Next, a plan view of a conventional semiconductor device will be described with reference to FIG.

FIG. 10 is a plan view of a memory cell of one full CMOS SRAM. The second aluminum wiring 19 in FIG. 10 is formed after the step shown in FIG. 14B is completed.

The equivalent circuit diagram of this full CMOS SRAM is similar to that of the semiconductor device of the present invention, and is shown in FIG.

[0017] As a prior art related to the present invention,
There are a "method of manufacturing a semiconductor device" described in JP-A-5-67736 and a "method of manufacturing a semiconductor device and a master wafer used in the method" described in JP-A-7-161945.

[0018]

In the prior art,
As described above, the common contact 12 and the normal contact 1
3 must be formed separately, ie, FIG.
In step 2 (b), a common contact is opened and the first tungsten plug 12 is buried. In the step of FIG. 13 (b), a normal contact is opened and the second tungsten plug 1 is opened.
Since 3 must be embedded, the number of manufacturing steps increases.

An object of the present invention is to provide a method for manufacturing a semiconductor device having a common contact and a normal contact in a small number of steps.

[0020]

A method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device having a common contact not connected to an upper wiring and a normal contact connected to the upper wiring. Forming a first insulating layer on the semiconductor substrate on which the diffusion layer and the gate electrode are formed; and forming the first insulating layer on the semiconductor substrate on which the diffusion layer and the gate electrode are formed. A contact forming step of forming a contact and the normal contact at the same time.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described method of manufacturing a semiconductor device, a step of forming a second insulating layer after the step of forming a contact; The method includes a step of removing a part including a part on the contact, and a step of forming the upper wiring in the removed part.

Further, the method of manufacturing a semiconductor device according to the present invention, in the method of manufacturing a semiconductor device described above, further comprises a step of forming an etching stopper on the surface of the first insulating layer before the step of forming a contact. It is characterized by.

Further, the method of manufacturing a semiconductor device according to the present invention, in the method of manufacturing a semiconductor device described above, further comprises a step of forming a third insulating layer on the upper wiring and the second insulating layer. It is characterized by.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the method of manufacturing a semiconductor device described above, after the contact forming step, a wiring material is formed and patterned to form the upper wiring. It is characterized by having.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the method of manufacturing a semiconductor device described above, the common contact is formed so as to connect the gate electrode and the diffusion layer.

Further, a method of manufacturing a semiconductor device according to the present invention is characterized in that, in the method of manufacturing a semiconductor device described above, the normal contact is formed on the diffusion layer.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device manufactured by the manufacturing method according to the present invention, and FIG. 2 is a plan view thereof.

First, the manufacturing method of the present invention will be described.

FIGS. 3 to 6 are sectional views showing the steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 3A shows a gate oxide film 2 having a thickness of, for example, 50.degree. And a gate electrode 3 made of polysilicon having a thickness of, for example, 1500.degree.

FIG. 3 (b) shows that the gate electrode 3 is patterned by a known method, and using this as a mask, for example, phosphorus is implanted at 40 keV and 1 × 10 ¹³ atoms / cm ² to form a low concentration diffusion layer 5. Things.

FIG. 3C shows a known structure on the side wall of the gate electrode 3.
The sidewall 4 is formed by the method, and this is further masked.
Arsenic is 50 keV, 3 × 10^Fifteenatom /
cm ^TwoImplanted to form a high concentration diffusion layer 5
You.

FIG. 4A shows a first oxide film 6 made of, for example, a BPSG film having a thickness of, for example, 4000 .ANG. And SiON 7 having a thickness of, for example, 1000 .ANG. The first oxide film 6 functions as an insulating layer.

FIG. 4B shows that the SiON 7 and the first oxide film 6 are sequentially etched by a known method, a contact is opened, and tungsten is buried in the contact by a known method to form a tungsten plug 8. Things.
At this time, a common contact 15 extending over the gate electrode 3 and the diffusion layer 5 and a normal contact 16 on the diffusion layer 5 are simultaneously formed.

FIG. 4C shows a second oxide film 9 made of, for example, a 3000 .mu.m thick plasma oxide film. The second oxide film 9 functions as an insulating layer.

FIG. 5A shows a groove formed by removing the second oxide film 9 on a contact and a portion where a wiring is to be formed by a known method. At this time, SiON7
Can be used as an etching stopper. In this step, the surface of the tungsten plug of the normal contact 16 is exposed.

FIG. 5B shows an example in which a tungsten film having a thickness of 3000 ° is formed by a known method. In this step, tungsten is buried in the aforementioned groove. Further, the portion in the tungsten groove becomes the wiring tungsten 10 after the next step is completed.

FIG. 6A shows a wiring tungsten 10 formed by leaving tungsten only inside a groove by a known method.

FIG. 6B shows a third oxide film 11 formed of a plasma oxide film having a thickness of 2000 °, for example. The third oxide film 11 functions as an insulating layer. This figure shows the completed semiconductor device, which is the same as FIG.

FIG. 2 is a plan view of a memory cell of one full CMOS SRAM completed by the above steps. FIG. 7 shows an equivalent circuit diagram.

FIG. 2 shows that the common contact 15 is arranged at a position connecting the gate electrode 3 and the diffusion layer 5, and the normal contact 16 is arranged at a position connecting the diffusion layer 5 and the wiring tungsten 10. ing. The aluminum wiring 17 is formed after the step shown in FIG. 6B is completed, and is the same as the second aluminum wiring 19 of the conventional example.

In the other embodiments, only the parts different from the first embodiment will be described.

FIG. 2 shows a plan layout, and FIG. 8 shows a sectional view.

In this embodiment, the wiring tungsten 10 is not formed by burying it in the groove, but by patterning after forming a tungsten film. The tungsten on the common contact 15 is removed. Thereby, the wiring tungsten 10 and the common contact 15 are insulated. In this case, the number of steps can be further reduced as compared with the first embodiment.

[0046]

As described above, according to the present invention, the number of manufacturing steps can be reduced because the normal contact and the common contact can be formed in the same step.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device manufactured by a manufacturing method according to an embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor device manufactured by a manufacturing method according to an embodiment of the present invention.

FIG. 3 is a view illustrating a method of manufacturing a semiconductor according to an embodiment of the present invention;

FIG. 4 is a view illustrating a method of manufacturing a semiconductor according to an embodiment of the present invention;

FIG. 5 is a view illustrating a method of manufacturing a semiconductor according to an embodiment of the present invention.

FIG. 6 is a view illustrating a method of manufacturing a semiconductor according to an embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of the semiconductor device shown in FIG. 2;

FIG. 8 is a sectional view of a semiconductor device manufactured by a manufacturing method according to another embodiment of the present invention;

FIG. 9 is a cross-sectional view of a semiconductor device manufactured by a manufacturing method according to a conventional example.

FIG. 10 is a plan view of a semiconductor device manufactured by a manufacturing method according to a conventional example.

FIG. 11 is a view for explaining a method of manufacturing a semiconductor according to a conventional example.

FIG. 12 is a view illustrating a method of manufacturing a semiconductor according to a conventional example.

FIG. 13 is a view for explaining a method of manufacturing a semiconductor according to a conventional example.

FIG. 14 is a view illustrating a method of manufacturing a semiconductor according to a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate oxide film 3 Gate electrode 4 Side wall 5 Diffusion layer 6 First oxide film 7 SiON 9 Second oxide film 10 Wiring W 11 Third oxide film 15 Normal contact (W plug) 16 Common contact ( W plug) 17 Aluminum wiring 100, 101, 102, 103, 104, 105 Transistor

Claims (7)

[Claims] 1. A method for manufacturing a semiconductor device having a common contact not connected to an upper wiring and a normal contact connected to the upper wiring, comprising: forming a diffusion layer and a gate electrode on a semiconductor substrate; Forming a first insulating layer on a semiconductor substrate on which a layer and a gate electrode are formed; and forming a common contact and the normal contact simultaneously so as to penetrate the first insulating layer; And a method of manufacturing a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a second insulating layer after the step of forming a contact, and a portion of the second insulating layer on the normal contact. A method for manufacturing a semiconductor device, comprising: a step of removing a part; and a step of forming the upper wiring in the removed part. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of forming an etching stopper on a surface of said first insulating layer before said step of forming a contact. Manufacturing method. 4. The method for manufacturing a semiconductor device according to claim 2, further comprising a step of forming a third insulating layer on the upper wiring and the second insulating layer. A method for manufacturing a semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 1, further comprising, after the contact forming step, a step of forming a wiring material and patterning the wiring material to form the upper wiring. Semiconductor device manufacturing method. 6. The semiconductor device manufacturing method according to claim 1, wherein said common contact is formed so as to connect said gate electrode and said diffusion layer. Device manufacturing method. 7. The method for manufacturing a semiconductor device according to claim 1, wherein said normal contact is formed on said diffusion layer.