TW457660B - Flip chip packaging IC element module with molding-free ceramic substrate - Google Patents
Flip chip packaging IC element module with molding-free ceramic substrate Download PDFInfo
- Publication number
- TW457660B TW457660B TW089117125A TW89117125A TW457660B TW 457660 B TW457660 B TW 457660B TW 089117125 A TW089117125 A TW 089117125A TW 89117125 A TW89117125 A TW 89117125A TW 457660 B TW457660 B TW 457660B
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- Prior art keywords
- chip
- substrate
- aforementioned
- wafer
- ceramic substrate
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
457660 案號 89117125 修正 五、發明說明¢1) 1.摘要 本技藝採用無封膠晶片覆蓋式技藝，將晶片之球閘陣列輸 出入端點覆蓋耦合於具有陣列導電墊片之陶瓷基材，週邊 以金屬延伸腳突出於基材，完成有突出腳之無封膠陶瓷基 材覆晶封裝I C元件模組。 2.本技藝適用領域 本技藝適用於各種晶片之高散熱封裝，尤其是高腳數之晶 片之散熱封裝。 3.背景說明 習知技藝之晶月封裝，需要「保護膠體54」將元件封裝， 以保護各個元件之可靠度，參見圖十習知技藝，晶片5 0安 置在金屬腳架5 6上，晶片5 0上之各輸出入端點以打線5 2的 方式耦合於金屬腳架56之各個腳位，最後再以膠體54加以 封裝保護之。本技藝首先揭露不使用膠體為封裝的技藝， 實施例之一是以基材與晶片壓合以後即完成晶片封裝，省 略了習知技藝必須以「膠體」為晶片封裝之技藝。 4.圖示的簡單說明 圖一是本技藝第一實施例截面圖 圖二是本技藝基材之第一實施例頂面示意圖 圖三是圖一的分解示意圖 圖四是本技藝第二貫施例_晶片寬度與基材相同
第4頁 2001.08.01.004 457660 五、發明說明（2) 圖五是本技藝第三實施例_雙面晶片 圖六是本技藝基材之第二實施例頂面示意圖_雙面週邊導 電墊片 圖七是圖六的截面圖 圖八是本技藝第四實施例_雙面晶片封裝 圖九是本技藝應用於雙排腳封裝時之製程優勢 圖十是習知技藝 5.元件編號表 1 0陶曼基材 11晶片 1 2陣列導電墊片 1 3陶瓷壓板 14週邊導電墊片 1 5金屬導線 1 6金屬延伸腳 1 7開口 1 9隙縫 2 1晶片 2 2球閘陣列輸出入端點 23晶片 24週邊導電墊片 25陣列導電墊片 2 6金屬延伸腳
第5頁 457660 五、發明說明（3) 29隙縫 30切割線 31單片晶片封裂 32兩片晶片封裝 33二片晶片封裝 34四片晶片封裝 3 9隙缝 50晶片 52打線 54膠體 5 6金屬延伸腳 6 ·本技藝之詳細說明 圖一是本技藝第一實施例截面圖 圖中顯π陶瓷基材10，具有電路（圖中未表示）：基材1〇表 面t央有陣列導電墊片12，藉著基材1〇之單層電路或是多 層電路技藝’耦合至基材1〇的週邊導電墊片14，週邊導電 墊片14女置於基材1〇的第一面週邊至少一邊，也可以是兩 邊、二邊、或是四邊。當需要較多的輸出入端點時，基材 10的第二面也可以設計有週邊導電墊片14提供金屬延伸腳 1 6連接之用；晶片丨〗，具有球閘陣列輸出入端點22，球閘 陣列輸出入端點22以晶片覆蓋式技藝分別耦合於前述基材 10之陣列導電墊片1 2 ;金屬延伸腳1 6，耦合於前述之週邊 導電墊片I 4，作為前述晶片11之球閘陣列輸出入端點22之 5 7 6 6 0 五、發明說明（4) 延伸輸出入端點。基材1 〇與晶片丨丨之間的空間丨9，必要時 可以加入填充材料，提高封裝模組之可靠度。 本技藝以陶竞基材作為範例說明，實際實施時，其他高散 熱電性絕緣基材’例如：玻璃、石夕基材、藍寶石 (sapphire)基材、GaAs基材.·.等也是可以取代使用 的。 圖二是本技藝基材之第一實施例頂面示意圖 圖中顯示基材1 0的頂面視圖’顯示基材丨〇有陣列導電墊片 12，以及週邊導電墊片14，金屬導線15連接導電墊片12與 週邊導電墊片14，金屬延伸腳16耦合於週邊導電墊片η。 圖中是以左右兩邊每邊各一排之週邊導電墊片14為範例說 明’實際實施時’可以是一邊、二邊 '三邊、四邊有週邊 導電墊片14 ’也可以在基材的第二面製作導電塾片。 圖三是圖一的分解示意圖 圖中顯示壓板1 3具有中央開口 1 7，開口 1 7用以容納晶片 11，壓板1 3用以壓制在晶片11的周邊，壓制封裝遇邊之金 屬延伸腳16使其耦合於週邊導電墊片14。壓板的材料也是 用陶瓷或是其他高散熱電性絕緣材料。 圖四是本技藝第二實施例„晶片寬度與基材相同 圖中顯示當晶片2 1的面積大小與基材1 〇的面積大小相等或
第7頁
Claims (1)
- M4 Mill 25 3 457660 修正 六、申請專利範圍 1. 一種無封膠陶瓷基材覆晶封裝IC元件模組，包含·· 一片晶片或是一片以上之晶片，具有球閘陣列輸出入端 點； 基材，具有電路； 陣列導電墊片，安置於前述之基材表面至少一面，分別耦 合於前述之晶片之球閘陣列輸出入端點： 週邊導電塾片，安置於前述之基材至少一面之一邊； 金屬延伸腳，搞合於前述之週邊導電塾片’作為前述晶片 之球閘陣列輸出入端點之延伸輪出入端點。 2.如申請專利範圍第/項所述之無封膠陶瓷基材覆晶封裝 IC元件模組，其中所述之晶片平面面積等於或近似於所述 之基材平面面積。 如申請專利範圍第·-項=述之無封膠陶瓷基材覆晶封裝 1C元件模組，其中所述之邮片平面面積小於所述之基材平 面面積。 4.如申請專利範園第彡項所述之無封膠陶瓷基材覆晶封裝 IC元件模組，更包含： 曰 壓板，中央具有開口容納前述之曰日片，壓制在前述之晶片 週邊。 曰曰 5.如申請專利範圍第/項所述之無封膠陶竟基材覆第12頁 2001.08. 〇} 〇12
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW089117125A TW457660B (en) | 2000-08-21 | 2000-08-21 | Flip chip packaging IC element module with molding-free ceramic substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW089117125A TW457660B (en) | 2000-08-21 | 2000-08-21 | Flip chip packaging IC element module with molding-free ceramic substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW457660B true TW457660B (en) | 2001-10-01 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW089117125A TW457660B (en) | 2000-08-21 | 2000-08-21 | Flip chip packaging IC element module with molding-free ceramic substrate |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TW457660B (zh) |
-
2000
- 2000-08-21 TW TW089117125A patent/TW457660B/zh not_active IP Right Cessation
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