TW454351B - Manufacturing method for self-aligned insulated gate semiconductor device - Google Patents

Abstract

The present invention discloses a manufacturing method for insulated gate semiconductor device which includes the following steps: defining a contact between the gate structures; then, forming the channel region and the source region in the drain region. Next, depositing a layer of doped polysilicon layer covering both sides of the gate structures; using thermal diffusion process to form a region with heavier doping concentration in the source region; using etching and lithography processing to define a heavily doped channel region in the source region and using ion implantation process to dope the conductive dopant in the heavily doped channel region; after forming the channel region, removing the doped polysilicon layer to expose the source region; then, covering with silicon dioxide layer on the surface of gate structure as the insulated passivation layer and also covering part of the surface of the source; finally, depositing metal layer into the contact as the source electrode of the device.

Description

A7 B7 454351 V. Description of the invention (5) 5-1 Field of the invention: The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an insulated gate semiconductor device by using automatic alignment to reduce the parasitic double carrier effect. . 5-2 Background of the Invention: BJT is one of the most important semiconductor components. Although this component can be used as high-power components and high-speed logic circuits, it consumes a large amount of power during the operation. Energy has become the biggest drawback. Nowadays, the development of metal-oxide-semiconductor field-effect transistors (MOSFETs) has gradually replaced the application of bipolar transistors. Due to energy conservation, it has become the most commonly used semiconductor element in integrated circuits. In the general technology, the so-called Insulated Gate Semiconductor Device is the most common metal oxide semiconductor structure described above. The metal oxide half field effect transistor has an insulating layer of silicon dioxide, and uses polycrystalline silicon instead of metal as a gate. This metal oxide half field effect transistor consumes less power and is suitable for accumulation. Can withstand commercial temperature and increase component stability. However, the shortcomings of this component are higher sheet resistance and larger RC constant, and lower breakdown voltage. Therefore, general metal oxide semiconductor field effect transistors are not suitable as high power components. Please refer to the first figure, which shows the layout of the insulation gate semiconductor components. 2 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page). 11 --- 11 Order ---------. ^ ≫-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy / 1 ^ Λ ^ 1 Α7

V. Description of the invention () (Please read the precautions on the back before filling in this page) Figure, Section 11 and Section 22 shown in the first picture are shown in the second and third pictures, respectively, for a corresponding representation . Referring to the second figure, 70 insulated gate semiconductors are formed on the semiconductor substrate 100, and an N-type doped polycrystalline silicon layer 11 is formed on the semiconductor substrate 100. The channel region 120 and the source electrode 130 of the insulating gate semiconductor element are formed in an N-type doped compound silicon layer n0, and the N-type doped compound silicon layer ι10 is used as a drain region of the insulating gate semiconductor element. A plurality of gates are formed on the N-type doped polycrystalline silicon layer 110. The gate is composed of a hafnium oxide layer 140 and a polycrystalline stone layer 150, and then the surface of the gate is covered with a silicon dioxide layer 160. , As the insulating layer of the gate. Finally, a metal layer 170 'is deposited to cover the surface of the silicon dioxide layer 160, and is connected to the source electrode 130 as an electrical contact of the insulating semiconductor device. Please refer to the second figure. The structure of the insulated gate semiconductor device's source, channel, and extended drain region shown in the figure can be regarded as the emitter, channel, and collector regions of a parasitic NpN type bipolar transistor. When the parasitic transistor's emitter / collector interface (that is, the source / channel interface) is applied at room temperature with a forward bias greater than the barrier potential, the parasitic transistor Will be turned on 'and this barrier can be about 0.6 volts at room temperature. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the cooperative. According to Ohm's law, the potential drop between two points is equal to the current flowing between the two points, multiplied by the resistance value between the two points. Therefore, the voltage drop 'between the PN junction of the source / channel is affected by the resistance of the flowing current and surrounding materials. This voltage drop occurs at the lateral size of the source / channel PN junction 'as indicated by A in the third figure. Another factor limiting the preferred size A is the contact area between the source electrode and the source region, as shown in Figure 3 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) > '4 54 3 5 1 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. The position B marked by the invention description (). The size of the B position is affected by the size of the oxide layer i covering the gate surface, as indicated by the C position in the third figure. However, during the manufacturing process, the misalignment of the polycrystalline spar gate in the 'source region' will affect the minimum size of position A2. Therefore, there is a need for a manufacturing method capable of reducing the channel / source contact area of an insulated gate semiconductor device 'while reducing the influence of parasitic bipolar transistors', and reducing the number of times the mask is used, enhancing the efficiency of the device and simplifying the complexity of the process . 5-3 Purpose and Summary of the Invention: The present invention discloses a method for manufacturing an insulated gate semiconductor device, which uses an automatic alignment method to manufacture an insulated gate semiconductor device with a smaller source channel contact area, and at the same time reduces the resistance value of this contact area That is, reducing the possibility of turning on the parasitic bipolar transistor in the semiconductor device of the insulation gate, and effectively improving the efficiency of the semiconductor device of the insulation gate. The present invention discloses an insulated gate semiconductor device. The manufacturing method is as follows: Provide a semiconductor substrate, form a first polycrystalline silicon layer on the semiconductor substrate with a first polarity, and then form a first oxide layer to cover the first compound. A second polycrystalline silicon layer is formed on the crystalline silicon layer, having a first polarity, covering the first oxide layer, and forming a second oxide layer covering the second polycrystalline silicon layer. Then, the second oxide layer and the second polycrystalline silicon layer are etched, a contact window is defined, and the first oxide layer is exposed. The first ion implantation process is performed, and the second polycrystalline silicon layer is doped with a second-polar conductive impurity, and the first paper size is in accordance with the Chinese National Standard (CNS) A4 specification (21〇X 297). ) Γ Qi first read the note $ on the back before filling in this page) -------- Order --------- So. 454351 A7 ----------- --- V. Description of the invention () " The first channel region of the insulating gate semiconductor element is formed in the spar layer. In the second ion implantation process, in the first channel region, a first-polar conductive impurity is implanted to form a first-doped region. A third oxide layer is deposited, covering the second oxide layer and the first oxide layer. Then, "etch the second oxide layer and the first oxide layer" to expose the first doped region in the first channel region, and use the first oxide layer, the second polycrystalline stone layer, and the second oxide layer as the insulating spacers. Gate of a semiconductor element. A third polycrystalline gadolinium is deposited, covering the second oxide layer, the third oxide layer, and the first doped region. The third polycrystalline dream layer has a first polarity, and its conductive impurities will diffuse into the first doped region. Among them, a second doped region is formed in the first doped region. The doping concentration of the second doped region is greater than the doped concentration of the first doped region. The first doped region and the second doped region are formed. The miscellaneous region is used as a source region, and the third polycrystalline stone layer and the first polycrystalline hair layer are engraved by the money, exposing the first channel region. An ion implantation process is performed, and a second polar conductive impurity is doped into the first channel region to form a second channel region. The third polycrystalline silicon layer is removed, and a fourth oxide layer is deposited to cover the gate surface. Finally, a metal layer is formed to connect the first doped region 'as a metal contact. 5-4 Schematic illustrations: Many of the objects and advantages of the present invention will become easier to appreciate and understand by referring to the following detailed descriptions, while referring to the following drawings to illustrate, where: The first diagram is Layout diagram showing insulation gate semiconductor components in the conventional technology 'illustrates the top structure of the entire insulation gate semiconductor components. 5 This paper is compatible with Chinese National Standard (CNS) A4 (210 X 297 cm) (Please read the back first) (Please fill in this page again for the item of ίίϋ) 'Installation -------- Order i: ------- Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

Fig. 4543 5; The first diagram is a schematic cross-sectional view of an insulated gate semiconductor element in the first technology. This section is a schematic diagram of the η cross-section in the first diagram. The second ^ shows a cross-sectional view of an insulating semiconductor element in the conventional technology. 'This section is a schematic diagram of the 22 plane in the first diagram; the fourth diagram is a schematic diagram showing the cross-section of an insulated gate semiconductor device according to the present invention;' a sectional structure in which several film layers are formed on a semiconductor substrate; the fifth diagram _ Shows a schematic cross-sectional view of an insulating gate semiconductor element of the present invention. Among the film layers on a semiconductor substrate, a contact window of the insulating gate semiconductor element is defined; the sixth diagram is a schematic cross-sectional view showing the insulating gate semiconductor element of the present invention. A P-type doped region is formed in the layer as a channel region of the insulating gate semiconductor element. The seventh diagram is a schematic cross-sectional view of the insulating gate semiconductor element of the present invention. In the channel region of the insulating gate semiconductor element, an N-type semiconductor element is formed. Figure 8 shows a schematic cross-sectional view of an insulated gate semiconductor device of the present invention, and a silicon dioxide sidewall is formed to cover both sides of the film layer; Figure 9A is a first schematic cross-sectional view of an insulated gate semiconductor device according to the present invention. After forming a polycrystalline silicon layer, a trench is formed in the N-type doped region, and a P-type doped region is formed in the trench. Figure B is a second schematic cross-sectional view of an insulated gate semiconductor device according to the present invention. 'After forming a polycrystalline layer, a trench is formed in the N-type doped region, and a P-type doped region is formed in the trench. (Please (Read the note on the back before filling in this page)

454351 Printed A7 by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Figure 10A is a first schematic cross-sectional view showing the insulated gate semiconductor element of the present invention. The polycrystalline silicon layer on the surface is removed to expose the insulated gate semiconductor. The source region of the device; FIG. 10B is a second schematic cross-sectional view of the insulated gate semiconductor device according to the present invention. The polycrystalline silicon layer on the surface is removed to expose the source region of the insulated gate semiconductor device. The first cross-sectional schematic diagram of the insulated gate semiconductor device of the present invention is shown. A silicon dioxide layer is covered on the surface, and then a contact window of the insulated gate semiconductor device is defined, a channel region of the insulated gate semiconductor device is exposed, and a metal layer is filled to the contact. In the window, FIG. 11B is a schematic diagram showing a second cross-section of the insulated gate semiconductor device of the present invention, which is defined on the gate surface of the insulated gate semiconductor device—a layer of silicon dioxide layer exposes the source region of the insulated gate semiconductor device. Contact the channel region and backfill the metal layer above the channel region and the source region as metal contact; twelfth Based display layout of FIG insulated gate semiconductor device of the present invention, a display, and two cross-sectional directions of the source drain region and the channel of the insulated gate semiconductor element. 5-5 Detailed description of the invention: In the present invention, it is disclosed that an insulated gate semiconductor element 'has a smaller source / channel interface area, effectively reduces the parasitic bipolar transistor effect, and reduces the number of times the photomask is used. First define the absolute paper size on the semiconductor substrate and apply the Ningguo National Standard (CNS) A4 specification (2i0 x 297) (Please read the precautions on the back before filling this page) -Order -------! ^. 454351 V. Description of the invention () = Connection of the material element, and then form the channel area of the element, and then form the-^ replacement area in the insulation area. Then define The gate region of the pure edge gate + conductor element forms a compound crystal to protect the two sides of the gate structure, and defines a second p-type channel region of 7G pieces using a thermal diffusion process at the first N Stroke ^

A second N-doped region is formed in the sperm-doped region. Use ion implantation process to replace p-type conductive impurities

-In the channel area. Finally, the polycrystalline crane is removed, the N-type erbium-doped region 'of the element is exposed, and the metal layer is backfilled into the contact f as a metal electrode. In the above configuration, the first n-type doping region and the second n-type doping region are used as the source of the semiconductor device of the insulating gate to form a crystal. The preferred embodiment enumerated in the present invention is a Peng-type power transistor: but the method of the present invention can be used to make a general 7L piece of insulated semiconductors. Those skilled in the art must understand that with the manufacturing method of the present invention, only the polarity of doped impurities needs to be appropriately changed to produce a haze-type insulated gate semiconductor device. Printed by the Consumer Cooperative of the Smart Finance Bureau of the Ministry of Economic Affairs Please refer to the fourth figure to provide a semiconductor substrate 200 on which an insulated gate semiconductor element is manufactured. An N-type doped polycrystalline stone layer 21 is deposited to cover the surface of the semiconductor substrate 200, and then a stone dioxide layer 220 is deposited to cover the surface of the N-type doped polycrystalline silicon layer 21O. Next, an N-type doped polycrystalline silicon layer 230 is deposited to cover the surface of the silicon dioxide layer 22o, and finally a silicon dioxide layer 24 is deposited to cover the surface of the N-doped polycrystalline silicon layer 230 to form a A laminated structure on a semiconductor substrate 200. Please refer to the fifth figure. A photoresist is defined on the surface of the silicon dioxide layer 200. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love 4 5 4 3 5 1; the size of this paper is small.) A7 V. Description of the invention () Layer 400, which defines the contact window area of the semiconductor device of the insulating gate, and then uses an etching process to remove the silicon dioxide layer 24 and the N-type doped polycrystalline stone not covered by the photoresist layer 400. Layer 23o, exposing the surface of the dioxide layer 22o. In a preferred embodiment of the present invention, the method of etching the silicon dioxide layer 24o and the 1 ^ -type doped complex crystal second layer 230 is to use a non-uniform Anisotropic silver engraving process or general wet # engraving process. Please refer to the sixth figure for the ion implantation process, using a hard dioxide layer as the ion implantation mask, and an N-type doped polycrystalline spar layer. 21 P implanted p-type conducting dopant doped complex crystal layer 形成 forms a P-type doped region 25. This region is an N-type doped complex crystal located below the contact window. Among the sand layers 21G, it is used as the semiconductor gate area of the insulation gate. Please refer to the seventh figure for the ion implantation process. Dioxide 2 = Sub-planting mask, implanting the dioxin-layered coffee ions in the contact window, and implanting N-type conductive impurities into the 卩 -type doped region 25〇 ^ P-type doped region 250 —The N-type doped region is fine when you are in the contact window “1Γ 如 进” and it is located in the implantation process, for example, while performing the ion cloth here, 疋 :: Positive N-type ion cloth implantation process is in Ion decoration process

'. The silicon monoxide layer 240 is used as the ion implantation cover I. Impurities penetrate to other parts. Turn to prevent conduction. Deposition of oxygen: The second picture, after the above-mentioned ion implantation process, is followed by two t2 N-type doped polycrystalline osmium 230 and -oxidized H-layer, the surface of the fossil evening layer 220. In this post -------- Guang Zheng (Please read the notes on the back before filling this page)

---- Order ---------- ό ------ I ___-_________ I 4 6 4351 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Better implementation of the Ming In the example, the method for forming the silicon dioxide layer 270 is to use a chemical vapor deposition process. Referring again to the eighth figure, the silicon dioxide layer 27o and the silicon dioxide layer 240 are etched, and the silicon dioxide layer 27o and the silicon oxide layer 220 above the first N-type doped region 26o are removed, exposing the first An N-type doped region 26. After the etching process, a stacked structure of a silicon dioxide layer 220 and an N-type doped polycrystalline silicon layer 23 () is formed as a gate structure of an insulating gate semiconductor element, and the silicon dioxide layer 220 is used as a gate oxide layer. The silicon dioxide layer 27 is formed on the sidewalls of the silicon dioxide layer 240 and the N-type doped polycrystalline silicon layer 23o as a protective layer for the gate structure, avoiding the gate during subsequent processes, It is extremely affected by the process. Next, a polycrystalline silicon layer 280 is deposited on the semiconductor device of the insulating gate.

The surface is covered on the silicon dioxide layer 280, the silicon dioxide layer 27 and the first N-type plastic doped region 260. Then, the polycrystalline silicon layer 280 and the N-type doped polycrystalline stone layer 21 are etched. . Please refer to FIG. 9a and FIG. 9B. These two figures respectively illustrate the structure of the semiconductor device of the insulation gate from different sections. Based on the cross-section shown in Figure 9A, the polycrystalline silicon layer 280 on the top surface of the dioxide dioxide layer 240 has been removed, leaving only the sides of the dioxide belt layer 27 and the oxide monoxide layer 220. And forming an indentation groove between the polycrystalline silicon layers 280 by etching the n-doped polycrystalline silicon layer 210 at the same time. During the etching process of the polycrystalline silicon layer 280, the polycrystalline silicon layer 280 is used as an etching mask, and the polycrystalline silicon layer 280 is etched by using an etching selectivity between the polycrystalline silicon material and the polycrystalline silicon material. From the process, it can be seen that the silicon dioxide layer 240 is used as an etching protection layer to prevent duplicates. This paper size applies the Chinese National Standard (CNS) A4 specification (21〇χ 297 mm). (Please read the back Please fill in this page again for the matters needing attention)-..install ------- order ----! 丨 ·. ^ 45435 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Description of the invention () 230 takes the remaining damage. Please refer to ㈣ 九 ^ 目 ’, which shows the second

; 70 plane side: The 'multicrystalline dream layer 280 on the Γ plane is not only left on the other side of the dioxide dream layer, but is also covered on the N-type doped region 260 at the same time. In a preferred embodiment of the present month, the method for depositing the polycrystalline stone layer is to use a simultaneous doping chemical vapor deposition process (in situ d-cvd) and the doping polarity of the polycrystalline yarn layer 280 It is N type. After the polycrystalline stone layer 'deposition process, a thermal diffusion process is performed to form a second dopant doped region in the -N-type doped region 260 as shown in Figures 9a and 9b. The above-mentioned process for forming the second N-type doped region 265 is to first etch the polycrystalline spar layer 280 ′ and then perform the thermal diffusion process; another method is to use an advanced thermal diffusion process in the first N-type doped region 260. A second N-type doped region 265 is formed, and then an etching process is performed to define a contact window region. Then, the ion implantation process is performed, and the polycrystalline silicon layer 280 and the silicon dioxide layer 240 are used as the ion implantation mask, and a p-type conductive impurity is doped into the n-type doped polycrystalline stone layer 210 to form a second layer. The p-type doped region 255 is shown in FIGS. 9A and 9B. The first p-type doped region 250 and the second p-type doped region 255 are channel regions serving as an insulating gate semiconductor device. In a preferred embodiment, the doping concentration of the second p-type doped region 255 is greater than The doping concentration of the first P-type doped region 250. Please refer to Figure 10A and Figure 10B, respectively, to explain the removal of the polycrystalline silicon layer 280 from the rain section. After removing the polycrystalline silicon layer 280, the second 11 paper standards are applicable to Chinese national standards (CNS ) A4 size (210 X 297 mm) (Please read the notes on the back before filling this page)

454351 ‘Explanation of the invention (）) of the N-type doping region 265 >, Surface. In the preferred implementation of the present invention, the method for removing the polycrystalline stone layer 280 is to use the __ process dream layer and the dioxy-cut layer as a curtain to prevent the polycrystalline silicon layer 230 from being damaged by etching. Please fill in this page again for 1 doping item. Please refer to Figure 10-A and Figure 11B. The deposition-layer SiO2 layer 290 covers the surface of the closed electrode structure and removes part of the second n-type wiper. A layer of two gasified fossils above the miscellaneous region 265. The oxygen cut layer 290 is used as an insulation layer to isolate the gate and the source. In a preferred embodiment of the present invention, the composition material of the 'dream dioxide layer' is a pinch doped stone layer (BPSG) or a phosphorus-doped stone layer (pSG). Then, a deposition-layer metal layer 300 'covers the dioxide layer 29 and is filled in the contact south' to contact the second N-type doped region 265.

The structure shown in the eleventh circles A and eleventh B is a complete structure of an insulated gate semiconductor device, in which an N-type doped polycrystalline silicon layer 210 is used as the drain of the transistor. The N-type doped region 26 and the second N-type doped region 265 serve as the source of the transistor, forming a complete NpN-type transistor. In the method disclosed in the present invention, in the manufactured semiconductor device structure of the insulated gate, the interface between the source and the channel has been reduced to a minimum, and the contact area between the source electrode and the source is still relatively large. Effectively reduce the contact resistance between the source and the channel, and reduce the influence of the parasitic bipolar transistor. Please refer to the twelfth figure, which shows the layout of the insulated gate semiconductor element, and the ninth A, tenth A, and eleventh A are the 33 section of the twelfth figure; the ninth] 5th figure, Figures 10B and 11B are the twelfth and twelfth national standards (CNS) A4 specifications (210 X 297 public love) employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. Printed by cooperatives 454351 A7 " --- ------------- V. Description of the invention (wide ^ Figure 44 section. It can be clearly seen from the figure that the second N-type doped region 265 and the second channel region 255 The layout of the area is different from the conventional technology. By changing the structure design of the device, the bipolar effect of the semiconductor device of the insulation gate can be reduced. The present invention is described above with reference to the preferred embodiment, and those skilled in the art will not depart from it. Within the spirit of the present invention, when it can be modified slightly, the scope of its patent protection depends on the scope of the attached patent application and its equivalent fields.-----I. Equipment -------- Order ---------% 'Γ ------------------ · _! -— f Please read the notes on the back before filling this page) Paper size applicable to China Quasi (CNS) A4 size < 210 X 297 mm)

Claims (1)

Produced 4543 51 Printed by ASB8, C8, D8, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs, Patent Application 1. A method for manufacturing an insulated semiconductor device, including at least: providing a semiconductor substrate; forming a first polycrystalline silicon layer having a first A polarity covering the surface of the semiconductor substrate to form a first oxide layer covering the first polycrystalline silicon layer; forming a second polycrystalline silicon layer having a first polarity covering the first oxide Forming a second oxide layer covering the second polycrystalline silicon layer; etching the second oxide layer and the second polycrystalline silicon layer to form a contact window to expose the first oxide layer; Performing a first ion implantation process, doping a second polar conductive impurity into the first polycrystalline silicon layer, and forming a first channel region of an insulating gate semiconductor element in the first polycrystalline silicon layer; In a second ion implantation process, a first polar conductive impurity is implanted in the first channel region to form a first doped region; a third oxide layer is deposited, covering the second oxide layer and the first Of oxide Etch the second oxide layer and the first oxide layer, expose the first doped region in the first channel region, and use the first oxide layer, the second polycrystalline silicon layer, and the second An oxide layer is used as the gate of the insulating gate semiconductor element; a third polycrystalline second layer is deposited, covering the second oxide layer, the third oxide layer, and the first doped region, wherein the third polycrystalline silicon The layer has a first polarity, and its conductive impurities will diffuse into the first doped region, forming a second doped region in the first doped region. The doping of the second doped region (please read first Note on the back, please fill in this page again) Packing --- Ordering --------- Line / This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Afi B8 CS D8 Six Economy The Ministry of Intellectual Property Bureau employee consumer cooperative prints a patent application with a doping concentration greater than the doping concentration of the first doped region, and the first doped region and the second doped region are used as source regions; A polycrystalline silicon layer and the first polycrystalline silicon layer, exposing the first channel region; performing an ion implantation process, and doping A bipolar conductive impurity enters the first channel region to form a second channel region; removes the third polycrystalline silicon layer; deposits a fourth oxide layer to cover the gate surface; and forms a metal layer connected to the first channel region Two doped regions serve as metal contacts. 2. The method for manufacturing an insulated gate semiconductor element according to item 1 of the scope of the patent application, wherein the first polarity is N-type and the second polarity is p-type. The method for manufacturing an insulated gate semiconductor device according to item 1 of the scope of the patent application, wherein the first polarity is P-type and the second polarity is N-type. 4. The method for manufacturing an insulated gate semiconductor device according to item 1 of the scope of the patent application, wherein the second polycrystalline dream layer and the second oxide layer are etched using an anisotropic etching process. 5. The method for manufacturing an insulated gate semiconductor device as described in item i of the patent claim, wherein the ion implantation process for forming the first channel region in the -multi-crystalline silicon is using the second oxide layer. As an ion implanted curtain. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) i ----------- Q -------- Order i (Please read the precautions on the back first (Fill in this page again) 4543 5 1 A8 B8 C8 D8 Printed by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by cooperatives. 6. Scope of patent application. '' The ion implantation process in which the first doped region is formed uses the second oxide layer as an ion implantation mask. 7. The method for manufacturing an insulated gate semiconductor device according to item 1 of the scope of the patent application, wherein the ion implantation process for forming the second channel region uses the first oxide layer, the third oxide layer, and the third compound. The crystalline silicon layer is used as an ion-etching mask β 8 · The method for manufacturing an insulated gate semiconductor device as described in item 1 of the patent application scope, wherein the removal of the third polycrystalline silicon layer uses the second oxide layer and the second oxide layer as Etching the curtain. 9. A method for manufacturing a power transistor, comprising at least: providing a semiconductor substrate; forming a first polycrystalline silicon layer having a first polarity covering the surface of the semiconductor substrate; forming a first oxide layer covering the first oxide layer; Over a polycrystalline silicon layer; forming a second polycrystalline silicon layer with a first polarity covering the first chemical layer; # forming a second oxide layer covering the second polycrystalline silicon layer Etching the second oxide layer and the second polycrystalline silicon layer to form a contact window to expose the first oxide layer; performing a first ion implantation process, and doping in the first polycrystalline silicon layer 16 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I ------ (Please read the precautions on the back before filling this page) -—— — — III [111111 · ^ 1 -4543 2. The scope of patent application: The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a second-polar conductive impurity in the first-channel region of the semiconductor element of the first polycrystalline silicon layer; Yuanwen carried out the second ion implantation process in the In the first channel region, a polar conductive impurity forms a first doped region; a first oxide layer is deposited and deposited on the second oxide layer and the second oxide layer; and the second oxide layer is oxidized and etched. An oxide layer and the first oxide layer are exposed in the first doped region among the first and second regions, and the first oxide layer: the; a crystalline silicon layer and the second oxide layer are used as insulating gates. A third polycrystalline silicon layer is deposited on the semiconductor device to cover the second oxide layer, the first polarized layer, and the first doped region. The third polycrystalline hair layer has a polarity, which is Conductive impurities will diffuse into the first doped region to form a second doped region. The second doped region has a doping concentration greater than the doped concentration of the first doped region. , The first doped region and the second doped region are used as source regions; 'the third polycrystalline sand layer and The first—multicrystalline dream layer, exposing the first channel region; the ion implantation process is performed, and the doped m is transferred into the first channel region to form a second channel region, and the third polycrystalline silicon layer is removed; A fourth oxide layer covers the gate surface; and a metal layer is formed to connect the second doped region as a metal contact. The method for manufacturing power transistors described in item 9 of the patent application, including 17 paper sizes, is applicable to China National Standard (CNS) A4 (210 X 297 mm). Please read the notes on the back before filling out this page. 〕 ^ Ini --- order --- I line ο- 454351 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. In the scope of patent application, the first polarity is N-type, and the second polarity is p-type. 11. The method for manufacturing a power transistor according to item 9 of the scope of patent application, wherein the first polarity is P-type and the second polarity is N-type. 1 12. The method of manufacturing a power transistor according to item 9 of the scope of the patent application, wherein the second polycrystalline silicon layer and the second oxide layer are etched by using an anisotropic post-etching process. It is considered that the power transistor manufacturing method according to item 9 of the scope of patent application, wherein the ion implantation process for forming the first channel region in the first-multicrystalite layer uses the second oxide layer as ions Plant the curtain. 14. The method for manufacturing a power transistor according to item 9 of the patent application, wherein the ion implantation process for forming the first doped region uses the second oxide layer as an ion implantation mask. 15. If applying for a special shop _ 9 meal power transistor manufacturing method, the ion implantation process to form the second channel region is to use the second layer, the third oxide layer and the third compound. The spar stone layer acts as an ion mask. : Application for the power transistor manufacturing method described in item 9 of the patent, 1: = ;; crystal " layer is using the second gasification layer and the third oxygen ;: 18 This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297) (please read the precautions on the back before filling in this page) Λ ¥ -------- Order i Brigade A8B8C8D8 ^ 454351 VI. Application for patent scope 7.- Power transistors The manufacturing method includes at least: providing a semiconductor substrate; .m crystal 'layer' having a polarity 'covering the half material to form a second oxide layer, covering the first polycrystalline stone layer; forming a second complex layer , With N-type polarity, covered on the chemical layer; # Kai / Chengdi oxide layer, covered on the second polycrystalline hair layer; the second oxide layer and the second polycrystalline stone layer in the remaining moment Forming the first oxide layer; contacting the quotient, performing the first ion implantation process, rf polar conductive impurities are doped in the first compound crystal, and an insulating semiconductor is formed in the first compound crystal A first channel region of the element; performing a second ion implantation process, in the first channel region, Implanting a ^ -type polar conductive impurity m doped region; depositing a first oxide layer covering the second oxide layer and the first oxide layer; and carving the second oxide layer and the first oxide layer to expose The first-fifth impurity region in the first channel f, and the first oxide layer, the second complex layer, and the second oxide layer are used as gates of the insulating gate semiconductor element; A triple-polycrystalline silicon layer is overlaid on the second oxide layer, the third oxide layer and the first doped region, wherein the third polycrystalline silicon layer has a ^ -type polarity, and conductive impurities will diffuse to the Among the first miscellaneous areas, the 19 paper sizes are applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) (please read the precautions on the back before filling this page). -------- --Order --------- Line'_ Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed A8 E8 C8 D8 VI. Forming a second doped region, the doped concentration of the second doped region is greater than the doped concentration of the first doped region The first doped region and the second doped region are used as source regions; the third polycrystalline silicon layer and the first polycrystalline silicon layer are etched to expose the first channel region; an ion implantation process is performed, doping Doping p-type polar conductive impurities into the first channel region to form a second channel region; removing the third polycrystalline silicon layer; depositing a fourth oxide layer to cover the gate surface; and forming a metal layer connection The second doped region serves as a metal contact. 18. The method for manufacturing a power transistor according to item 17 in the scope of the patent application, wherein the second polycrystalline silicon layer and the second oxide layer are etched using an anisotropic etching process. 19_ The method for manufacturing a power transistor according to item 17 of the scope of patent application, wherein the ion implantation process for forming the first channel region in the first polycrystalline dream layer uses the second oxide layer as ions Plant the curtain. 20. The method for manufacturing a power transistor according to item 17 in the scope of the patent application, wherein the ion implantation process for forming the first doped region uses the second oxide layer as an ion implantation mask ^ 21. If applied The power transistor manufacturing method described in item π of the patent scope, 20 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) (please read the note § on the back before filling this page). -------- Order -------- line, 454351 A8 B8 C8 Ό8, the ion implantation process that forms the second channel region in the scope of patent applications, uses the second oxide layer, The third oxide layer and the third polycrystalline silicon layer serve as an ion etching mask. 22. The method for manufacturing a power transistor according to item 17 of the scope of the patent application, wherein the third polycrystalline silicon layer is removed by using the second oxide layer and the third oxide layer as a silver engraved mask. (Please read the precautions on the back before filling this page) Order --------- Printed by the Consumers and Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with China National Standard (CNS) A4 (210 X 297 mm)