451312 A7 經濟部智慧財產局員工消費合作社印製 —____!Z__五、發明説明（） 5 · 1發明領域 本發明係有關於一種高功率半導體元件的製造方法. 特別是有關於一種利用離子自動對準場氧化層植入，製 造達到具有低夾擊電阻及完全對稱特性之高功率半導體 元件的方法。 5-2發明背督 雙載子連接電晶體（BJT)爲現今最重要的半導體元件 之一，這種元件雖然可作爲高功率元件及高速邏輯電路 之用，但是在操作的過程之中，其最大的缺點爲會消耗 大量的能量。目前，金氧半場效電晶體（MOSFET)的發展， 已經逐漸取代了雙載子電晶體之應用，由於節省電能的 因故，成爲積體電路之中，最常使用的半導體元件。 在一般技術之中，所稱的絕緣閘半導體元件 (Insulated Gate Semiconductor Device)，最常見的就 如同上述之金屬氧化半導體結構。此金氧半場效電晶體 所使用之絕緣層爲二氧化矽，且利用多晶矽取代金屬作 爲閘極，此種金氧半場效電晶體的耗電量少且適合高積 集度，矽更能耐高溫而增加元件穩定度。但是這種元件 的缺點是層電阻（sheet-resistance)較高與RC常數較 _______2__________ 本紙張尺度逋用中困國家揉準（CNS ) A4規格（210 X 297公釐） (請先閲讀背面之注意事項 丨 再^^本頁 訂 ，線· ..My 451312 A7 經濟部智慧財產局員工消費合作社印焚 B7五、發明説明（） 大•而且崩潰電壓較低。因此，一般的金屬氧化半導體 場效電晶體並不適合作爲高功率元件。 高功率電晶體（Power Transistor)之特性在於其電流 處理能力更佳，而其汲極至源極之電壓約在50至100V 之間。最大之優點在於因爲其輸入電阻抗大，就算在開 關狀態，閘極電流依然很小。因此在控制閘極訊號時， 可以用小控制電流來切換大電流。高功率金氧半場效電 晶體爲了完成大通道以得到大電流，並經常以製造相同 晶胞的方式來並聯。 請參考第一圖，在傳統方式的高功率半導體元件製作中， 在重摻雜Ν型（或Ρ型）之半導體基材100上成長一層單 晶矽層105,再在Ν型單晶矽105之上定義閘極氧化層140 及多晶矽閘極150,並在Ν型單晶矽層105之中植入一輕 摻雜Ρ并區120，且再次在輕摻雜Ρ井區120中植入兩側 的重摻雜Ν井區130,做爲高功率半導體元件的源極，然 後覆蓋一層硼矽磷玻璃（BPSG) 160於多晶矽閘極150之上 以做爲絕緣層*而且兩側的重摻雜Ν井區130之間以重 摻雜Ρ井區180，以做爲重摻雜Ν井區的接觸窗 (contact)，最後再BPSG之上形成一接觸重摻雜Ν井區130 之金屜層170,以做爲高功率半導體元件金屬接觸。 依照第一圖傅統元件的設計，元件的操作是以重摻雜 N井區130爲源極，輕摻雜P井區120爲基體層，並以N 型單晶矽層105爲元件的汲極。電子先進入源極區，在 _i____ 本紙張尺度適用中8囲家揉準（CNS ) A相I格（2〖0Χ297公釐） <請先Μ讀背面之注$項再^k本頁) 訂 4513 12 A7 B7 經濟部智慧財產局S工消費合作社印製 五、發明説明（） 橫向進入閘極下反轉層後到N型摻雜單晶矽層1 〇5 ’電子 直向流經N型摻雜單晶矽層105到達汲極。在高功率半 導體元件的操作過程中，電流經由通道區域流動於源極 與汲極之間，在此產生了夾擊電阻《如果將通道區域加 寬，即可因爲降低夾擊電阻的大小而增加電流傳導能力， 但是卻亦會增大元件尺寸，影響積集度。所以需要一種 新的方法，改善高功率半導體元件中夾擊電阻的問題， 並且不影響高功率半導體元件的大小尺寸。 5 - 3發明目的與槪沭 本發明的主要目的爲提供高功率電晶體元件一種具 有良好對稱性的製作方法，在離子植入井區、基體、汲 極及源極的方法上，藉由使用完全自動對準之於場氧化 區，而達到具有良好對稱性的效果。 本發明的另一目的在於提供高功率電晶體元件一種提 昇多晶矽閘極下方之矽摻雜濃度的製作方法，在閘極建 立前先在閘極下方摻雜矽|使其矽濃度升高，就可以降 低元件之夾擊電阻。 本發明揭露一種高功率電晶體元件的製造方法，使用 離子會自動對準於場氧化區植入井區、基體、汲極及源 極之技術，製造具有良好對稱性的半導體元件，同時可 _、__5____ 本纸張尺度遑用中國國家揉準( CNS > A4规格（210X297公釐> ' A7 B7 451312 五、發明説明（） 以藉由提高閛極下方之矽濃度，得到降低元件夾擊電阻 之效果，有效改善高功率半導體元件的效能。 本發明揭露一種高功率電晶體元件，其製造方法如下 所述：在具有N型極性之半導體矽基材上形成第一磊晶 矽層，並在該磊晶矽層上沉積一氧化層與氮化矽層，以 光罩定義出閘極位置後蝕刻部分的氧化層與氮化矽層， 然後利用傅統之離子植入法輕摻雜N型雜質於閘極部位 的磊晶矽靥內，並利用爐管驅入將N型雜質熱擴散進入 該磊晶矽層內以降低夾擊電阻，同時於高溫下在閘極位 置長出場氧化區。接下來移除在閘極位置上場氧化區上 之氮化矽，之後自動對準場氧化區植入並驅入離子形成 基體區。在基體區中央經過圖案化光罩對準後，植入並 驅入離子進入磊晶層使形成源極》之後移除光罩層及場 氧化區層，並分別沉稹另一氧化層及多晶矽層，再以另 一光罩定義出閘極區域並蝕刻，後續製作保護層覆蓋、 接觸窗及導電連線。 5-4圖式簡單說明 由以下本發明中較佳具體實施例之細節描狀，可以對 本發明之目的、觀點及優點有更佳的了解。同時參考下 列本發明之圖式加以說明： 第一圖 爲一剖面圖，說明先前技術中高功率半導體元 本紙張尺度適用中國國家橾準（CNS > A4規格（210X297公釐） 請 先 鬩 讀 背 面 之 注 項 I 妾 經濟部智慧財是局8工消費合作社印製 A7 B7 _ 五、發明説明（） 件的結構； 第二圖 爲一高功率半導體元件剖面圖，說明本發明於 N型基材上形成具有N型極性之磊晶矽層、氧化 層、介電材料層及圖案後的光罩層之步驟： 第三圖 爲一高功率半導體元件剖面圖，說明本發明於 以圖案化後之光罩層爲罩幕，進行N型雜質的摻 雜； 第四圖 爲一高功率半導體元件剖面圖，說明本發明於 熱擴散後N型雜質形成N型井區及氧化層形成場 氧化區； 第五圖 爲一高功率半導體元件剖面圖，說明本發明摻 雜P型雜質以形成基體區之步驟； 第六圖 爲一高功率半導體元件剖面圖，說明本發明以 光罩層爲罩幕摻雜N型離子：及 第七圖 爲一高功率半導體元件剖面圖，說明本發明形 成源極區後移除光罩層。 第八圖 爲一高功率半導體元件剖面圖，說明本發明移 除氧化層之步驟； 第九圖 爲一高功率半導體元件剖面圖，說明本發明沉 積閘極氧化層及閘極多晶矽層：及 第十圖 爲一高功率半導體元件剖面圖，說明完成本發 明後續之定義閘極區、製作保護層覆蓋、接觸窗 及導電連線等製程後*完成之高功率半導體元件 本紙垠尺度適用中國國家揉準（CNS ) Α4规格（210Χ297公釐） η 先 閲 讀 背 ιέ 之 注 項451312 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ____! Z__ V. Description of the Invention () 5 · 1 Field of the Invention The present invention relates to a method for manufacturing a high-power semiconductor element. In particular, it relates to a method for automatically using ions. A method for implanting aligned field oxide layer to manufacture a high power semiconductor device with low pinch resistance and complete symmetry. 5-2 The invention of the BJT is one of the most important semiconductor components today. Although this component can be used as a high-power component and a high-speed logic circuit, during the operation, its The biggest disadvantage is that it consumes a lot of energy. At present, the development of metal-oxide-semiconductor field-effect transistors (MOSFETs) has gradually replaced the application of bipolar transistors. Due to energy saving, it has become the most commonly used semiconductor element in integrated circuits. In the general technology, the so-called Insulated Gate Semiconductor Device is the most common metal oxide semiconductor structure described above. The metal oxide half field effect transistor has an insulating layer of silicon dioxide and uses polycrystalline silicon instead of metal as the gate. This metal oxide half field effect transistor has less power consumption and is suitable for high accumulation, and the silicon is more resistant to high temperatures. And increase component stability. However, the disadvantage of this component is that the sheet resistance is higher and the RC constant is higher. _______2__________ This paper size is suitable for use in difficult countries (CNS) A4 size (210 X 297 mm) (Please read the back Note 丨 ^^ Order this page again, line .. My 451312 A7, Intellectual Property Bureau, Ministry of Economic Affairs, Employee Consumer Cooperative, B7, V5. Invention Description () Large, and the breakdown voltage is low. Therefore, the general metal oxide semiconductor field The effect transistor is not suitable as a high power component. The characteristics of a high power transistor (Power Transistor) is that its current handling capability is better, and its drain-to-source voltage is about 50 to 100V. The biggest advantage is because Its input impedance is large, even in the switching state, the gate current is still small. Therefore, when controlling the gate signal, a small control current can be used to switch the high current. The high-power metal-oxide-semiconductor half-effect transistor is used to obtain a large channel to obtain High current, and often connected in parallel to make the same unit cell. Please refer to the first figure, in the traditional high-power semiconductor device manufacturing, heavy doping A single-crystal silicon layer 105 is grown on a type (or P-type) semiconductor substrate 100, and a gate oxide layer 140 and a polycrystalline silicon gate 150 are defined on the N-type single-crystal silicon 105, and an N-type single-crystal silicon layer is formed. A lightly doped P well region 120 is implanted in 105, and heavily doped N well regions 130 on both sides are implanted again in the lightly doped P well region 120 as the source of a high power semiconductor element, and then covered. A layer of borosilicate phosphor glass (BPSG) 160 over polycrystalline silicon gate 150 as an insulating layer * and heavily doped N well regions 130 on both sides are heavily doped P well regions 180 as heavy doping A contact window in the N-well region, and finally a gold drawer layer 170 in contact with the heavily-doped N-well region 130 is formed on the BPSG as a metal contact for the high-power semiconductor element. The operation of the device is based on the heavily doped N-well region 130 as the source, the lightly doped P-well region 120 as the base layer, and the N-type single crystal silicon layer 105 as the drain of the element. The electrons enter the source region first. In the application of _i____ this paper standard (CNS) A phase I grid (2 〖0 × 297mm） < Please read the note on the back side first, then ^ k page) Order 4513 1 2 A7 B7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, S Industrial Consumer Cooperative, V. Description of the invention () After entering the inversion layer under the gate laterally, it reaches the N-type doped single crystal silicon layer 105. The electrons flow straight through the N-type doped The hetero-monocrystalline silicon layer 105 reaches the drain. During the operation of high-power semiconductor elements, current flows between the source and the drain via the channel region, which creates a pinch resistance. "If the channel region is widened, the current conduction can be increased by reducing the pinch resistance. Capability, but it also increases component size and affects the degree of accumulation. Therefore, a new method is needed to improve the problem of pinch resistance in high-power semiconductor elements without affecting the size of the high-power semiconductor elements. 5-3 Objects of the invention and the main purpose of the present invention is to provide a manufacturing method of high power transistor elements with good symmetry. In the method of ion implantation of the well region, the substrate, the drain and the source, by using Fully auto-aligned to the field oxidation area, to achieve the effect of good symmetry. Another object of the present invention is to provide a manufacturing method for increasing the silicon doping concentration under a polycrystalline silicon gate of a high-power transistor element. Before the gate is established, silicon is doped under the gate to increase the silicon concentration. Can reduce pinch resistance of components. The invention discloses a method for manufacturing a high-power transistor element. The technology of automatically aligning ions in a field oxidation region and implanting a well region, a substrate, a drain, and a source is used to manufacture a semiconductor element with good symmetry. __5____ This paper size is based on the Chinese national standard (CNS > A4 (210X297mm > 'A7 B7 451312) 5. Description of the invention () In order to reduce the pinch resistance of the component by increasing the silicon concentration under the pole This invention effectively improves the performance of high-power semiconductor devices. The present invention discloses a high-power transistor device, the manufacturing method of which is described as follows: a first epitaxial silicon layer is formed on a semiconductor silicon substrate with N-type polarity, and An oxide layer and a silicon nitride layer are deposited on the epitaxial silicon layer, and an oxide layer and a silicon nitride layer are etched after the gate position is defined by a photomask, and then N-type impurities are lightly doped by using a conventional ion implantation method. In the epitaxial silicon wafer at the gate, the furnace tube is used to drive the N-type impurities into the epitaxial silicon layer to reduce the pinch resistance. At the same time, field oxygen is grown at the gate at high temperature. Next, the silicon nitride on the field oxide region at the gate position is removed, and then the field oxide region is automatically implanted and driven into the ion to form the base region. After the patterned mask is aligned in the center of the base region, the After inserting and driving ions into the epitaxial layer to form the source, the photomask layer and the field oxide layer are removed, and another oxide layer and a polycrystalline silicon layer are sunk respectively. Then, another gate is used to define the gate region and Etching, subsequent production of protective layer covering, contact windows and conductive connections. 5-4 The schematic description of the following detailed description of the preferred embodiments of the present invention can better the purpose, perspective and advantages of the present invention. Understand. At the same time, please refer to the following drawings of the present invention for explanation: The first figure is a cross-sectional view illustrating that the paper size of the high-power semiconductor element in the prior art is applicable to the Chinese national standard (CNS > A4 specification (210X297 mm). Read the note I on the back 妾 The Ministry of Economic Affairs ’s Smart Finance is printed by the Industrial and Commercial Cooperatives of the Bureau A7 B7 _ V. Description of the invention () The structure of the device; The second figure is a cross-section view of a high-power semiconductor component, illustrating In the present invention, the steps of forming an epitaxial silicon layer, an oxide layer, a dielectric material layer, and a patterned photomask layer having an N-type polarity on an N-type substrate are as follows: The third figure is a cross-sectional view of a high-power semiconductor element, and illustrates the present invention. The invention uses the patterned photomask layer as a mask to dope N-type impurities; the fourth figure is a cross-sectional view of a high-power semiconductor element, illustrating that the N-type impurity forms an N-type well area after thermal diffusion and The oxide layer forms a field oxide region. The fifth figure is a cross-sectional view of a high-power semiconductor element, illustrating the steps of doping a P-type impurity to form a matrix region according to the present invention. The sixth figure is a cross-sectional view of a high-power semiconductor element, illustrating the present invention. The photomask layer is a mask doped with N-type ions: and FIG. 7 is a cross-sectional view of a high-power semiconductor element, illustrating that the photomask layer is removed after the source region is formed in the present invention. The eighth figure is a cross-sectional view of a high-power semiconductor element, illustrating the step of removing the oxide layer of the present invention; the ninth figure is a cross-sectional view of a high-power semiconductor element, illustrating the deposition of a gate oxide layer and a gate polycrystalline silicon layer according to the present invention: and Figure 10 is a cross-sectional view of a high-power semiconductor component, illustrating the completion of the subsequent processes of the present invention to define the gate region, the production of protective layer coverage, contact windows, and conductive connections. Standard (CNS) Α4 size (210 × 297 mm) η Read the notes of the back first
訂 經濟部智慧財產局8工消費合作社印製 5 經濟部智慧財產局貝工消費合作社印製 4 3 1 2 A7 B7 五、發明説明（） 的結構^ 5-5對照圖號說明 100半導體基材 105單晶矽層 U0磊晶矽層 120 Ρ井區 130Ν井區 140閛極氧化層 150多晶矽閘極 160硼矽磷玻璃（BPSG) 170金屬層 180重摻雜Ρ井區 210第一氧化層 220介電材料層 230光罩層 240第一極性離子 250高濃度Ν型井區 255場氧化層 260第二極性離子 270基體區 280第二光阻層 290第三極性離子 300源極區 310第二氧化靥 320多晶矽層 5-6發明詳細說明 本發明揭露一種高功率電晶體元件的製造方法’使用 離子植入井區'基體、汲極及源極會自動對準於場氧化 區之技術，製造具有良好對稱性的半導體元件，同時可 以藉由提高閘極下方之矽濃度，得到降低元件夾擊電阻 本紙伕尺度適用中國國家揉準（CNS > A4規格（210X297公釐） (請先Μ讀背面之注意事項寫本頁) -裝. 訂 -竦· 513 12 A7 B7 五、發明説明（） 經濟部智慧財產局員工消費合作社印製 之效果，有效改善高功率半導體元件的效能。 自第二圖至第十圖表示爲本發明使用於高功率半導體 元件架構上的具體實施例。請參考第二圖所述，首先提 供一具有極性之單晶半導體基材100,在本發明之較佳實 施例爲Ν型半導體基材100,竑在此Ν型半導體基材100 上長出一層帶有相同極性的磊晶矽層110,例如生成之Ν 型矽厚度約爲1〇4至106埃》接下來，於磊晶層110之上 以形成~薄第一氧化層210 |舉例來說，以加熱氧化法形 成厚度約爲103至104埃的氧化層》並且在第一氧化層上 再沉積一介電材料層220 »在較佳實施例中以化學氣相沉 積法（CVD)沉積厚度約爲1000至5000埃的氮化矽。之後 在一介電材料層2 20上形成一光罩層2 30,在圖案化光罩 230之後，即形成如同第二圖所示之結構。 請參考第三圖，以圖案化後的第一光罩層230爲罩幕， 進行對介電材料層220的蝕刻，例如使用乾式蝕刻的方 法進行非等向性蝕刻，以除去在閘極區域部位的介電材 料，此時閘極區域的第一氧化層210會暴露在外。在蝕 刻完成後，同樣的以圖案化後的第一光罩餍2 30爲罩幕， 摻雜進入與半導體基材100相同極性之第一雜質240,進 而植入並驅入第一雜質240至第一氧化層下之磊晶矽層 110中，以形成高濃度井區250。以本發明之實施例中爲 摻雜Ν型雜質，摻雜濃度約爲1〇13至l〇15i〇ns/cm2，此 時磊晶矽層110的閘極區域中會有較非閘極區域更高的 請 先 閲 讀 背 面 之 注 意 事 項Ordered by the Intellectual Property Bureau of the Ministry of Economic Affairs, 8 printed by the consumer cooperatives 5 Printed by the Intellectual Property Bureau of the Ministry of Economics, printed by the shelling consumer cooperatives 4 3 1 2 A7 B7 V. The structure of the description of the invention ^ 5-5 illustrates the semiconductor substrate with reference to the drawing number 105 single crystal silicon layer U0 epitaxial silicon layer 120 well region 130N well region 140 pole oxide layer 150 polycrystalline silicon gate 160 borosilicate phosphor glass (BPSG) 170 metal layer 180 heavily doped P well region 210 first oxide layer 220 Dielectric material layer 230 Photomask layer 240 First polar ion 250 High concentration N-type well region 255 Field oxide layer 260 Second polar ion 270 Matrix region 280 Second photoresist layer 290 Third polar ion 300 Source region 310 First 5-6 inventions of hafnium dioxide 320 polycrystalline silicon layer Detailed description The present invention discloses a method for manufacturing a high-power transistor element using the technology of "implanted well region", wherein the substrate, the drain and the source are automatically aligned with the field oxidation region. Manufacture a semiconductor device with good symmetry, and at the same time, reduce the pinch resistance of the device by increasing the silicon concentration under the gate. This paper is suitable for Chinese standards (CNS > A4 size (210X297 mm)) (Please Μ Read the notes on the back to write this page)-Binding. 竦-513 12 A7 B7 V. Description of the invention () The effect printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, effectively improving the performance of high-power semiconductor components. The second to tenth diagrams show specific embodiments of the present invention used in high-power semiconductor device architectures. Please refer to the second diagram, and first provide a polar single crystal semiconductor substrate 100. In the comparison of the present invention, A preferred embodiment is an N-type semiconductor substrate 100. On the N-type semiconductor substrate 100, an epitaxial silicon layer 110 with the same polarity is grown. For example, the thickness of the N-type silicon is about 104 to 106 angstroms. "Next, a thin first oxide layer 210 is formed on the epitaxial layer 110 | For example, an oxide layer with a thickness of about 103 to 104 Angstroms is formed by a thermal oxidation method" and then deposited on the first oxide layer A dielectric material layer 220 »In a preferred embodiment, a silicon nitride layer having a thickness of about 1000 to 5000 angstroms is deposited by chemical vapor deposition (CVD). A mask layer is then formed on a dielectric material layer 2 20 2 30, after patterning the photomask 230, it is formed as The structure shown in the second figure. Please refer to the third figure, and use the patterned first photomask layer 230 as a mask to etch the dielectric material layer 220, for example, to perform anisotropy using dry etching. Etching to remove the dielectric material in the gate area, the first oxide layer 210 in the gate area will be exposed at this time. After the etching is completed, the patterned first mask 餍 2 30 is also used as a mask. The first impurity 240 having the same polarity as the semiconductor substrate 100 is doped, and then the first impurity 240 is implanted and driven into the epitaxial silicon layer 110 under the first oxide layer to form a high-concentration well region 250. In the embodiment of the present invention, N-type impurities are doped, and the doping concentration is about 1013 to 1015 ns / cm2. At this time, the gate region of the epitaxial silicon layer 110 may have a non-gate region. For higher please read the notes on the back first
訂 〇線 本紙張尺度通用中國國家揉準（CNS ) A4规格（2丨0X297公釐） 513 12 A7 ___B7 五、發明説明（） 摻雜濃度’該更高的摻雜濃度可以在高功率半導體元件 的操作上降低夾擊電阻，使高功率半導體元件得到更佳 的表現。 隨後，以蝕刻移除圖案化後剩餘的第一光罩層230, 之後再參考第四圖’以接雜進入蓋晶砍層110的雜質240 進行擴散處理，舉例來說以熱擴散製程使用熱爐管在1000 至2000°C的溫度驅入，形成了低摻雜的高濃度井區250。 同時第一氧化層亦在閘極區域位置上形成場氧化區255。 接下來分別移除在介電材料層220上的第一光罩層23 0 及第一氧化層210上的介電材料層220。以場氧化層255 爲罩幕，做第二離子260植入並驅入，使第二離子260 進入第一氧化層下的磊晶矽層內。在本發明實施例中採 用離子植入的方法植入並驅入P型離子進入磊晶矽層110 中，摻雜濃度約爲1013至10l5ions/cm2，以形成基體區 270，即形成第五圖之結構。 參考第六圖，在位於場氧化層255區間之基體區的中 央部位，形成Μ圖案化第二光阻層280。並以第二光罩層 280爲罩幕，將第三離子290自動對準場氧化區，摻雜進 入位於元件端、磊晶層110內的基體區270中。如同第 七圖所示之本發明之實施例中，採用離子植入的方法植 入並驅入Ν型離子形成源極區300。 接下來，參考第八圖所示|移除剩餘的場氧化層255 及第一氧化層210。並在磊晶矽層U0中的高濃度井區 本紙乐尺度適用中固國家樣率（CNS ) A4規格（210X297公釐） ;-------装-- (請先Μ讀背面之注意事項本頁) •11〇〇 The size of this paper is universal Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) 513 12 A7 ___B7 V. Description of the invention () Doping concentration 'This higher doping concentration can be used in high power semiconductor components The pinch resistance is reduced in the operation, so that the high-power semiconductor components get better performance. Subsequently, the first photomask layer 230 remaining after patterning is removed by etching, and then referring to the fourth figure 'doping the impurities 240 into the capping layer 110 for diffusion treatment, for example, using a thermal diffusion process using heat The furnace tube is driven at a temperature of 1000 to 2000 ° C, and a low-doped high-concentration well region 250 is formed. At the same time, the first oxide layer also forms a field oxide region 255 on the gate region. Next, the first mask layer 23 0 on the dielectric material layer 220 and the dielectric material layer 220 on the first oxide layer 210 are removed, respectively. With the field oxide layer 255 as a mask, a second ion 260 is implanted and driven in, so that the second ion 260 enters the epitaxial silicon layer under the first oxide layer. In the embodiment of the present invention, an ion implantation method is used to implant and drive P-type ions into the epitaxial silicon layer 110 with a doping concentration of about 1013 to 1015ions / cm2 to form a matrix region 270, that is, a fifth figure is formed. The structure. Referring to the sixth figure, an M-patterned second photoresist layer 280 is formed at the center of the base region located in the field 255 interval. Using the second photomask layer 280 as a mask, the third ion 290 is automatically aligned with the field oxidation region and doped into the base region 270 located at the element end and within the epitaxial layer 110. As in the embodiment of the present invention shown in FIG. 7, the N-type ions are implanted and driven by the ion implantation method to form the source region 300. Next, referring to FIG. 8, the remaining field oxide layer 255 and the first oxide layer 210 are removed. And in the high concentration well area of epitaxial silicon layer U0, the paper scale of the paper is applicable to the national solid sample rate (CNS) A4 specification (210X297 mm); (Notes on this page) • 11
-線 C 經濟部智慧財產局員工消費合作社印製 A7 B7 451312 五、 發明説明（） 請 先 閱 讀 背 面 Ϊ 事 項 再. 250 '基體區270及源極區300上形成一第二氧化層310， 做爲閘極氧化層，例如使用加熱氧化法的方式沉積一層 厚度約102至103埃的二氧化矽。然後，在第二氧化層310 上再沉稹一層多晶矽層320，做爲多晶矽閘極之用，在本 發明之具體實施例中，以CVD方式沉積厚度約1〇3至104 埃的多晶矽》形成之結構即如同第九圖所示》 再接著利用另一光罩層定義出閘極區域，然後圖案化 並蝕刻多晶矽層320及第二氧化層3 1 0，舉例來說使用乾 式蝕刻，定義出閘極的範圍後，移除閘極區域以外的多 晶矽與氧化物，此時，在磊晶矽層110上只有多晶矽閘 極及閘極氧化層（未以圖面表示）。 訂 (> 接下來的製程可利用一般的做法：形成一保護層160， 例如硼矽磷玻璃（BPSG)，覆蓋於多晶矽閘極320及閘極 氧化層310，以做爲絕緣層》最後在保護層160之上形成 —接觸源極區3 00之金靥層170，做爲高功率半導體元件 金靥接觸，以形成高功率半導體元件的結構，如第十圖 所示。 經濟部智慧財產局Μ工消費合作社印製 本發明以較佳之具體實施例敘述如上，僅用於藉以 幫助了解本發明之實施，非用以限定本發明之精神，而 熟悉此領域技藝者於領悟本發明之精神後，凡其它未脫 離本發明所揭示之精神下，所完成之些許更動潤飾及 等效之改變或修飾，其專利保護範圍當視包含在下述 之申請專利範圔及其等同領域而定。 本紙張尺度適用中國國家揲準（CNS > Α4说格（210X297公釐）-Line C Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 451312 V. Description of the invention () Please read the following Ϊ Matters first. 250 ′ A second oxide layer 310 is formed on the base region 270 and the source region 300. Do For the gate oxide layer, for example, a layer of silicon dioxide with a thickness of about 102 to 103 angstroms is deposited by a thermal oxidation method. Then, a second polycrystalline silicon layer 320 is deposited on the second oxide layer 310 as a polycrystalline silicon gate. In a specific embodiment of the present invention, a polycrystalline silicon having a thickness of about 103 to 104 angstroms is deposited by CVD. The structure is as shown in the ninth figure. Then, another gate layer is used to define the gate area, and then the polycrystalline silicon layer 320 and the second oxide layer 3 1 0 are patterned and etched. For example, dry etching is used to define After the gate range, polycrystalline silicon and oxides outside the gate region are removed. At this time, there is only the polycrystalline silicon gate and the gate oxide layer (not shown in the figure) on the epitaxial silicon layer 110. (≫ The next process can use the general method: forming a protective layer 160, such as borosilicate phosphor glass (BPSG), covering the polycrystalline silicon gate 320 and the gate oxide layer 310 as an insulating layer. "Finally in Formed on the protective layer 160-contact the gold layer 170 of the source region 300, as a high-power semiconductor element contact, to form the structure of the high-power semiconductor element, as shown in Figure 10. Intellectual Property Bureau, Ministry of Economic Affairs The printing of the present invention by the MG Consumer Cooperatives is described in the preferred specific embodiments as described above, and is only used to help understand the implementation of the present invention. It is not intended to limit the spirit of the present invention. Those skilled in the art will appreciate the spirit of the present invention. For any other changes or modifications that are completed without departing from the spirit disclosed by the present invention, the scope of patent protection shall be determined by the scope of patent applications and their equivalents included in the following. Standards apply to Chinese National Standards (CNS > Α4 grid (210X297 mm)