1310590 玖、發明說爾 . (發明說明應敘明：發賴屬之技術領域、絲技術、内容、實施方式及圖式簡單說明） 發明所屈技術領域： 本發明與一種半導體元件製程有關，特別是有 關一種溝渠式功率金氧半場效電晶體元件之製作 方法。 先前技術= 雙載子連接電晶體（BJT)為現今最重要的半導 體元件之一，這種元件雖然可作為高功率元件及 高速邏輯電路之用，但是在操作的過程之中，其 最大的缺點為會消耗大量的能量。目前，金氧半 場效電晶體（M0SFET)的發展，已經逐漸取代了雙 載子電晶體之應用’由於節省電能的因故，成為 積體電路之中，最常使用的半導體元件。 在-般技術之中，所稱的功率I氧半場效電晶 體（POWER Mosm)基本操作和任何的金氧半場效 電晶體相肖，但是電流處理能力在安培範圍，汲 極至源極的阻隔電壓約20V〜1 200V或是更高，功 =氧半場效電晶體的優點是，控制訊號施加於 ::共輸入阻抗大’即使在開關狀態，閘極電 仅小，因此，可以使用小控制電壓來切換大 1310590 電流。 請參閱第-圖，為傳統高功率半導體元件之結 構刮面示意圖。纟重摻雜㈣（或？型）半導體基 材100之上，蠢晶成長一 g N型梦蟲晶層i i 2，然 二’在N型矽磊晶層112之上定義出複晶矽閘極 0在N型矽磊晶層112之中，形成一輕摻雜p1310590 玖, invention said er. (The invention should be stated: the technical field, silk technology, content, implementation and graphic description of the genus It relates to a method for manufacturing a trench type power MOS half field effect transistor component. Prior Art = Bi-Sub-Connected Transistor (BJT) is one of the most important semiconductor components today. Although it can be used as a high-power component and high-speed logic circuit, its biggest disadvantage in the process of operation. It will consume a lot of energy. At present, the development of metal oxide half field effect transistors (M0SFETs) has gradually replaced the application of bipolar transistors. As a result of saving electrical energy, it has become the most commonly used semiconductor component among integrated circuits. In the general technology, the so-called power I oxygen half field effect transistor (POWER Mosm) basic operation and any gold oxide half field effect transistor phase, but the current processing capability in the amperage range, bungee to source barrier The voltage is about 20V~1 200V or higher. The advantage of the power=oxygen half-field effect transistor is that the control signal is applied to:: The total input impedance is large. Even in the switching state, the gate is only small, so small control can be used. The voltage is used to switch the large 1310590 current. Please refer to the figure-figure for a schematic diagram of the structure of a conventional high-power semiconductor device. On the heavily doped (four) (or ?) semiconductor substrate 100, the stupid crystal grows a g-type N-type dream crystal layer ii 2, but the second 'defined on the N-type germanium epitaxial layer 112 A pole 0 is formed in the N-type germanium epitaxial layer 112 to form a lightly doped p
，區108’作為功率金氧半場效電晶體的通道區 jBocly)，在輕摻雜p井區1〇8之中，形成兩個重 務雜N114 ’作為功率半導體的源極。最後， :兩個重摻雜N井區114之上，形成一金屬層並接 重摻雜N井區，作為功率半導體之源極 觸102與1〇4 。 按 依照第一圖的元件設計，整個元件的操作是以 換雜N井區114作為源極，而輕摻雜p井區 是作為通道區，然後再以重摻雜N型矽基材1〇〇The region 108' serves as the channel region jBocly of the power MOS field-effect transistor, and among the lightly doped p well region 1 〇8, two heavy-duplexes N114' are formed as the source of the power semiconductor. Finally, over the two heavily doped N well regions 114, a metal layer is formed and heavily doped with the N well region as the source of the power semiconductor contacts 102 and 1〇4. According to the component design according to the first figure, the operation of the entire component is to replace the N well region 114 as a source, and the lightly doped p well region is used as a channel region, and then heavily doped with an N-type germanium substrate. 〇
=7C件的没極，電子進人源極區，並橫向通過 甲和下反轉層而到\型摻雜磊晶矽層112，電子將 垂直机經N型摻雜磊晶矽層112到達汲極1 〇 〇。 然而，隨著積體電路之製程進入超大型 路（ULSI)，ΛτΑ接雜# Α 趙電 ^ ^為了在積體電路的設計上符合高積極 又 ’，且繼績縮小諸元件所需之空間與維 度且同時兼顧所製造元件之操作性能，g卩為银 階段最重要之要求。而另一方面，電流流動= 極與;及極之間’若源極與 >及極間之距離越長，則 7 1310590 電阻亦會越大’因此如何降低此部分之電阻，亦 為另一重要課題。 發明内容： 鑒於上述之發明背景中，傳統功率金氧半場效 電晶體之平面設計不利於提升元件製程密度之要 求下》因此為了在積體電路的設計上符合高積極 度之需求，本發明將傳統功率元件之閘極結構， 由平面設計朝向立體設計，將閘極結構設計成於 半導體底材上的溝渠中，且源極與汲極分別鄰接 於該垂直溝渠式閘極結構之上下兩端，是以可有 效的降低製造整個電晶體所需之空間。且另一方 面，本發明之閘極結構係直接與汲極區接觸，因 此可有效的降低源極與汲極間之電阻。 因此本發明之主要目的為提供一種高密度高功 率半導體元件及其製造方法，在源極區與汲極區之 間形成溝渠式的閘極結構，提升高功率半導體元件 的電流流通能力。 根據上述之目的，本發明提出一種溝渠式高功 率半導體元件及製造方法’製造方法包含下列步 驟.首先’首先制-4摻雜之N型半導體基板作 為汲極之用，再於此基板上依序沉積一 p型磊晶 層。接著利用一光阻層定義出閘極區域，並對半= 1310590 曰曰圓進行蝕刻，以定義出溝渠圖案於半導體基板 上再沿著該溝渠結構之表面形成閘極氧化層，且 形成摻雜多晶矽層以填充於溝渠結構中。接著，分 別形成兩極性相反之摻雜區域於半導體底材中。其 令摻雜區域鄰接於該溝渠結構作為源極，而另一摻 雜區域則為深基體區。隨後，形成一介電層於該半 導體底材之上表面，並進行接觸窗蝕刻，並填入金 屬層。 實施方式： 在不限制本發明之精神及應用範圍之下，以下 即以一實施例，介紹本發明之實施；熟悉此領域技 藝者’在瞭解本發明之精神後，當可應用本發明之 高功率半導體元件結構與其製程方法於多種不同 的功率電晶體製程中。藉由本發明溝渠式閘極結 構’不僅可提升元件之積集度，且本發明之溝渠式 閘極結構係直接接觸於沒極區，因此源極區之電子 可直接經由閘極旁之反轉層進入汲極區，因此可有 效的降低源極與汲極間之電阻。本發明之應用當不 僅限於以下所述之實施例。 首先參考第二圖，提供一個N +型或是p+型的半 導體底材（substrate) 200，在其上面形成一層蟲 晶層2 0 4，在本發明的較佳實施例中以p型的蟲晶 1310590 破為例，蟲晶層204濃度約1013〜l〇15cm-3，以作為所 欲形成的半導體元件之基體（body)區域，其中基 體區與半導體底材之極性相反》舉例來說，蟲晶 層204可以化學氣相沉積法（Chemical Vapor· Deposition, CVD)法加以形成之。接著，在p型基 體區204上使用光罩（未圖示），並進行曝光、顯 影以暴露出P型基體區204之上表面，並形成一光 阻圖案層206，定義出溝渠式閘極區域。 隨後，如第三圖所示使用光阻圖案層206作為 餘刻罩冪，對半導體底材200與p型基體區2〇4進行 钮刻程序’以形成溝渠結構208於半導體底材200 上。以較佳實施例而言，此姓刻步驟利用非等向 性反應離子蚀刻製程（reactiVe etch ; RIE) 來對P型基體區2 0 4進行蝕刻以形成溝渠結構 208，其中此溝渠結構2〇8之蝕刻深度需至少能接 觸到半導體底材200 ’接著移除光阻圖案層2〇6。 接著請參照第四圖所示，接著沿溝渠結構2〇8 之表面形成薄閘極氧化層21 〇。一般而言，此閘極 氧化層210可在溫度約700至n〇(rc且充滿氧氣之 環境中’進行熱氧化程序加以形成，且所製造之 閘極氧化層210其厚度大約是數百至數千埃。接 著形成摻雜多晶石夕層（doped polysilicon)212 以填充於溝渠結構2 〇 8之中，以作為後續所形成高 功率電晶體之溝渠式閘極結構。 10 1310590 -般而纟’可先形成_摻雜多晶發層於該半導 體底材2〇〇上，且填充於該溝渠結構2〇8中。再藉 著對該摻雜多晶石夕層進行回钮刻程序，以移除位 於P型基體區204上表面之摻雜多晶矽層，並使殘 餘摻雜多晶矽層212與閘極氧化層21 〇其上表面低 於P型基體區204上表面，μ此摻雜多晶㈣212 係作為閘極。亦即形成如第四圖中具有凹陷上表 面之摻雜多晶矽層212。值得注意的是上述摻雜多 晶矽層212亦可使用其它導電材料來加以取代。例 如可使用同步摻雜多晶石夕（in_situ d〇ped Polysilicon)、銅、鋁、鈦、鎢、白金或合金等 來作為上述閘極之材料。 參照第五圖所示，形成一圖案化光阻層（圖中 未展示出），此光阻層係用以形成p型深基體區 216。接著以此光阻層為罩幕，進行p型深基體區 216之製程，其係利用佈植製程及高溫擴散法進行 推雜’於P型基體區204中形成p型深基體區216， 其中商溫擴散法的溫度介於5〇〇至2〇〇〇。(3之間，摻 質例如可為硼，離子佈植的濃度介於1χ1〇15至 7χ1 015/cm3 ° 接著移除此圖案化光阻層，並形成另一圖案 化光阻層（圖中未展示出），其中此圖案化光阻 層係用以形成源極區域。以此圖案化光阻層為罩 幕，對該P型基體區204進行離子植入，以便形成 1310590 推雜區域於P型基體區204中，作為所製造電晶體 之源極區域21 8。其中該摻雜區域鄰接於閘極氧化 層21 0，亦即在該溝渠結構2 〇 8之側壁上方，形成 源極區域218。源極區域218佈植的濃度介於1><1〇15 至7x1 015/cm2。此外’源極區域218離子佈植的電性 與深基體區216的電性相反。 接者進行接觸窗之製作，首先形成一介電層220 以覆蓋於Ρ型基體區204與摻雜多晶矽層212之上 表面。此介電層220例如可為麟；ε夕玻璃（ps(j)或是 领磷矽玻璃（BPSG)，其中利用常壓化學氣相沉積 (Atmospheric Pressure Chemical Vapor Deposition，APCVD)法沉積磷矽玻璃（ρ%)，而以 電黎·增強化學氣相沉積（PIasma_enhance(j=7C piece of the pole, the electron enters the source region, and laterally passes through the armor and the lower inversion layer to the \ type doped epitaxial layer 112, and the electron reaches the vertical machine through the N-type doped epitaxial layer 112 Bungee 1 〇〇. However, as the process of the integrated circuit enters the super-large-scale road (ULSI), the ΛτΑ 杂 # Α 电 电 为了 ^ ^ In order to meet the high positive and positive in the design of the integrated circuit, and the space required to reduce the components With dimensions and at the same time taking into account the operational performance of the components manufactured, g卩 is the most important requirement in the silver phase. On the other hand, current flow = pole and; and between the poles, if the distance between the source and the > and the pole is longer, the resistance of the 7 1310590 will also increase. So how to reduce the resistance of this part is also another An important topic. SUMMARY OF THE INVENTION In view of the above-mentioned background of the invention, the planar design of the conventional power MOS field-effect transistor is not conducive to the requirement of increasing the process density of the component. Therefore, in order to meet the high positivity requirement in the design of the integrated circuit, the present invention will The gate structure of the conventional power component is designed from a planar design to a three-dimensional design, and the gate structure is designed to be in a trench on the semiconductor substrate, and the source and the drain are respectively adjacent to the upper and lower ends of the vertical trench gate structure. In order to effectively reduce the space required to manufacture the entire transistor. On the other hand, the gate structure of the present invention is in direct contact with the drain region, thereby effectively reducing the resistance between the source and the drain. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a high-density, high-power semiconductor device and a method of fabricating the same that form a trench-type gate structure between a source region and a drain region to improve current flow capability of a high-power semiconductor device. According to the above object, the present invention provides a trench type high power semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps. First, a first -4 doped N-type semiconductor substrate is used as a drain electrode, and then on the substrate. A p-type epitaxial layer is deposited. Then, a photoresist region is defined by a photoresist layer, and a half = 1310590 circle is etched to define a trench pattern on the semiconductor substrate and then a gate oxide layer is formed along the surface of the trench structure, and doping is formed. The polysilicon layer is filled in the trench structure. Next, doped regions of opposite polarities are formed in the semiconductor substrate, respectively. The doped region is adjacent to the trench structure as a source and the other doped region is a deep matrix region. Subsequently, a dielectric layer is formed on the upper surface of the semiconductor substrate, and contact window etching is performed, and the metal layer is filled. The embodiments of the present invention are described below by way of an embodiment without departing from the spirit and scope of the invention. Those skilled in the art will understand that the invention can be applied Power semiconductor component structures and their fabrication methods are used in a variety of different power transistor processes. The ditch-type gate structure of the present invention not only enhances the integration of components, but also the trench gate structure of the present invention directly contacts the non-polar region, so that the electrons in the source region can be directly inverted by the gate. The layer enters the drain region, thus effectively reducing the resistance between the source and the drain. The application of the present invention is not limited to the embodiments described below. Referring first to the second figure, an N + -type or p-type semiconductor substrate 200 is provided on which a layer of insect crystals 204 is formed, in the preferred embodiment of the invention a p-type insect For example, in the case of the crystal 1310590, the concentration of the crystal layer 204 is about 1013 〜1 〇 15 cm-3 as the body region of the semiconductor element to be formed, wherein the substrate region is opposite in polarity to the semiconductor substrate, for example, The worm layer 204 can be formed by a chemical vapor deposition (CVD) method. Next, a photomask (not shown) is used on the p-type base region 204, and exposure and development are performed to expose the upper surface of the P-type base region 204, and a photoresist pattern layer 206 is formed to define a trench gate. region. Subsequently, the photoresist substrate layer 206 is used as a mask power as shown in the third figure, and the semiconductor substrate 200 and the p-type substrate region 2〇4 are subjected to a bonding process to form the trench structure 208 on the semiconductor substrate 200. In a preferred embodiment, the surname step utilizes an anisotropic reactive ion etching process (RIE) to etch the P-type body region 220 to form a trench structure 208, wherein the trench structure 2〇 The etching depth of 8 needs to be at least accessible to the semiconductor substrate 200' and then the photoresist pattern layer 2〇6 is removed. Next, referring to the fourth figure, a thin gate oxide layer 21 形成 is formed along the surface of the trench structure 2〇8. In general, the gate oxide layer 210 can be formed by a thermal oxidation process at a temperature of about 700 to n 〇 (rc and filled with oxygen), and the gate oxide layer 210 is manufactured to a thickness of about several hundred to Thousands of angstroms. A doped polysilicon 212 is then formed to fill the trench structure 2 〇8 as a trench gate structure for the subsequent formation of a high power transistor. 10 1310590 -纟' may first form a _doped polycrystalline layer on the semiconductor substrate 2〇〇, and fill in the trench structure 2〇8, and then perform a loopback procedure by using the doped polycrystalline layer To remove the doped polysilicon layer on the upper surface of the P-type body region 204, and to make the residual doped polysilicon layer 212 and the gate oxide layer 21 have an upper surface lower than the upper surface of the P-type substrate region 204, such as doping Polycrystalline (tetra) 212 is used as a gate. That is, a doped polysilicon layer 212 having a depressed upper surface as in the fourth figure is formed. It is noted that the doped polysilicon layer 212 may be replaced with other conductive materials. For example, it may be used. Synchronous doping of polycrystalline stone (in_situ d Ped Polysilicon), copper, aluminum, titanium, tungsten, platinum or alloy, etc. as the material of the gate. Referring to the fifth figure, a patterned photoresist layer (not shown) is formed, the photoresist layer The utility model is used for forming a p-type deep base region 216. Then, the photoresist layer is used as a mask to carry out the process of the p-type deep base region 216, which is carried out by the implantation process and the high-temperature diffusion method. A p-type deep base region 216 is formed in 204, wherein the temperature of the quotient diffusion method is between 5 〇〇 and 2 〇〇〇. (Between 3, the dopant may be, for example, boron, and the concentration of the ion implant is between 1 χ 1 〇 15 Up to 7χ1 015/cm3°, the patterned photoresist layer is then removed and another patterned photoresist layer (not shown) is formed, wherein the patterned photoresist layer is used to form a source region. The patterned photoresist layer is a mask, and the P-type body region 204 is ion implanted to form a 1310590 doping region in the P-type body region 204 as a source region 218 of the fabricated transistor. The impurity region is adjacent to the gate oxide layer 210, that is, above the sidewall of the trench structure 2〇8, The source region 218. The source region 218 is implanted at a concentration of 1><1〇15 to 7x1 015/cm2. In addition, the 'source region 218 ion implanted electricity is opposite to the deep base region 216. The contact window is formed by first forming a dielectric layer 220 to cover the upper surface of the germanium-type substrate region 204 and the doped polysilicon layer 212. The dielectric layer 220 can be, for example, a lin; j) or lead-phosphorus glass (BPSG), in which phosphorus-phosphorus glass (ρ%) is deposited by Atmospheric Pressure Chemical Vapor Deposition (APCVD) method, and electro-chemical deposition is performed by electric reinforced ( PIasma_enhance(j
Chemical Vapor Deposition, PECVD)法沉積硼磷 石夕玻璃（BPSG)。接著形成一圖案化光阻層（圖中未 展示出）於介電層220上，並以此圖案化光阻層為 罩幕進行介電層220之钱刻製程，以曝露出部分之 源極區域218及全部深基體區216。 接著在第六圖中，於介電層220及暴露出之源 極區域218和深基體區216上形成金屬層222。 具體而言，當進行本發明的高功率半導體元件 操作時’首先施加電場於溝渠式之閘極結構212 上，會在P型基體區204上形成反轉層，此時載子 即可由源極區域218經過反轉層移動至汲極區 1310590 2〇〇,由於閘極結構212係穿入半導體底材2〇〇内， 因此可降低電子流通於源極與汲極間之距離進而 降低功率7L件之電阻’增加元件的操作效率舆切換 速度。 t發明已揭示較佳實施例如上，僅用於幫助瞭 發明之實施，非用以限定本發明之精神，而孰 2領域技藝者於領悟本發明之精神後，在不脫離 x月之精神範圍内，當可作些許更動潤飾及等同 ，變化替換’其專利保護範圍當視後附之中請專利 範圍及其等同領域而定。 置式簡單說明 為讓本發明之上述和其他目的、特徵、和優點能 更明顯易懂’下文特舉一較佳實施例’並配合所附圖 式，作詳細說明如下： 第一圖繪示傳統高功率半導體元件之刮面示意 圖； 第二圖為依據本發明的較佳實施例的方法中， 於N型基板上形成一 p型磊晶層，接著以光阻圖案 層定義出閘極區域之晶圓剖面圖； 第二圖為依據本發明的較佳實施例的方法中， 蝕刻出溝渠式閘極結構之晶圓剖面圖； 第四圖為依據本發明的較佳實施例的方法 13 1310590 中，於溝渠式閘極結構中填入接雜多晶石夕 曰 圓剖面圖； 曰阳 第五圖為為依據本發明的較佳實施例的方法 中，進行接觸窗製作的晶圓剖面圖；以及 ' 第六圖為依據本發明的較佳實施例的方法所完 成功率金氧半場效電晶體的晶圓剖面圖。 疋 圈號對照說明： · 100重摻雜N型半導體基材 102與104金屬接觸 108輕摻雜p井區 11 0複晶矽閘極 11 2 N型矽磊晶層 114重摻雜n井區 200 N +型或是p+型的半導體底 2〇4 P型基體區 206光阻圖案層 · 208溝渠結構 21 〇薄閘極氧化層 212摻雜多晶石夕層 216深基體區 21 8源極區域 220介電層 222金屬層 14Chemical Vapor Deposition, PECVD) deposits borophosphite (BPSG). Then, a patterned photoresist layer (not shown) is formed on the dielectric layer 220, and the photoresist layer is patterned as a mask to perform a dielectric layer 220 process to expose a part of the source. Region 218 and all deep base regions 216. Next, in the sixth figure, a metal layer 222 is formed over the dielectric layer 220 and the exposed source region 218 and deep substrate region 216. Specifically, when the high power semiconductor device of the present invention is operated, 'first applying an electric field to the trench gate structure 212, an inversion layer is formed on the P type substrate region 204, and the carrier can be sourced at this time. The region 218 is moved to the drain region 1310590 2〇〇 through the inversion layer, and since the gate structure 212 penetrates into the semiconductor substrate 2, the distance between the source and the drain can be reduced, thereby reducing the power 7L. The resistance of the piece 'increased the operating efficiency of the component 舆 switching speed. The invention has been described with respect to the preferred embodiments, and is only used to assist the implementation of the invention, and is not intended to limit the spirit of the invention, and the skilled artisan will not depart from the spirit of the invention. Within the scope of the patent, the scope of the patent and its equivalents may vary depending on the scope of the patent protection. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; A schematic diagram of a scratched surface of a high power semiconductor device; a second embodiment of the method according to the preferred embodiment of the present invention, a p-type epitaxial layer is formed on an N-type substrate, and then a gate region is defined by a photoresist pattern layer. Wafer sectional view; second embodiment is a cross-sectional view of a wafer in which a trench gate structure is etched in accordance with a preferred embodiment of the present invention; and a fourth embodiment is a method 13 1310590 in accordance with a preferred embodiment of the present invention. In the trench gate structure, the doped polysilicon is filled with a circular cross-sectional view; the fifth view of the solar cell is a cross-sectional view of the wafer fabricated by the contact window in the method according to the preferred embodiment of the present invention. And the sixth figure is a wafer cross-sectional view of a power MOS half field effect transistor completed in accordance with the method of the preferred embodiment of the present invention.疋 circle number comparison description: · 100 heavily doped N-type semiconductor substrate 102 and 104 metal contact 108 lightly doped p well region 11 0 polycrystalline germanium gate 11 2 N-type germanium epitaxial layer 114 heavily doped n well region 200 N + type or p + type semiconductor bottom 2 〇 4 P type base region 206 photoresist pattern layer · 208 trench structure 21 〇 thin gate oxide layer 212 doped polycrystalline layer 216 deep base region 21 8 source Region 220 dielectric layer 222 metal layer 14