TWI631627B - Method and structure to make fins with different fin heights and no topography - Google Patents

Method and structure to make fins with different fin heights and no topography Download PDF

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TWI631627B
TWI631627B TW105113709A TW105113709A TWI631627B TW I631627 B TWI631627 B TW I631627B TW 105113709 A TW105113709 A TW 105113709A TW 105113709 A TW105113709 A TW 105113709A TW I631627 B TWI631627 B TW I631627B
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boron
region
buried
germanium
fin
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TW201705305A (en
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慷果 程
喬爾Ｐ 德索隆
艾利 哈奇佛羅斯
艾力克安德魯 瑞尼克
多明尼克Ｊ 史奇佩斯
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美商格羅方德半導體公司
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Abstract

本發明提供一種半導體結構，其含有具有不同高度的矽鰭片，同時保持針對處理合理性的合理的鰭片高度對寬度比例。該半導體結構包含第一高度且位於第一埋入氧化結構上的第一矽鰭片。該結構還包含第二高度且位於第二埋入氧化結構上的第二矽鰭片，該第二埋入氧化結構與該第一埋入氧化結構隔開。該第二矽鰭片的第二高度大於該第一矽鰭片的第一高度，但該第一矽鰭片的最頂表面與該第二矽鰭片的最頂表面共平面。 The present invention provides a semiconductor structure that includes fin fins having different heights while maintaining a reasonable fin height to width ratio for processing rationality. The semiconductor structure includes a first fin fin of a first height and located on the first buried oxide structure. The structure further includes a second fin fin of a second height and located on the second buried oxide structure, the second buried oxide structure being spaced apart from the first buried oxide structure. The second height of the second fin is greater than the first height of the first fin, but the topmost surface of the first fin is coplanar with the topmost surface of the second fin.

Description

製造具有不同鰭片高度且無形貌之鰭片的方法與結構 Method and structure for fabricating fins having different fin heights and no features

本發明相關於半導體結構及其形成方法。更特定地，本發明相關於含有位於埋入氧化結構上且具有不同高度的半導體結構矽鰭片，又具有與各其它者共平面的最頂表面。本發明也提供形成這樣半導體結構的方法。 The invention relates to semiconductor structures and methods of forming the same. More particularly, the present invention relates to a semiconductor structure fin fin having a different height on a buried oxide structure and having a top surface coplanar with each other. The invention also provides a method of forming such a semiconductor structure.

持續30年以上，繼續縮小的金屬氧化半導體場效電晶體(MOSFET)已驅動全球半導體產業。雖已斷定十年間有各種繼續微縮的瓶頸，但仍已維持在許多挑戰的精神中的摩爾定律的創新歷史。然而，今日存在金屬氧化半導體電晶體正開始達到其傳統微縮極限的成長跡象。既然改進MOSFET及因此通過繼續微縮的互補金屬氧化半導體(CMOS)的表現變得越發困難，用於改進增進微縮的表現的進一步方法變得關鍵。 Metal oxide semiconductor field effect transistors (MOSFETs), which continue to shrink for more than 30 years, have driven the global semiconductor industry. Although it has been determined that there are various bottlenecks that continue to shrink in the decade, it has maintained the history of innovation in Moore's Law in the spirit of many challenges. However, today there are signs that metal oxide semiconductor transistors are beginning to reach their traditional microscopic limits. Since the improvement of MOSFETs and thus the performance of complementary metal oxide semiconductors (CMOS) by continuing to shrink becomes more and more difficult, further methods for improving the performance of the miniaturization become critical.

非平面半導體裝置的使用，如舉例來說為矽鰭片場效電晶體(FinFET)是互補金屬氧化半導體(CMOS)裝置的演化的下一階段。矽鰭片場效電晶體(FET)能以相比 現有平面FET更加小尺寸而達到較高驅動電流。 The use of non-planar semiconductor devices, such as, for example, 矽 fin field effect transistors (FinFETs), is the next stage in the evolution of complementary metal oxide semiconductor (CMOS) devices.矽Fin field effect transistor (FET) can be compared Existing planar FETs are smaller in size and achieve higher drive currents.

允許微縮雙閘極FinFET以繼續至下二至三世代。然而，由於三維裝置的本質，裝置寬度(在此情況的鰭片高度)不能如所想要的改變。舉例來說且在SRAM裝置中，針對上拉及下拉FET裝置的裝置寬度比例是重要參數。在傳統(例如，平面)電路中此比例能由設計者隨機選擇以甚至在單元尺寸局限中有助於電路。然而，用於FinFET的裝置寬度是通過鰭片(n個鰭片)的數量乘以(X)鰭片高度(h Fin)而決定且由於單元尺寸(佔用空間)的局限，故設計者不能使用他們希望的許多鰭片，因此FinFET裝置的寬度比例為FinFET電路中的限制。 The miniature double gate FinFET is allowed to continue to the next two to three generations. However, due to the nature of the three-dimensional device, the device width (the fin height in this case) cannot be changed as desired. For example and in SRAM devices, the device width ratio for pull-up and pull-down FET devices is an important parameter. In conventional (eg, planar) circuits this ratio can be randomly selected by the designer to contribute to the circuit even in cell size limitations. However, the width of the device used for the FinFET is determined by multiplying the number of fins (n fins) by the (X) fin height (h Fin) and due to the limitation of the cell size (occupied space), the designer cannot use it. Many fins they want, so the width ratio of the FinFET device is a limitation in the FinFET circuit.

以上觀之，須要一種提供含具有不同高度的矽鰭片的半導體結構，同時保持針對處理合理性的合理的鰭片高度對寬度比例。 In view of the above, there is a need for a semiconductor structure that provides fin fins having different heights while maintaining a reasonable fin height to width ratio for processing rationality.

在一個本發明的態樣中，提供一種形成半導體結構的方法。依據本發明的具體實施例，該方法包括：提供塊體半導體基板，其從底至頂為具有p型導電性和第一摻質濃度的矽基層、以及具有小於該第一摻質濃度的第二摻質濃度的硼摻雜矽層。其次，在該硼摻雜矽層內形成犧牲溝槽隔離結構以定義第一硼摻雜矽部及第二硼摻雜矽部。在該第一硼摻雜部中及位於該第一硼摻雜矽部的留存的最頂部下方形成第一深度的第一多孔矽區域，且在該第二硼摻雜部中及位於該第二硼摻雜矽部的留存的最頂部下 方形成第二深度的第二多孔矽區域，其中，該第二深度大於該第一深度。轉化該第一多孔矽區域成該第一深度的第一埋入氧化結構且轉化該第二多孔矽區域成該第二深度的第二埋入氧化結構。接著，圖案化該第一硼摻雜矽部的該留存的最頂部以在該第一埋入氧化結構上設置第一高度的第一矽鰭片，且圖案化該第二硼摻雜矽部的該留存的最頂部以在該第二埋入氧化結構上設置第二高度的第二矽鰭片，其中，該第二高度大於該第一高度，但各第一矽鰭片及各第二矽鰭片的最頂表面是彼此共平面。 In one aspect of the invention, a method of forming a semiconductor structure is provided. According to a specific embodiment of the present invention, the method includes: providing a bulk semiconductor substrate having a p-type base layer having a p-type conductivity and a first dopant concentration from bottom to top, and having a first concentration smaller than the first dopant concentration A boron-doped ruthenium layer having a second dopant concentration. Next, a sacrificial trench isolation structure is formed in the boron doped germanium layer to define a first boron doped germanium and a second boron doped germanium. Forming a first porous tantalum region of a first depth in the first boron doping portion and below the remaining topmost portion of the first boron doped germanium portion, and in the second boron doping portion and located in the first boron doping portion The bottom of the second boron-doped crest The square forms a second porous tantalum region of a second depth, wherein the second depth is greater than the first depth. Transforming the first porous tantalum region into the first buried oxide structure of the first depth and converting the second porous tantalum region into the second buried oxide structure of the second depth. Next, patterning the remaining topmost portion of the first boron doped germanium to provide a first germanium fin of a first height on the first buried oxide structure, and patterning the second boron doped germanium The topmost portion of the remaining portion is to provide a second height fin second fin on the second buried oxide structure, wherein the second height is greater than the first height, but each first fin and each second The topmost surfaces of the 矽 fins are coplanar with each other.

在本發明的另一態樣中，提供含具有不同高度的矽鰭片的一種半導體結構，同時保持針對處理合理性的合理的鰭片高度對寬度比例。在一個本發明的具體實施例中，該半導體結構包含第一高度且位於第一埋入氧化結構上的第一矽鰭片。該結構還包含具有第二高度且位於第二埋入氧化結構上的第二矽鰭片，該第二埋入氧化結構與該第一埋入氧化結構隔開。依據本發明，該第二矽鰭片的第二高度大於該第一矽鰭片的第一高度，但該第一矽鰭片的最頂表面與該第二矽鰭片的最頂表面共平面。該結構還包含直接接觸該第一埋入氧化結構的最底表面及該第二埋入氧化表面的最底表面鄰近的硼摻雜矽部。該結構甚至還包含具有直接接觸該鄰近的硼摻雜矽層部的最底表面的最頂表面的矽基層，其中，該矽基層具有p型導電性及大於存在於該硼摻雜矽部中的硼的濃度的摻質濃度。 In another aspect of the invention, a semiconductor structure comprising yttrium fins having different heights is provided while maintaining a reasonable fin height to width ratio for processing plausibility. In a particular embodiment of the invention, the semiconductor structure includes a first fin fin of a first height and located on the first buried oxide structure. The structure also includes a second skiliary fin having a second height and located on the second buried oxidized structure, the second buried oxidized structure being spaced apart from the first buried oxidized structure. According to the invention, the second height of the second samarium fin is greater than the first height of the first samarium fin, but the topmost surface of the first samarium fin is coplanar with the topmost surface of the second samarium fin . The structure further includes a boron-doped germanium adjacent to the bottommost surface of the first buried oxide structure and the bottommost surface of the second buried oxide surface. The structure even further includes a germanium-based layer having a topmost surface directly contacting the bottommost surface of the adjacent boron-doped germanium layer portion, wherein the germanium-based layer has p-type conductivity and is greater than that present in the boron-doped germanium portion The concentration of boron in the concentration of boron.

10‧‧‧塊體半導體基板 10‧‧‧ bulk semiconductor substrate

12‧‧‧矽基層 12‧‧‧矽 grassroots

14‧‧‧硼摻雜矽層 14‧‧‧Boron-doped layer

14P‧‧‧硼摻雜矽部 14P‧‧‧Boron-doped crotch

16‧‧‧犧牲溝槽隔離結構 16‧‧‧ Sacrificial trench isolation structure

18‧‧‧阻擋遮罩 18‧‧‧Block mask

20A‧‧‧第一埋入硼摻雜區域、第一硼摻雜區域、埋入硼摻雜區域 20A‧‧‧First buried boron doped region, first boron doped region, buried boron doped region

20A’‧‧‧組件、埋入硼摻雜區域、硼摻雜區域 20A'‧‧‧ components, buried boron doped regions, boron doped regions

20B‧‧‧第二埋入硼摻雜區域、第二埋入摻雜區域、第二硼摻雜區域、埋入硼摻雜區域 20B‧‧‧Second buried boron doped region, second buried doped region, second boron doped region, buried boron doped region

22A‧‧‧第一硼摻雜矽部、硼摻雜矽部 22A‧‧‧First boron doped crotch, boron doped crotch

22B‧‧‧第二硼摻雜矽部、硼摻雜矽部 22B‧‧‧Second boron doped crotch, boron doped crotch

24‧‧‧阻擋遮罩 24‧‧‧Block mask

26A‧‧‧第一多孔矽區域、多孔矽區域 26A‧‧‧First porous germanium region, porous germanium region

26B‧‧‧第二多孔矽區域、多孔矽區域 26B‧‧‧Second porous 矽 area, porous 矽 area

28‧‧‧溝槽 28‧‧‧ trench

30A‧‧‧第一埋入氧化結構 30A‧‧‧First buried oxide structure

30B‧‧‧第二埋入氧化結構 30B‧‧‧Second buried oxide structure

32‧‧‧隔離結構 32‧‧‧Isolation structure

34A‧‧‧第一矽鰭片、矽鰭片 34A‧‧‧First fins, fins

34B‧‧‧第二矽鰭片、矽鰭片 34B‧‧‧Second fins, fins

40A‧‧‧第一功能閘極結構、功能閘極結構 40A‧‧‧First function gate structure, functional gate structure

40B‧‧‧第二功能閘極結構、功能閘極結構 40B‧‧‧Second-function gate structure and functional gate structure

42A‧‧‧閘極介電部 42A‧‧‧Terminal Dielectric Department

42B‧‧‧閘極介電部 42B‧‧‧Gate Electrical Department

44A‧‧‧閘極導體部 44A‧‧‧ Gate Conductor

44B‧‧‧閘極導體部 44B‧‧‧ Gate Conductor

100A‧‧‧第一裝置區域、裝置區域 100A‧‧‧First device area, device area

100B‧‧‧第二裝置區域、裝置區域 100B‧‧‧Second device area, device area

h1‧‧‧第一高度 H1‧‧‧first height

h2‧‧‧第二高度 H2‧‧‧second height

hA‧‧‧厚度 hA‧‧‧thickness

hB‧‧‧厚度 hB‧‧‧thickness

第1圖為依據本發明的具體實施例的塊體半導體基板的示例半導體結構的剖示圖，該塊體半導體基板包含從底至頂為具有p型導電性及第一摻質濃度的矽基層、以及具有依據本發明的具體實施例的小於第一摻質濃度的第二摻質濃度的硼摻雜矽層。 1 is a cross-sectional view showing an exemplary semiconductor structure of a bulk semiconductor substrate including a bismuth layer having a p-type conductivity and a first dopant concentration from the bottom to the top, in accordance with an embodiment of the present invention. And a boron-doped germanium layer having a second dopant concentration that is less than the first dopant concentration in accordance with a particular embodiment of the present invention.

第2圖為第1圖的示例半導體結構在該硼摻雜矽層內形成犧牲溝槽隔離結構以定義含有第一硼摻雜矽部的第一裝置區域及含有第二硼摻雜矽部的第二裝置區域後的剖示圖。 2 is an exemplary semiconductor structure of FIG. 1 forming a sacrificial trench isolation structure in the boron doped germanium layer to define a first device region including a first boron doped germanium portion and a second boron doped germanium portion A cross-sectional view after the second device area.

第3圖為第2圖的示例半導體結構在設置上覆於第二裝置區域的阻擋遮罩後、並同時留下露出的第一裝置區域後的剖示圖。 Figure 3 is a cross-sectional view of the exemplary semiconductor structure of Figure 2 after it has been placed over the barrier mask of the second device region while leaving the exposed first device region.

第4圖為第3圖的示例半導體結構在形成第一深度的第一埋入硼摻雜區域後的剖示圖，其中，該第一埋入硼摻雜區域具有大於第一硼摻雜矽部中的第二摻質濃度的第三摻質濃度。 4 is a cross-sectional view of the example semiconductor structure of FIG. 3 after forming a first buried boron doped region of a first depth, wherein the first buried boron doped region has a larger than the first boron doped germanium. a third dopant concentration of the second dopant concentration in the portion.

第5圖為第4圖的示例半導體結構在移除上覆於第二裝置區域的阻擋遮罩且形成上覆於第一裝置區域的另一阻擋遮罩後的剖示圖。 Figure 5 is a cross-sectional view of the example semiconductor structure of Figure 4 after removing the barrier mask overlying the second device region and forming another barrier mask overlying the first device region.

第6圖為第5圖的示例半導體結構在形成第二深度的第二埋入硼摻雜區域於該第二硼摻雜矽部中後的剖示圖，其中，該第二埋入硼摻雜區域具有第三摻質濃度，並且該第二深度大於第一深度。 6 is a cross-sectional view of the example semiconductor structure of FIG. 5 after forming a second buried boron doped region of a second depth in the second boron doped germanium, wherein the second buried boron doped The impurity region has a third dopant concentration and the second depth is greater than the first depth.

第7圖為第6圖的示例半導體結構在從上覆 於第一裝置區域移除另一阻擋遮罩後的剖示圖。 Figure 7 is an example semiconductor structure of Figure 6 overlying A cross-sectional view of the first blocking device after removing another blocking mask.

第8圖為第7圖的示例半導體結構在進行陽極處理以將第一埋入硼摻雜區域轉化成第一深度的第一多孔矽區域且將第二埋入硼摻雜區域轉化成第二深度的第二多孔矽區域並同時移除犧牲溝槽隔離結構後的剖示圖。 8 is an example semiconductor structure of FIG. 7 undergoing anodization to convert a first buried boron doped region into a first porous germanium region of a first depth and a second buried boron doped region into a first A cross-sectional view of the second porous tantalum region of the second depth and simultaneously removing the sacrificial trench isolation structure.

第9圖為第8圖的示例半導體結構在進行氧化退火以將第一多孔矽區域轉化為第一深度的第一埋入氧化結構及將第二多孔矽區域轉化為第二深度的第二埋入氧化結構後的剖示圖。 Figure 9 is a diagram showing an exemplary semiconductor structure of Figure 8 in which an oxidation anneal is performed to convert a first porous germanium region to a first buried oxide structure and a second porous germanium region to a second depth. Second, a cross-sectional view after embedding the oxidized structure.

第10圖為第9圖的示例半導體結構在形成於溝槽內的底部的隔離結構後的剖示圖，其中，該溝槽之前包含該犧牲溝槽隔離結構。 Figure 10 is a cross-sectional view of the exemplary semiconductor structure of Figure 9 after the isolation structure formed at the bottom of the trench, wherein the trench previously includes the sacrificial trench isolation structure.

第11圖為第10圖的示例半導體結構的在圖案化第一硼摻雜矽部的留存的最頂部以設置第一高度的第一矽鰭片在第一埋入氧化結構上及圖案化第二硼摻雜矽部的留存的最頂部以設置第二高度的第二矽鰭片在第二埋入氧化結構上後的剖示圖，其中，該第二高度大於該第一高度，但各第一矽鰭片及各第二矽鰭片的最頂表面是彼此共平面。 11 is a first semiconductor fin of the exemplary semiconductor structure of FIG. 10 at a topmost portion of the patterned first boron-doped germanium portion to provide a first height on the first buried oxide structure and patterned. a top view of the remaining top of the diboron-doped crotch portion to provide a second height second second fin fin on the second buried oxide structure, wherein the second height is greater than the first height, but each The topmost surfaces of the first fin and each of the second fins are coplanar with each other.

第12圖為第11圖的示例半導體結構在形成跨各第一矽鰭片的第一功能閘極結構及跨各第二矽鰭片的第二功能閘極結構後的剖示圖。 Figure 12 is a cross-sectional view of the exemplary semiconductor structure of Figure 11 after forming a first functional gate structure across each of the first fins and a second functional gate structure across each of the second fins.

第13圖為第4圖的示例半導體結構依據本發明的另一具體實施例在移除上覆於第二裝置區域的阻擋 遮罩後的剖示圖。 Figure 13 is an illustration of the exemplary semiconductor structure of Figure 4 in accordance with another embodiment of the present invention for removing the barrier overlying the second device region A cross-sectional view after the mask.

第14圖為第13圖的示例半導體結構在該第二硼摻雜矽部中形成第二深度的第二埋入硼摻雜區域及第一硼摻雜矽部的留存的部分後的剖示圖，其中，該第二埋入硼摻雜區域具有第三摻質濃度，該第一硼摻雜矽部的該留存的部分直接位於該第一埋入硼摻雜區域下方，而該第二深度大於該第一深度。 Figure 14 is a cross-sectional view showing the example semiconductor structure of Fig. 13 after the second buried boron doped region of the second depth and the remaining portion of the first boron doped germanium portion are formed in the second boron doped germanium portion. The second buried boron doped region has a third dopant concentration, and the remaining portion of the first boron doped germanium is directly below the first buried boron doped region, and the second The depth is greater than the first depth.

第15圖為第14圖的示例半導體結構在進行陽極處理以將存在於該第一裝置區域中的該第一埋入硼摻雜區域及下方的第二埋入摻質區域轉化成第一深度的第一多孔矽區域及將該第二裝置區域中的該第二埋入硼摻雜區域轉化成第二深度的第二多孔矽區域並同時移除犧牲溝槽隔離結構後的剖示圖。 Figure 15 is an illustration of the semiconductor structure of Figure 14 being anodized to convert the first buried boron doped region present in the first device region and the second buried dopant region below the first depth After the first porous germanium region and the second buried boron doped region in the second device region are converted into the second porous germanium region of the second depth while removing the sacrificial trench isolation structure Figure.

第16圖為第15圖的示例半導體結構的在進行氧化退火以將第一多孔矽區域轉化成第一深度的第一埋入氧化結構且將第二多孔矽區域轉化成第二深度的第二埋入氧化結構後的剖示圖。 Figure 16 is a first buried oxide structure of an exemplary semiconductor structure of Figure 15 undergoing an oxidation anneal to convert a first porous germanium region to a first depth and a second porous germanium region to a second depth A cross-sectional view after the second buried oxide structure.

第17圖為第16圖的示例半導體結構在形成溝槽的底部內的隔離結構後的剖示圖，該溝槽先前包含犧牲溝槽隔離結構。 Figure 17 is a cross-sectional view of the exemplary semiconductor structure of Figure 16 after forming an isolation structure in the bottom of the trench, the trench previously comprising a sacrificial trench isolation structure.

第18圖為第17圖的示例半導體結構在圖案化第一硼摻雜矽部的留存的最頂部以在第一埋入氧化結構上設置第一高度的第一矽鰭片及圖案化第二硼摻雜矽部的留存的最頂部以在第二埋入氧化結構上設置第二高度的第 二矽鰭片後的剖示圖，其中，第二高度大於第一高度，但各第一矽鰭片及各第二矽鰭片的最頂表面是彼此共平面。 Figure 18 is an exemplary semiconductor structure of Figure 17 at a topmost portion of the patterned first boron doped germanium to provide a first fin of the first height and a patterned second on the first buried oxide structure The topmost portion of the boron-doped crotch portion is provided with a second height on the second buried oxide structure A cross-sectional view of the second fin, wherein the second height is greater than the first height, but the topmost surfaces of the first fins and the second fins are coplanar with each other.

第19圖為第18圖的示例半導體結構在形成跨各第一矽鰭片的第一功能閘極結構及跨各第二矽鰭片的第二功能閘極結構後的剖示圖。 Figure 19 is a cross-sectional view of the exemplary semiconductor structure of Figure 18 after forming a first functional gate structure across each first fin and a second functional gate structure across each second fin.

本發明現在將通過參照下文討論及伴隨本發明的附圖而以詳細描述。須注意本發明附圖是僅用於說明目的，例如，附圖未照比例繪製。也須注意類似及對應組件是通過類似標號而提及。 The invention will now be described in detail by reference to the accompanying drawings and the accompanying drawings. The drawings of the present invention are intended to be illustrative only, and the drawings are not drawn to scale. It should also be noted that similar and corresponding components are referred to by similar reference numerals.

在下文描述中，為了提供對於本發明各種具體實施例的理解，闡述數種實際細節，例如特定結構、成份、材料、尺寸、處理步驟及技術。然而，由本技術領域的技術人員將瞭解的是本發明的各種具體實施例可不以特定細節而實行。在其它情況下，背景技術的結構或處理步驟已為了免於混淆本發明而不詳細描述。 In the following description, numerous specific details are set forth, such as specific structures, compositions, materials, dimensions, processing steps and techniques, in order to provide an understanding of various embodiments of the invention. However, it will be understood by those skilled in the art that the various embodiments of the invention may be In other instances, the structures or processing steps of the prior art have been described in detail in order not to obscure the invention.

首先參照第1圖，此處說明包含塊體半導體基板10的示例半導體結構，從底至頂為具有p型導電性及第一摻質濃度的矽基層12，以及具有能依據本發明的具體實施例而施用的小於第一摻質濃度的第二摻質濃度的硼摻雜矽層14。 Referring first to Figure 1, an exemplary semiconductor structure including a bulk semiconductor substrate 10 is illustrated herein, having a p-type conductivity and a first dopant concentration from the bottom to the top, and having a specific implementation in accordance with the present invention. A boron-doped germanium layer 14 of a second dopant concentration that is less than the first dopant concentration is applied, for example.

如上文提及，第1圖的塊體半導體基板10包含具有p型導電性及第一摻質濃度的矽基層12。通過“p型導電性”，其意謂矽基層12含p型摻質。術語“p型摻 質”指出當添加至本質半導體材料時於本質半導體材料中造成自由電子的缺陷的不純物(也就是，摻質)。對於矽、硼、鋁、鎵及/或銦而言其可使用為p型不純物。一般而言，使用於本發明中的硼是作為提供給矽基層12的p型導電性的摻質。p-摻質的第一摻質濃度能從5×1018原子/cm3至1×1020原子/cm3而可於矽基層12中存在。p型摻質能在形成矽基層12的期間導入矽基層12，或替代地p型摻質能通過利用離子植入而導入本質半導體材料。 As described above, the bulk semiconductor substrate 10 of Fig. 1 includes the ruthenium base layer 12 having p-type conductivity and first dopant concentration. By "p-type conductivity", it is meant that the ruthenium base layer 12 contains a p-type dopant. The term "p-type dopant" refers to impurities (i.e., dopants) that cause defects in free electrons in the intrinsic semiconductor material when added to the intrinsic semiconductor material. For bismuth, boron, aluminum, gallium and/or indium, it can be used as a p-type impurity. In general, boron used in the present invention is a dopant which is a p-type conductivity which is supplied to the ruthenium base layer 12. The first dopant concentration of the p-doped material can be from 5 x 10 18 atoms/cm 3 to 1 x 10 20 atoms/cm 3 and can be present in the ruthenium base layer 12. The p-type dopant can be introduced into the ruthenium-based layer 12 during the formation of the ruthenium-based layer 12, or alternatively the p-type dopant can be introduced into the intrinsic semiconductor material by ion implantation.

具有小於第一摻質濃度的第二摻質濃度的硼摻雜矽層14能利用磊晶生長處理而形成在矽基層12的頂上。術語“磊晶生長及/或沉積”及“磊晶形成及/或生長”意指半導體材料的生長是在半導體材料的沉積表面上，其中，生長的半導體材料具有如沉積表面的半導體材料的相同晶體特性。在磊晶沉積處理中，通過來源氣體提供的化學反應物受到控制且設定系統參數以使沉積的原子以充分能量到達半導體材料的沉積表面處以在表面四處遊走且使其自身定向至沉積表面的原子的晶體排列。因此，通過磊晶沉積處理形成的的磊晶半導體材料具有如其形成的沉積表面上的沉積表面的相同晶體特性。舉例來說，沉積在{100}晶體表面上的磊晶半導體材料將得到{100}的排列定向。在本發明中，硼摻雜矽層14具有磊晶關係，也就是，相同晶體排列定向，如矽基層12的排列定向。在本發明中，矽基層12可具有任何晶體學的表面排列定向，就如同，舉例來說，{100}、{110}或{111}。 A boron-doped germanium layer 14 having a second dopant concentration less than the first dopant concentration can be formed on top of the germanium base layer 12 by epitaxial growth processing. The terms "elevation growth and/or deposition" and "epitaxial formation and/or growth" mean that the growth of the semiconductor material is on the deposition surface of the semiconductor material, wherein the grown semiconductor material has the same semiconductor material as the deposition surface. Crystal characteristics. In an epitaxial deposition process, the chemical reactants provided by the source gas are controlled and system parameters are set such that the deposited atoms reach the deposition surface of the semiconductor material with sufficient energy to migrate around the surface and direct themselves to the atoms of the deposition surface. The crystal arrangement. Therefore, the epitaxial semiconductor material formed by the epitaxial deposition process has the same crystal characteristics as the deposition surface on the deposition surface it forms. For example, epitaxial semiconductor material deposited on the {100} crystal surface will result in an orientation orientation of {100}. In the present invention, the boron-doped germanium layer 14 has an epitaxial relationship, that is, the same crystal alignment orientation, such as the alignment orientation of the germanium base layer 12. In the present invention, the ruthenium base layer 12 can have any crystallographic surface alignment orientation as if, for example, {100}, {110} or {111}.

適合用於形成硼摻雜矽層14所使用的各種磊晶生長處理的範例包含，例如，快速熱化學氣相沉積(RTCVD)、低-能量電漿沉積(LEPD)、超-高真空化學氣相沉積(UHVCVD)、大氣壓力化學氣相沉積(APCVD)、分子束磊晶附生(MBE)或金屬-有機化學氣相沉積(MOCVD)。用於磊晶沉積的溫度一般是從250℃至900℃的範圍。雖然較高溫度一般導致較快沉積，較快沉積可導致晶體缺陷及膜崩潰。 Examples of various epitaxial growth processes suitable for use in forming the boron-doped germanium layer 14 include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical gas. Phase deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD). The temperature for epitaxial deposition is generally in the range of from 250 °C to 900 °C. Although higher temperatures generally result in faster deposition, faster deposition can result in crystal defects and film collapse.

可針對硼摻雜矽層14的沉積而使用數種不同來源氣體。在某些具體實施例中，針對硼摻雜矽層14的沉積的來源氣體包含含於氣體來源的矽。能使用類似氫、氮、氦及氬的載體氣體。在一具體實施例中，硼能在磊晶沉積處理的期間導入來源氣體。在另一具體實施例中，硼能通過利用離子植入或氣相摻雜而以充足提供予硼摻雜矽層14的濃度導入本質矽層中。 Several different source gases can be used for the deposition of the boron doped germanium layer 14. In some embodiments, the source gas for the deposition of the boron-doped germanium layer 14 comprises germanium contained in a gas source. A carrier gas similar to hydrogen, nitrogen, helium and argon can be used. In a specific embodiment, boron can be introduced into the source gas during the epitaxial deposition process. In another embodiment, boron can be introduced into the intrinsic germanium layer by a concentration sufficient to provide the boron doped germanium layer 14 by ion implantation or gas phase doping.

可替代地，可能首先形成具有第二摻質濃度的硼摻雜矽材料。硼或另一類似p型摻質的離子植入能接著形成如第1圖顯示的塊體半導體基板10的矽基層12而進行。 Alternatively, it is possible to first form a boron-doped germanium material having a second dopant concentration. Ion implantation of boron or another similar p-type dopant can be performed by subsequently forming the germanium base layer 12 of the bulk semiconductor substrate 10 as shown in Fig. 1.

硼摻雜矽層14的厚度能從100nm至500nm而形成。小於其或大於其前述的厚度範圍的其它厚度也能施用於本發明中。硼摻雜矽層14的第二摻質濃度能在從1×1018原子/cm3至5×1018原子/cm3的範圍中。第二摻質濃度的其它範圍也可施用於本發明中，該其它範圍如同小於存 在矽基層12中的第一摻質濃度的存在於硼摻雜矽層14中的第二摻質濃度。 The thickness of the boron-doped germanium layer 14 can be formed from 100 nm to 500 nm. Other thicknesses less than or greater than their aforementioned thickness ranges can also be applied in the present invention. The second dopant concentration of the boron-doped germanium layer 14 can range from 1 x 10 18 atoms/cm 3 to 5 x 10 18 atoms/cm 3 . Other ranges of the second dopant concentration may also be applied in the present invention as the second dopant concentration present in the boron-doped germanium layer 14 is less than the first dopant concentration present in the germanium base layer 12.

現在參照第2圖，其說明於形成硼摻雜矽層14內的犧牲溝槽隔離結構16以定義含有第一硼摻雜矽部的第一裝置區域100A及含有第二硼摻雜矽部的第二裝置區域100B後的第1圖的示例半導體結構。各硼摻雜矽部具有第二摻質濃度及表示各裝置區域(100A,100B)中的硼摻雜矽層14的不-蝕刻部。各犧牲溝槽隔離結構16能藉由先設置在硼摻雜矽層14內的溝槽而形成，其中該溝槽的溝槽底部在達到矽基層12的最上表面之前停止。溝槽能通過微影及蝕刻而形成。微影包含形成上覆顯示於第1圖中的示例半導體結構的光阻材料，且接著通過利用例如舉例來說為旋轉鍍覆、蒸鍍、化學氣相沉積或電漿加強化學氣相沉積而沉積處理。沉積的光阻材料接著受到照光的圖案化，之後利用阻劑顯影劑顯影暴露的光阻材料以提供圖案化的光阻。光阻材料內的圖案接著利用例如舉例來說為反應離子蝕刻的非等向蝕刻而轉化成下層的硼摻雜矽層14。在該蝕刻之後，圖案化光阻材料能利用例如舉例來說為灰化的阻劑剝除處理而從示例半導體結構剝除。 Referring now to Figure 2, there is illustrated a sacrificial trench isolation structure 16 formed in a boron doped germanium layer 14 to define a first device region 100A comprising a first boron doped germanium and a second boron doped germanium portion. An example semiconductor structure of FIG. 1 after the second device region 100B. Each of the boron-doped germanium portions has a second dopant concentration and a non-etched portion indicating the boron-doped germanium layer 14 in each device region (100A, 100B). Each sacrificial trench isolation structure 16 can be formed by a trench first disposed within the boron doped germanium layer 14, wherein the trench bottom of the trench stops before reaching the uppermost surface of the germanium base layer 12. The trench can be formed by lithography and etching. The lithography comprises forming a photoresist material overlying the exemplary semiconductor structure shown in FIG. 1 and then enhancing the chemical vapor deposition by using, for example, spin plating, evaporation, chemical vapor deposition, or plasma. Deposition treatment. The deposited photoresist material is then patterned by illumination, after which the exposed photoresist material is developed with a resist developer to provide a patterned photoresist. The pattern within the photoresist material is then converted to the underlying boron-doped germanium layer 14 using, for example, anisotropic etching, reactive ion etching. After the etching, the patterned photoresist material can be stripped from the exemplary semiconductor structure using, for example, a ashing resist stripping process.

在硼摻雜矽層14內形成溝槽後，溝槽接著以如舉例來說，二氧化矽或氮化矽的溝槽介電材料充填。溝槽的充填可包含利用如舉例來說，化學氣相沉積或電漿增強氣相沉積的沉積處理的任何背景技術而沉積溝槽介電材料。在某些具體實施例中，可使用如舉例來說，化學機 械拋光及/或研磨的平坦化處理以移除任何形成在溝槽外及硼摻雜矽層14的頂上的溝槽介電材料。 After the trench is formed in the boron doped germanium layer 14, the trench is then filled with a trench dielectric material such as, for example, hafnium oxide or tantalum nitride. The filling of the trenches may comprise depositing a trench dielectric material using any of the background techniques of deposition processing such as, for example, chemical vapor deposition or plasma enhanced vapor deposition. In some embodiments, a chemical machine can be used, for example, The planarization of the mechanical polishing and/or grinding removes any trench dielectric material formed on the top of the trench and on top of the boron doped germanium layer 14.

現在參照第3圖，其說明在設置上覆於第二裝置區域100B的阻擋遮罩18、同時留下露出的第一裝置區域100A後的第2圖的示例半導體結構。阻擋遮罩18在隨後存在於第一裝置區域100A中的第一硼摻雜矽部內的第一埋入摻雜區域的形成期間作用為植入遮罩。 Referring now to FIG. 3, an exemplary semiconductor structure of FIG. 2 after the barrier mask 18 overlying the second device region 100B is disposed while leaving the exposed first device region 100A is illustrated. The blocking mask 18 acts as an implant mask during the formation of the first buried doped region that is subsequently present in the first boron doped germanium in the first device region 100A.

能施用於本發明的阻擋遮罩18包含任何材料能作用為阻擋遮罩以防止摻質離子導入含有第二硼摻雜矽部的第二裝置區域100B。在一個具體實施例中，阻擋遮罩18可僅由光阻材料組成。在另一具體實施例中，阻擋遮罩18可僅由硬遮罩材料組成。硬遮罩材料的範例能使用如包含二氧化矽、氮化矽及/或氮氧化矽的阻擋遮罩18。在本發明的另一具體實施例中，阻擋遮罩18可包括從底至頂的硬遮罩材料及光阻材料的堆疊。 The barrier mask 18 that can be applied to the present invention comprises any material that acts as a barrier mask to prevent dopant ions from being introduced into the second device region 100B containing the second boron doped germanium. In a specific embodiment, the blocking mask 18 can be composed only of a photoresist material. In another embodiment, the barrier mask 18 can be composed only of a hard mask material. An example of a hard mask material can use a barrier mask 18 such as ruthenium dioxide, tantalum nitride, and/or hafnium oxynitride. In another embodiment of the invention, the barrier mask 18 can comprise a stack of hard mask material and photoresist material from bottom to top.

阻擋遮罩18能利用對於本技術領域的技術人員為背景技術的技術而形成。舉例來說，阻擋遮罩18能通過首先沉積至少一個上述材料且接著通過微影圖案化至少一個沉積材料而形成。如舉例來說，也能使用反應離子蝕刻的非等向蝕刻處理以完成可能須要的任何圖案轉移；舉例來說，可使用非等向蝕刻以從微影定義阻層轉移圖案至可定義阻擋遮罩18的下層材料。 The blocking mask 18 can be formed using techniques that are the background art to those skilled in the art. For example, the barrier mask 18 can be formed by first depositing at least one of the above materials and then patterning the at least one deposition material by lithography. An anisotropic etch process using reactive ion etching can also be used, for example, to accomplish any pattern transfer that may be required; for example, anisotropic etch can be used to define a resist layer transfer pattern from lithography to a definable blocking mask. The underlying material of the cover 18.

現在參照第4圖，其說明在形成第一深度的第一埋入硼摻雜區域20A且其具有大於第一硼摻雜矽部中 的第二摻質濃度的第三摻質濃度後的第3圖的示例半導體結構。在本發明中，該深度(例如，第一深度及第二深度)稱呼如從原來第一硼摻雜矽部及第二硼摻雜矽部的最頂表面至形成其中的埋入區域的最頂表面的所測量垂直距離。舉例來說，第一深度為如從第一硼摻雜矽部的最頂表面至第一埋入摻雜區域20A的最頂表面的所測量深度。在本發明的一個具體實施例中，能形成從30nm至200nm的第一深度。也可施用小於或大於上述第一深度範圍的其它第一深度於本發明中。 Referring now to FIG. 4, a first buried boron doped region 20A is formed at a first depth and is greater than the first boron doped germanium portion. An exemplary semiconductor structure of FIG. 3 after the third dopant concentration of the second dopant concentration. In the present invention, the depth (for example, the first depth and the second depth) is referred to as the most from the topmost surface of the original first boron doped germanium portion and the second boron doped germanium portion to the buried region formed therein. The measured vertical distance of the top surface. For example, the first depth is the measured depth as from the topmost surface of the first boron doped germanium to the topmost surface of the first buried doped region 20A. In a specific embodiment of the invention, a first depth from 30 nm to 200 nm can be formed. Other first depths less than or greater than the first range of depths described above may also be applied in the present invention.

第一埋入硼摻雜區域20A是形成在該第一硼摻雜矽部內，這樣該第一硼摻雜矽部的最頂部仍留存在第一埋入硼摻雜區域20A上方。第一硼摻雜矽部留存於第一埋入硼摻雜區域20A上方的最頂部可參照本文是指所留存最頂的第一硼摻雜矽部22A。上述的第一深度為等同於所留存最頂的第一硼摻雜矽部22A的厚度。第一埋入摻雜區域20A不完全延伸通過第一硼摻雜矽部。相對地，硼摻雜矽層14的部份是存在於第一埋入摻雜區域20A下方。第一埋入摻雜區域20A包含矽及硼。 The first buried boron doped region 20A is formed in the first boron doped germanium such that the topmost portion of the first boron doped germanium remains above the first buried boron doped region 20A. The topmost portion of the first boron-doped germanium remaining above the first buried boron-doped region 20A can be referred to herein as the first top boron-doped germanium portion 22A remaining. The first depth described above is equivalent to the thickness of the first boron-doped germanium portion 22A remaining. The first buried doped region 20A does not extend completely through the first boron doped germanium. In contrast, a portion of the boron doped germanium layer 14 is present below the first buried doped region 20A. The first buried doped region 20A contains germanium and boron.

第一埋入硼摻雜區域20A是通過將硼植入進硼摻雜矽層14的第一硼摻雜部而形成。硼的植入能利用本技術領域的背景技術的條件而進行。在一個範例中，下文的硼植入條件能使用於形成第一硼摻雜區域20A：能使用氟化硼(BF2)作為硼摻質來源且依所留存的最頂的第一硼摻雜矽部22A的厚度及想要的第一埋入硼摻雜區域20A 的厚度而施用能量。 The first buried boron doped region 20A is formed by implanting boron into the first boron doped portion of the boron doped germanium layer 14. The implantation of boron can be carried out using the conditions of the background art of the art. In one example, the following boron implantation conditions can be used to form the first boron doped region 20A: boron fluoride (BF 2 ) can be used as a boron dopant source and the topmost first boron doping remaining Energy is applied to the thickness of the crotch portion 22A and the thickness of the desired first buried boron doped region 20A.

如上所述，第一埋入硼摻雜區域20A具有大於第一硼摻雜矽部中的第二摻質濃度的第三摻質濃度。在本發明的一個具體實施例中，存在於第一埋入硼摻雜區域20A中的第三摻質濃度為從1×1020原子/cm3至3×1020原子/cm3。用於第三摻質濃度的其它範圍也可在本發明中施用成相同於存在於大於存在硼摻雜矽層14中的第二摻質濃度的第一埋入硼摻雜區域20A中的第三摻質濃度；第三摻質濃度也小於矽基層12的第一摻質濃度。 As described above, the first buried boron doped region 20A has a third dopant concentration that is greater than the second dopant concentration in the first boron doped germanium portion. In a specific embodiment of the invention, the third dopant concentration present in the first buried boron doped region 20A is from 1 x 10 20 atoms/cm 3 to 3 x 10 20 atoms/cm 3 . Other ranges for the third dopant concentration may also be applied in the present invention to be the same as those present in the first buried boron doped region 20A that is greater than the second dopant concentration present in the boron doped germanium layer 14. The third dopant concentration; the third dopant concentration is also less than the first dopant concentration of the ruthenium base layer 12.

第一埋入硼摻雜區域20A能具有從30nm至200nm的厚度。小於或大於上述厚度範圍的其它厚度也可施用成相同於存在於埋入於第一裝置區域100A中的硼摻雜矽層14內所留存的第一埋入摻雜區域20A。 The first buried boron doped region 20A can have a thickness of from 30 nm to 200 nm. Other thicknesses less than or greater than the above thickness range may also be applied to be the same as the first buried doped region 20A remaining in the boron doped germanium layer 14 embedded in the first device region 100A.

現在參照第5圖，其說明在移除上覆於第二裝置區域100B的阻擋遮罩18且形成上覆於第一裝置區域100A的另一阻擋遮罩24後的第4圖的示例半導體結構。 Referring now to FIG. 5, an exemplary semiconductor structure of FIG. 4 after removing the barrier mask 18 overlying the second device region 100B and forming another barrier mask 24 overlying the first device region 100A is illustrated. .

能利用任何能選擇性移除材料或設置阻擋遮罩18的材料(多種)的傳統處理而移除阻擋遮罩18。在一個具體實施例中，且當該阻擋遮罩由光阻材料的留存部組成時，能利用如舉例來說為灰化的阻劑剝除處理而移除光阻材料的留存部。在另一具體實施例中，且當阻擋遮罩18由硬遮罩材料組成時，可使用如舉例來說為化學機械研磨(CMP)或研磨的平坦化處理。替代地，能使用蝕刻處理以選擇性移除硬遮罩材料。當硬遮罩18包括從底至頂的硬遮 罩材料及光阻材料的堆疊時，能首先通過利用阻劑剝除處理而移除光阻材料，且之後可使用平坦化處理或蝕刻而移除硬遮罩材料。 The barrier mask 18 can be removed using any conventional treatment that selectively removes material or sets the material(s) of the barrier mask 18. In a specific embodiment, and when the barrier mask consists of a retention portion of the photoresist material, the retention portion of the photoresist material can be removed using a resist stripping process such as, for example, ashing. In another embodiment, and when the barrier mask 18 is comprised of a hard mask material, a planarization process such as, for example, chemical mechanical polishing (CMP) or grinding can be used. Alternatively, an etching process can be used to selectively remove the hard mask material. When the hard mask 18 includes a hard cover from the bottom to the top When the cover material and the photoresist material are stacked, the photoresist material can be removed first by using a resist stripping process, and then the hard mask material can be removed using a planarization process or etching.

能通過一個以設置上覆於第二裝置區域100B所形成的阻擋遮罩18的上述技術而設置上覆第一裝置區域100A的另一阻擋遮罩24。另一阻擋遮罩24可包含一個用於設置阻擋遮罩18的上述材料。另一阻擋遮罩24作用為在存在於第二裝置區域100B中的第二硼摻雜矽部內的第二埋入摻雜區域的隨後形成期間的植入遮罩。 Another barrier mask 24 overlying the first device region 100A can be provided by a technique described above that provides a barrier mask 18 formed overlying the second device region 100B. The other barrier mask 24 can include a material as described above for providing the barrier mask 18. Another blocking mask 24 acts as an implant mask during subsequent formation of the second buried doped region within the second boron doped germanium present in the second device region 100B.

現在參照第6圖，其說明在形成第二深度且具有於第二硼摻雜矽部中的第三摻質濃度的第二埋入硼摻雜區域20B後的第5圖的示例半導體結構，其中該第二深度大於第一深度。在本發明的一個具體實施例中，第二深度能從50nm至200nm。小於或大於上述第二深度範圍的其它第二深度也可如同大於第一埋入硼摻雜區域20A的第一深度的第二深度而施用在本發明中。第二埋入硼摻雜區域20B包含矽及硼。 Referring now to Figure 6, an exemplary semiconductor structure of Figure 5 after forming a second buried boron doped region 20B having a second depth and having a third dopant concentration in the second boron doped germanium, Wherein the second depth is greater than the first depth. In a specific embodiment of the invention, the second depth can range from 50 nm to 200 nm. Other second depths less than or greater than the second depth range described above may also be applied in the present invention as a second depth greater than the first depth of the first buried boron doped region 20A. The second buried boron doped region 20B contains germanium and boron.

第二埋入硼摻雜區域20B是形成在例如留存於第二埋入硼摻雜區域20B上方的第二硼摻雜矽部的最頂部的第二硼摻雜矽部內。留存在第二埋入硼摻雜區域20B上方的最頂部的第二硼摻雜矽部的可參照本文中所留存的最頂第二硼摻雜矽部22B。上述第二深度等同於留存的最頂第二硼摻雜矽部22B的厚度。第二埋入摻雜區域20B不完全延伸通過第二硼摻雜矽部。相對地，硼摻雜矽層14 的部份是存在於第二埋入摻雜區域20B的下方。 The second buried boron doped region 20B is formed in, for example, the topmost second boron doped germanium portion remaining in the second boron doped germanium portion above the second buried boron doped region 20B. The topmost second boron doped germanium portion remaining in the second buried boron doped region 20B can be referred to the topmost second boron doped germanium portion 22B retained herein. The second depth described above is equivalent to the thickness of the remaining top second boron doped germanium portion 22B. The second buried doped region 20B does not extend completely through the second boron doped germanium. In contrast, boron doped germanium layer 14 The portion is present below the second buried doped region 20B.

通過植入硼進硼摻雜矽層14的第二硼摻雜部而形成第二埋入硼摻雜區域20B。能利用本技術領域的背景技術的條件而進行植入硼。在一個範例中，下文的硼植入條件能使用於形成第二硼摻雜區域20B：能使用氟化硼(BF2)作為硼摻質來源且依所留存的最頂的第二硼摻雜矽部22B的厚度及想要的第二埋入硼摻雜區域20B的厚度而施用能量。 The second buried boron doped region 20B is formed by implanting a boron-doped boron doped second boron doped portion of the germanium layer 14. Boron can be implanted using the conditions of the background art of the art. In one example, the following boron implantation conditions can be used to form the second boron doped region 20B: boron fluoride (BF 2 ) can be used as a boron dopant source and the topmost second boron doping remaining Energy is applied to the thickness of the crotch portion 22B and the thickness of the desired second buried boron doped region 20B.

如上所述，第二埋入硼摻雜區域20B具有大於第二硼摻雜矽部中的第二摻質濃度的第三摻質濃度。在本發明的一個具體實施例中，存在於第二埋入硼摻雜區域20B的第三摻質濃度為從1×1020原子/cm3至3×1020原子/cm3。用於第三摻質濃度的其它範圍也可在本發明中施用成相同存在於大於存在硼摻雜矽層14中的第二摻質濃度的第二埋入硼摻雜區域20B的第三摻質濃度；第三摻質濃度也小於矽基層12的第一摻質濃度。 As described above, the second buried boron doped region 20B has a third dopant concentration that is greater than the second dopant concentration in the second boron doped germanium portion. In a specific embodiment of the invention, the third dopant concentration present in the second buried boron doped region 20B is from 1 x 10 20 atoms/cm 3 to 3 x 10 20 atoms/cm 3 . Other ranges for the third dopant concentration can also be applied in the present invention to the third doping of the second buried boron doped region 20B that is identical to the second dopant concentration present in the boron doped germanium layer 14. The concentration of the third dopant is also less than the concentration of the first dopant of the ruthenium base layer 12.

第二埋入硼摻雜區域20B能具有從50nm至200nm的厚度。小於或大於上述厚度範圍的其它厚度可施用成相同於存在埋入於第二裝置區域100B中的硼摻雜矽層14內所留存的第二埋入摻雜區域20B。 The second buried boron doped region 20B can have a thickness from 50 nm to 200 nm. Other thicknesses less than or greater than the above thickness range may be applied to be the same as the second buried doped region 20B remaining in the boron doped germanium layer 14 buried in the second device region 100B.

在形成第二埋入硼摻雜區域20B後，留存鄰近的硼摻雜矽層14的硼摻雜矽部14P且存在於各埋入硼摻雜區域(20A,20B)下，並在位於第一裝置區域100A與第二裝置區域100B之間的犧牲溝槽隔離結構16下。鄰近的 硼摻雜矽部14P因此直接接觸第一硼摻雜區域20A的最底表面及第二硼摻雜區域20B的最底表面。 After forming the second buried boron doped region 20B, the boron doped germanium portion 14P of the adjacent boron doped germanium layer 14 is retained and exists under each buried boron doped region (20A, 20B), and is located at the A sacrificial trench isolation structure 16 between a device region 100A and a second device region 100B. nearby The boron-doped germanium portion 14P thus directly contacts the bottommost surface of the first boron-doped region 20A and the bottommost surface of the second boron-doped region 20B.

並且，在形成第一及第二埋入硼摻雜區域(20A,20B)後，留存的最頂第一硼摻雜矽部22A存在於第一硼摻雜區域20A上方，且留存的最頂第二硼摻雜矽部22B存在於第二硼摻雜區域20B上方。在本具體實施例中，存在於第二埋入硼摻雜區域20B上方的留存的最頂第二硼摻雜矽部22B厚於存在於第一埋入硼摻雜區域20A上方的留存的最頂第一硼摻雜矽部22A。 And, after forming the first and second buried boron doped regions (20A, 20B), the remaining top first boron doped germanium portion 22A exists above the first boron doped region 20A, and the topmost remains The second boron doped germanium portion 22B exists above the second boron doped region 20B. In the present embodiment, the remaining topmost second boron doped germanium portion 22B present above the second buried boron doped region 20B is thicker than the remaining remaining in the first buried boron doped region 20A. The top first boron doped germanium portion 22A.

現在參照第7圖，其說明在從上覆於第一裝置區域100A移除另一阻擋遮罩24後的第6圖的示例半導體結構。移除另一阻擋遮罩24能利用上述從第6圖的示例半導體結構而從第二裝置區域100B移除阻擋遮罩18的其中之一的技術。移除另一阻擋遮罩露出了留存的最頂的第一硼摻雜矽部22A。 Referring now to Figure 7, an exemplary semiconductor structure of Figure 6 after removing another barrier mask 24 from overlying the first device region 100A is illustrated. Removing the other blocking mask 24 can utilize the techniques described above for removing one of the blocking masks 18 from the second device region 100B from the example semiconductor structure of FIG. Removing the other barrier mask reveals the remaining topmost boron-doped germanium portion 22A.

雖然本發明描述且說明在形成第二埋入硼摻雜區域20B之前形成第一埋入硼摻雜區域20A，上述處理步驟能從先於第一埋入硼摻雜區域20A形成第二埋入硼摻雜區域20B而改變。 Although the present invention describes and illustrates that the first buried boron doped region 20A is formed prior to forming the second buried boron doped region 20B, the above processing steps can form a second buried from the first buried boron doped region 20A. The boron doped region 20B changes.

現在參照第8圖，其說明進行將第一埋入硼摻雜區域20A轉化成第一深度的第一多孔矽區域26A且將第二埋入硼摻雜區域20B轉化成第二深度的第二多孔矽區域26B的陽極處理且同時移除犧牲溝槽隔離結構16以形成溝槽28後的第7圖的示例半導體結構。本發明通篇所使 用的術語“多孔矽”指出其中有納米多孔的洞的矽已導入其微結構內，呈現對體積比例的大表面，其可為500m2/cm3的等級。 Referring now to FIG. 8, a description is made of performing a first porous germanium region 26A that converts the first buried boron doped region 20A into a first depth and a second buried boron doped region 20B into a second depth. The exemplary semiconductor structure of FIG. 7 after the anode of the second porous germanium region 26B is treated and the sacrificial trench isolation structure 16 is simultaneously removed to form the trench 28. The term "porous tantalum" as used throughout the present invention indicates that a crucible having a nanoporous hole therein has been introduced into its microstructure, exhibiting a large surface to volume ratio, which may be on the order of 500 m 2 /cm 3 .

陽極處理是通過浸泡顯示於第7圖中的結構進含氫氟酸(HF)溶液中並同時施加電偏壓至具有相對電極(一般為負極)且也置於含氫氟酸(HF)溶液中的該結構而進行。在這樣的處理中，矽基層12一般作用為電化學單元的正極，同時施用例如鉑的金屬作為負極。通常而言，含氫氟酸溶液中的陽極處理轉化各硼摻雜區域(20A,20B)為多孔矽區域(26A,26B)。該含氫氟酸溶液也選擇性移除提供犧牲溝槽隔離結構16的材料。這樣形成(多孔性及結構)的多孔矽區域(26A,26B)的形成率及本質是通過多種材料特性而決定，該材料特性為例如摻雜類型及濃度、以及陽極處理本身的反應條件(電流密度、偏壓、照度及含氫氟酸溶液中的添加物)。通常而言，設置於本發明中的各多孔矽區域(26A,26B)具有約0.1%或更高的多孔性。 The anodic treatment is carried out by immersing the structure shown in Fig. 7 into a hydrofluoric acid (HF)-containing solution while applying an electrical bias to the opposite electrode (generally the negative electrode) and also to the hydrofluoric acid (HF)-containing solution. This structure is carried out. In such a treatment, the ruthenium base layer 12 generally functions as a positive electrode of an electrochemical cell while a metal such as platinum is applied as a negative electrode. Generally, anodization in a hydrofluoric acid containing solution converts each boron doped region (20A, 20B) into a porous tantalum region (26A, 26B). The hydrofluoric acid containing solution also selectively removes material that provides the sacrificial trench isolation structure 16. The formation rate and nature of the porous germanium regions (26A, 26B) thus formed (porosity and structure) are determined by various material properties such as doping type and concentration, and reaction conditions of the anode treatment itself (current) Density, bias, illuminance and additives in hydrofluoric acid containing solutions). In general, each of the porous tantalum regions (26A, 26B) provided in the present invention has a porosity of about 0.1% or more.

術語"含氫氟酸溶液"包含濃縮HF(49%)、HF與水的混合、HF與例如甲醇、乙醇、丙醇等的羥基醇、或者HF與至少一種表面活性劑的混合物。表面活性劑的量一般以基於49%HF的從約1至約50%含氫氟酸溶液而存在。 The term "hydrofluoric acid containing solution" comprises concentrated HF (49%), a mixture of HF and water, HF with a hydroxyl alcohol such as methanol, ethanol, propanol or the like, or a mixture of HF and at least one surfactant. The amount of surfactant is typically present as from about 1 to about 50% hydrofluoric acid based solution based on 49% HF.

能使用從0.05微安培/cm2至50微安培/cm2的電流密度操作的穩定電流來源而進行本發明的陽極處理。可選擇使用光源以照明樣品。陽極處理一般以室溫(從 20℃至30℃)進行，或可使用上升的溫度。在一個範例中，上升的溫度可從30℃上升至100℃。 Can be used from a stable current source of 0.05 microamperes / cm 2 to 50 micrometers amperes / cm 2 of current density of the anodizing operation of the present invention. A light source can be optionally used to illuminate the sample. The anodizing treatment is generally carried out at room temperature (from 20 ° C to 30 ° C), or an elevated temperature can be used. In one example, the rising temperature can rise from 30 ° C to 100 ° C.

接著陽極處理，顯示於第8圖中的結構一般以去離子水潤濕且乾燥。陽極化一般以小於10分鐘的時間週期發生，更一般而言以小於1分鐘的時間週期。 Following anodization, the structure shown in Figure 8 is typically wetted with deionized water and dried. Anodization typically occurs in a time period of less than 10 minutes, more generally in a time period of less than 1 minute.

在陽極處理後，鄰近的硼摻雜矽部14P留存且存在於各多孔矽區域(26A,26B)之下，又在位於第一裝置區域100A與第二裝置區域100B之間的溝槽28之下。鄰近的硼摻雜矽部14P因此直接接觸第一多孔矽區域26A的最底表面及第二多孔矽區域26B的最底表面。 After the anode treatment, adjacent boron-doped germanium portions 14P remain and exist under each of the porous tantalum regions (26A, 26B), and again in the trenches 28 between the first device region 100A and the second device region 100B. under. The adjacent boron-doped germanium portion 14P thus directly contacts the bottommost surface of the first porous tantalum region 26A and the bottommost surface of the second porous tantalum region 26B.

在陽極處理後，留存的最頂部第一硼摻雜矽部22A的存在於第一多孔矽區域26A上方，且留存的最頂部第二硼摻雜矽部22B的存在於第二多孔矽區域26B上方。 After the anodization, the remaining topmost first boron-doped germanium portion 22A is present over the first porous tantalum region 26A, and the remaining topmost second boron-doped germanium portion 22B is present in the second porous tantalum Above area 26B.

現在參照第9圖，其說明在進行將第一多孔矽區域26A轉化為第一深度的第一埋入氧化結構30A及將第二多孔矽區域26B轉化為第二深度的第二埋入氧化結構30B的氧化退火後的第8圖的示例半導體結構。於本發明中，多孔矽區域26A,26B作用為氧的海綿，且因此氧化發生在多孔矽區域26A,26B內。 Referring now to Figure 9, there is illustrated a first buried oxide structure 30A that converts the first porous tantalum region 26A to a first depth and a second buried layer that converts the second porous tantalum region 26B to a second depth. An exemplary semiconductor structure of FIG. 8 after oxidative annealing of oxidized structure 30B. In the present invention, the porous tantalum regions 26A, 26B act as sponges of oxygen, and thus oxidation occurs in the porous tantalum regions 26A, 26B.

能施用於本發明中的該氧化退火能以如舉例來說為氧氣、空氣、臭氧、氣相水及/或二氧化氮的氧化氣氛進行。在某些具體實施例中，氧化氣氛能混合如舉例來說為氦、氬及/或氖的惰性氣體。在這樣的具體實施例 中，惰性氣體是從含混合物的氧化氣氛的2%體積百分比至95%體積百分比而組成。氧化退火能以從400℃至1100℃的溫度進行。氧化退火可包含能將第一多孔矽區域26A轉化成第一深度的第一埋入氧化結構30A且將第二多孔矽區域26B轉化成第二深度的第二埋入氧化結構30B的爐式退火、快速熱退火或任何其它退火。 The oxidative annealing which can be applied in the present invention can be carried out in an oxidizing atmosphere such as, for example, oxygen, air, ozone, gas phase water and/or nitrogen dioxide. In some embodiments, the oxidizing atmosphere can be mixed with an inert gas such as, for example, helium, argon, and/or helium. In such a specific embodiment The inert gas is composed of 2% by volume to 95% by volume of the oxidizing atmosphere containing the mixture. The oxidation annealing can be carried out at a temperature of from 400 ° C to 1100 ° C. The oxidation anneal may comprise a furnace capable of converting the first porous tantalum region 26A into a first buried oxide structure 30A of a first depth and a second porous tantalum region 26B into a second buried oxide structure 30B of a second depth. Annealing, rapid thermal annealing or any other annealing.

在本發明中，第一埋入氧化結構30A及第二埋入氧化結構30B包括二氧化矽。在說明具體實施例中，以具有最底表面形成的第一埋入氧化結構30A是存在於第二埋入氧化結構30B的最底表面上方。並且，且在說明具體實施例中，第一埋入氧化結構30A的最頂表面位於第二埋入氧化結構30B的最頂表面的上方。 In the present invention, the first buried oxide structure 30A and the second buried oxide structure 30B include hafnium oxide. In the illustrated embodiment, the first buried oxide structure 30A having the bottommost surface is formed over the bottommost surface of the second buried oxide structure 30B. Also, and in the illustrated embodiment, the topmost surface of the first buried oxide structure 30A is located above the topmost surface of the second buried oxide structure 30B.

在氧化退火後，留存鄰近的硼摻雜矽部14P且其在第一及第二埋入氧化結構30A,30B下方並在位於第一裝置區域100A與第二裝置區域100B之間的溝槽28下方。鄰近的硼摻雜矽部14P因此直接接觸第一埋入氧化結構30A的最底表面及第二埋入氧化表面30B的最底表面。在本發明的本具體實施例中，直接位於第二埋入氧化結構30B下方的鄰近的硼摻雜矽部14P的厚度，即hB，小於直接位於第一埋入氧化結構30A下方的鄰近的硼摻雜矽部14P的厚度，即hA。 After the oxidative anneal, adjacent boron-doped germanium portions 14P are retained and are below the first and second buried oxide structures 30A, 30B and in trenches 28 between the first device region 100A and the second device region 100B. Below. The adjacent boron-doped germanium portion 14P thus directly contacts the bottommost surface of the first buried oxide structure 30A and the bottommost surface of the second buried oxide surface 30B. In this embodiment of the invention, the thickness of the adjacent boron-doped germanium portion 14P directly below the second buried oxide structure 30B, ie, h B , is less than the adjacent directly below the first buried oxide structure 30A. The thickness of the boron-doped crotch portion 14P, that is, h A .

在氧化退火後，留存的最頂部第一硼摻雜矽部22A的是存在於第一埋入氧化結構30A上方，且留存的最頂部第二硼摻雜矽部22B的是存在於第二氧化結構 30B上方。 After the oxidative annealing, the remaining topmost first boron-doped germanium portion 22A is present over the first buried oxide structure 30A, and the remaining topmost second boron-doped germanium portion 22B is present in the second oxide. structure Above 30B.

現在參照第10圖，其說明在形成於溝槽28內的底部的隔離結構32後的第9圖的示例半導體結構，溝槽28之前包含犧牲溝槽隔離結構16。如所顯示，位於第一裝置區域100A與第二裝置區域100B之間的隔離結構32具有直接接觸第一埋入氧化結構30A的側壁表面的側壁表面及直接接觸第二埋入氧化結構30B的側壁表面的另一側壁表面。在某些具體實施例中且如所顯示，各隔離結構32的最頂表面能與第二埋入氧化結構30B的最頂表面共平面。在某些具體實施例中且如進一步顯示，各隔離結構32的最頂表面位於第一埋入氧化結構30A的最底表面上方。 Referring now to FIG. 10, an exemplary semiconductor structure of FIG. 9 after the isolation structure 32 formed at the bottom of the trench 28 is illustrated, the trench 28 including the sacrificial trench isolation structure 16 previously. As shown, the isolation structure 32 between the first device region 100A and the second device region 100B has a sidewall surface directly contacting the sidewall surface of the first buried oxide structure 30A and a sidewall directly contacting the second buried oxide structure 30B. The other side wall surface of the surface. In some embodiments and as shown, the topmost surface of each isolation structure 32 can be coplanar with the topmost surface of the second buried oxide structure 30B. In some embodiments and as further shown, the topmost surface of each isolation structure 32 is above the bottommost surface of the first buried oxide structure 30A.

形成的各隔離結構32包括如舉例來說為氧化物或氮化物的溝槽介電材料。在一個範例中，二氧化矽能使用作為溝槽介電材料。溝槽介電材料能通過包含舉例來說為化學氣相沉積或電漿增強化學氣相沉積的沉積處理而形成。沉積處理可以溝槽介電材料過填充各溝槽。在這樣的具體實施例中，可首先使用如舉例來說為化學機械拋光及/或研磨的平坦化處理以減少沉積的溝槽介電材料的高度至顯示在第9圖的留存的第一及第二硼摻雜矽部(22A,22B)的最頂的高度。在平坦化後，能使用回蝕刻處理以形成隔離結構32。在又另一具體實施例中，沉積處理可以溝槽介電材料而部分填充各溝槽。在某些具體實施例中，可或可不施用凹入蝕刻以設置各隔離結構32。 Each of the isolation structures 32 formed includes a trench dielectric material such as, for example, an oxide or a nitride. In one example, cerium oxide can be used as a trench dielectric material. The trench dielectric material can be formed by a deposition process including, for example, chemical vapor deposition or plasma enhanced chemical vapor deposition. The deposition process can overfill the trenches with a trench dielectric material. In such a specific embodiment, a planarization process such as, for example, chemical mechanical polishing and/or grinding may be used first to reduce the height of the deposited trench dielectric material to the first and remaining retained in FIG. The topmost height of the second boron doped crotch portion (22A, 22B). After planarization, an etch back process can be used to form the isolation structure 32. In yet another embodiment, the deposition process can partially fill the trenches with a trench dielectric material. In some embodiments, a recess etch may or may not be applied to provide each isolation structure 32.

現在參照第11圖，其說明圖案化留存的最 頂第一硼摻雜矽部22A以設置第一高度h1的第一矽鰭片34A在第一埋入氧化結構30A上及留存的最頂第二硼摻雜矽部22B以設置第二高度h2的第二矽鰭片34B在第二埋入氧化結構30B上後的第10圖的示例半導體結構，其中，第二高度大於第一高度，又各第一矽鰭片34A及各第二矽鰭片34B的最頂表面是彼此共平面。雖然描述且說明多個第一矽鰭片34A及多個第二矽鰭片34B，本發明周密考慮能形成單一第一矽鰭片34A及/或單一第二矽鰭片34B的具體實施例。 Referring now to Figure 11, it illustrates the most retained patterning. The top first boron doped germanium portion 22A is disposed on the first buried oxide structure 30A and the remaining top second boron doped germanium portion 22B at a first height h1 to set a second height h2 The second semiconductor fin 34B is in the example semiconductor structure of FIG. 10 after the second buried oxide structure 30B, wherein the second height is greater than the first height, and each of the first fins 34A and each of the second fins The topmost surfaces of the sheets 34B are coplanar with each other. Although a plurality of first fin fins 34A and a plurality of second fin fins 34B are described and illustrated, the present invention contemplates a particular embodiment in which a single first fin fin 34A and/or a single second fin fin 34B can be formed.

各矽鰭片(34A,34B)能通過圖案化對應留存的最頂硼摻雜矽部(22A,22B)而形成。在一個具體實施例中，定義各矽鰭片(34A,34B)所使用圖案化處理包括側壁影像轉移(SIT)處理。SIT處理包含形成鄰近的芯軸材料層(未顯示)在留存的最頂硼摻雜矽部(22A,22B)上。鄰近的芯軸材料層(未顯示)能包含能在隨後進行蝕刻處理期間從結構邊擇性移除的任何材料(半導體、介電材或導體)。在一個具體實施例中，鄰近的芯軸材料層(未顯示)可由非晶矽或多晶矽所組成。在另一具體實施例中，鄰近的芯軸材料層(未顯示)可由如舉例來說為鋁(Al)、鎢(W)或銅(Cu)的金屬所組成。鄰近的芯軸材料層(未顯示)能舉例來說通過化學氣相沉積或電漿增強化學氣相沉積而形成。鄰近的芯軸材料層(未顯示)的厚度能從50nm至300nm，雖然也能施用更小或更大的厚度。沉積鄰近的芯軸材料層(未顯示)後，能通過微影及蝕刻圖案化鄰近的芯軸材料層(未顯示)以形成 多個芯軸結構(也未顯示)於結構的最頂表面。 Each of the dam fins (34A, 34B) can be formed by patterning the corresponding topmost boron doped dams (22A, 22B). In one embodiment, the patterning process used to define each of the fins (34A, 34B) includes sidewall image transfer (SIT) processing. The SIT process includes forming an adjacent core material layer (not shown) on the remaining top boron doped germanium (22A, 22B). Adjacent core material layers (not shown) can comprise any material (semiconductor, dielectric or conductor) that can be selectively removed from the structure during subsequent etching processes. In a specific embodiment, an adjacent layer of mandrel material (not shown) may be comprised of amorphous germanium or polycrystalline germanium. In another embodiment, an adjacent layer of mandrel material (not shown) may be comprised of a metal such as, for example, aluminum (Al), tungsten (W), or copper (Cu). Adjacent core material layers (not shown) can be formed, for example, by chemical vapor deposition or plasma enhanced chemical vapor deposition. The thickness of the adjacent core material layer (not shown) can range from 50 nm to 300 nm, although smaller or larger thicknesses can also be applied. After depositing an adjacent layer of mandrel material (not shown), adjacent layers of mandrel material (not shown) can be patterned by lithography and etching to form A plurality of mandrel structures (also not shown) are on the topmost surface of the structure.

SIT處理通過於各芯軸結構的側壁上形成介電間隔件而繼續。介電間隔件能通過沉積介電間隔件材料且接著蝕刻沉積的介電間隔材料而形成。介電間隔件材料可包括如舉例來說為二氧化矽、氮化矽或介電金屬氧化物的任何介電間隔件材料。能在設置介電間隔件材料時使用的沉積處理的範例包含，舉例來說，化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)或原子層沉積(ALD)。在設置介電間隔件時使用的蝕刻的範例包含任何蝕刻處理，如舉例來說，反應離子蝕刻。既然介電間隔件是作為蝕刻遮蔽而使用在SIT處理中，各介電間隔件的寬度確定各矽鰭片(34A,34B)的寬度。 The SIT process continues by forming dielectric spacers on the sidewalls of each mandrel structure. The dielectric spacer can be formed by depositing a dielectric spacer material and then etching the deposited dielectric spacer material. The dielectric spacer material can comprise any dielectric spacer material such as, for example, hafnium oxide, tantalum nitride or a dielectric metal oxide. Examples of deposition processes that can be used in setting the dielectric spacer material include, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). An example of an etch used in setting a dielectric spacer includes any etching process, such as, for example, reactive ion etching. Since the dielectric spacers are used as etch masks in the SIT process, the width of each dielectric spacer determines the width of each of the fins (34A, 34B).

形成介電間隔件後，SIT處理通過移除各芯軸結構而繼續。各芯軸結構能移除通過用於移除相比矽的芯軸材料的蝕刻處理。芯軸結構移除後，SIT處理通過由介電間隔件轉移所設置圖案進留存的最頂硼摻雜矽部(22A,22B)而繼續。可通過利用至少一個蝕刻處理而達到圖案轉移。能使用以轉移圖案的蝕刻處理的範例可包含乾蝕刻(例如，反應離子蝕刻、電漿蝕刻、離子束蝕刻或雷射削磨)及/或化學濕蝕刻處理。在一個範例，使用蝕刻處理以轉移圖案可包含一個或更多反應離子蝕刻步驟。當完成圖案轉移，SIT處理包含通過從結構移除介電間隔件。可通過蝕刻或平坦化處理移除各介電間隔件。 After the dielectric spacers are formed, the SIT process continues by removing the individual mandrel structures. Each mandrel structure can be removed by an etching process for removing the mandrel material compared to the crucible. After the mandrel structure is removed, the SIT process continues by transferring the disposed pattern of the topmost boron doped germanium (22A, 22B) by the dielectric spacer. Pattern transfer can be achieved by using at least one etching process. Examples of etching processes that can use transfer patterns can include dry etching (eg, reactive ion etching, plasma etching, ion beam etching, or laser sharpening) and/or chemical wet etching processes. In one example, using an etch process to transfer the pattern can include one or more reactive ion etch steps. When the pattern transfer is completed, the SIT process involves removing the dielectric spacer from the structure. Each dielectric spacer can be removed by etching or planarization.

在另一具體實施例中，使用圖案化處理以 定義各矽鰭片(34A,34B)能包含微影及蝕刻。微影包含在留存的最頂硼摻雜矽部(22A,22B)上形成光阻材料(未顯示)。光阻材料能利用如舉例來說為旋轉鍍覆、蒸鍍或化學氣相沉積的沉積處理而形成。沉積光阻材料後，暴露光阻材料於照射的圖案，且之後曝光的阻劑材料是利用現有阻劑顯影劑顯影以提供圖案化光阻材料。至少一個用於SIT處理的上述蝕刻能在此使用以完成圖案轉移。至少一個圖案轉移蝕刻處理後，能利用現有如舉例來說為灰化的阻劑剝除處理而從結構移除圖案化光阻材料。 In another embodiment, a patterning process is used It is defined that each fin (34A, 34B) can contain lithography and etching. The lithography comprises forming a photoresist material (not shown) on the remaining top boron doped germanium (22A, 22B). The photoresist material can be formed using a deposition process such as, for example, spin plating, evaporation, or chemical vapor deposition. After depositing the photoresist material, the photoresist material is exposed to the illuminated pattern, and the subsequently exposed resist material is developed using an existing resist developer to provide a patterned photoresist material. At least one of the above etchings for SIT processing can be used herein to complete pattern transfer. After at least one pattern transfer etch process, the patterned photoresist material can be removed from the structure using existing resist stripping processes, such as, for example, ashing.

如本文所使用，“鰭片”引用在本情況的矽的鄰近的半導體材料，且包含平行於每個其它者的一對垂直側壁。如本文所使用，若存在從其表面為垂直平面的表面，“垂直”不違背由比表面多於三倍的均方根粗糙度。形成的各第一矽鰭片34A具有能從30nm至200nm的第一高度，儘管，形成的各第二矽鰭片34B具有能從50nm至200nm的第二高度。小於或大於上述範圍的其它第一高度及第二高度也能施用作為各第一矽鰭片34A及各第二矽鰭片34B的高度，只要各第二鰭片34B的高度(即第二高度)大於各第一矽鰭片34A的高度(即第一高度)。 As used herein, "fin" refers to the adjacent semiconductor material of the crucible in this case and includes a pair of vertical sidewalls parallel to each of the others. As used herein, "vertical" does not violate the root mean square roughness of more than three times the specific surface if there is a surface that is perpendicular to its surface. Each of the first fin fins 34A formed has a first height from 30 nm to 200 nm, although each of the formed second fin fins 34B has a second height from 50 nm to 200 nm. Other first and second heights smaller or larger than the above range can also be applied as the height of each of the first fins 34A and each of the second fins 34B as long as the height of each of the second fins 34B (ie, the second height) ) is greater than the height of each of the first fins 34A (ie, the first height).

現在參照第12圖，其說明在形成跨各第一矽鰭片34A的第一功能閘極結構40A及跨各第二矽鰭片34B的第二功能閘極結構40B後的第11圖的示例半導體結構。雖然本發明描述且說明形成單一第一功能閘極結構40A及單一第二功能閘極結構40B，但能形成多個第一及/ 或第二閘極結構。術語“跨”指出各功能閘極結構(40A,40B)是跨越矽鰭片(34A,34B)，以使各功能閘極結構(40A,40B)的第一部分存在於矽鰭片(34A,34B)的一側上且各功能閘極結構(40A,40B)的第二部分存在於矽鰭片(34A,34B)的另一側上。 Referring now to FIG. 12, an example of FIG. 11 after forming a first functional gate structure 40A across each first fin fin 34A and a second functional gate structure 40B across each second fin fin 34B is illustrated. Semiconductor structure. Although the present invention describes and illustrates the formation of a single first functional gate structure 40A and a single second functional gate structure 40B, a plurality of first and/or Or the second gate structure. The term "span" indicates that each functional gate structure (40A, 40B) is across the fin fins (34A, 34B) such that the first portion of each functional gate structure (40A, 40B) is present in the fin fins (34A, 34B). The second portion of each functional gate structure (40A, 40B) on one side is present on the other side of the samarium fins (34A, 34B).

如顯示在第12圖中，第一功能閘極結構40A的一部分位於第一埋入氧化結構30A的最頂表面，且第二功能閘極結構40B的一部分位於第二埋入氧化結構30B的最頂表面。如進一步顯示在第12圖中，第一功能閘極結構40A的最頂表面與第二功能閘極結構40B的最頂表面共平面，且第一及第二功能閘極結構(40A,40B)是彼此隔開。 As shown in Fig. 12, a portion of the first functional gate structure 40A is located at the topmost surface of the first buried oxide structure 30A, and a portion of the second functional gate structure 40B is located at the most of the second buried oxide structure 30B. Top surface. As further shown in FIG. 12, the topmost surface of the first functional gate structure 40A is coplanar with the topmost surface of the second functional gate structure 40B, and the first and second functional gate structures (40A, 40B) They are separated from each other.

“功能閘極結構”意指使用以控制通過電或磁場的半導體裝置的輸出電流(例如，在通道中的載子流)的永久閘極結構。所形成的各功能閘極結構(40A,40B)包含從底至頂為閘極介電部(42A,42B)及閘極導體部(44A,44B)的閘極材料堆疊。在某些具體實施例中，閘極蓋帽部(未顯示)能存在於閘極導體部(44A,44B)的頂上。 "Functional gate structure" means a permanent gate structure that is used to control the output current of a semiconductor device that passes an electrical or magnetic field (eg, a carrier stream in a channel). The resulting functional gate structures (40A, 40B) include a gate material stack that is gate dielectric (42A, 42B) and gate conductor portions (44A, 44B) from bottom to top. In some embodiments, a gate cap portion (not shown) can be present on top of the gate conductor portion (44A, 44B).

閘極介電部(42A,42B)包括閘極介電材料。提供予閘極介電部(42A,42B)的閘極介電材料能為氧化物、氮化物及/或氧氮化物。在一個範例中，提供予閘極介電部(42A,42B)的閘極介電材料能為具有大於二氧化矽的介電常數的高k材料。示例的高k介電材包含但不限於二氧化鉿(HfO2)、二氧化鋯(ZrO2)、三氧化二鑭(La2O3)、三氧化二鋁(Al2O3)、二氧化鈦(TiO2)、三氧化鈦鍶(SrTiO3)、三 氧化鋁鑭(LaAlO3)、三氧化二釓(Y2O3)、氮氧化鉿(HfOxNy)、氮氧化鋯(ZrOxNy)、氮氧化二鑭(La2OxNy)、氮氧化二鋁(Al2OxNy)、氮氧化鈦(TiOxNy)、氮氧化鈦鍶(SrTiOxNy)、氮氧化鋁鑭(LaAlOxNy)、氮氧化釓(Y2OxNy)、氮氧化矽、氮化矽、以上的矽化物及以上的合金。各x的值是從0.5至3而獨立且各y的值是從0至2而獨立。在某些具體實施例中，多層的閘極介電結構包括能形成且使用作為閘極介電部(42A,42B)的不同閘極介電材料，例如，二氧化矽及高k閘極介電材。 The gate dielectric portion (42A, 42B) includes a gate dielectric material. The gate dielectric material provided to the gate dielectric portion (42A, 42B) can be an oxide, a nitride, and/or an oxynitride. In one example, the gate dielectric material provided to the gate dielectric (42A, 42B) can be a high-k material having a dielectric constant greater than that of cerium oxide. Exemplary high-k dielectric materials include, but are not limited to, hafnium oxide (HfO 2 ), zirconium dioxide (ZrO 2 ), hafronium trioxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), titanium dioxide. (TiO 2 ), TiO 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , Zirconium oxynitride (ZrO x ) N y ), lanthanum oxynitride (La 2 O x N y ), aluminum oxynitride (Al 2 O x N y ), titanium oxynitride (TiO x N y ), titanium oxynitride strontium (SrTiO x N y ) Aluminium oxynitride (LaAlO x N y ), yttrium oxynitride (Y 2 O x N y ), yttrium oxynitride, tantalum nitride, the above telluride and alloys of the above. The value of each x is independent from 0.5 to 3 and the value of each y is independent from 0 to 2. In some embodiments, the multi-layered gate dielectric structure includes different gate dielectric materials that can be formed and used as gate dielectrics (42A, 42B), such as germanium dioxide and high-k gate dielectrics. Electrical materials.

使用在設置閘極介電部(42A,42B)的閘極介電材料能通過包含例如為化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)、物理氣相沉積(PVD)、濺鍍或原子層沉積的任何沉積處理而形成。在某些具體實施例中，閘極介電部42A包括如閘極介電部42B的相同閘極介電材料。在其它具體實施例中，閘極介電部42A可包括第一閘極介電材料，同時閘極介電部42B可包括不同於第一閘極介電材料中的組成的第二閘極介電材料。當使用用於閘極介電部的不同閘極介電材料時，能使用阻擋遮罩技術。在本發明的一個具體實施例中，使用在設置閘極介電部(42A,42B)的閘極介電材料能具有從1nm至10nm的厚度範圍。小於或大於上述厚度範圍的其它厚度也能施用於閘極介電材料。 The gate dielectric material used in the provision of the gate dielectric portion (42A, 42B) can be comprised by, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD). Formed by any deposition process of sputtering or atomic layer deposition. In some embodiments, gate dielectric portion 42A includes the same gate dielectric material as gate dielectric portion 42B. In other embodiments, the gate dielectric portion 42A can include a first gate dielectric material while the gate dielectric portion 42B can include a second gate dielectric that is different from the composition of the first gate dielectric material. Electrical material. Blocking masking techniques can be used when using different gate dielectric materials for the gate dielectric. In a specific embodiment of the invention, the gate dielectric material used in the provision of the gate dielectric portion (42A, 42B) can have a thickness ranging from 1 nm to 10 nm. Other thicknesses less than or greater than the above thickness range can also be applied to the gate dielectric material.

閘極導體部(44A,44B)包括閘極導體材料。使用於設置閘極導體部(44A,44B)的能包含任何導電材料 的閘極導體材料，該導電材料包含，舉例來說，摻雜多晶矽、基本金屬(例如，鎢、鈦、鉭、鋁、鎳、釕、鈀及鉑)、至少二種基本金屬的合金、基本金屬氮化物(例如，鎢氮化物、鋁氮化物及鈦氮化物)、基本金屬矽化物(例如，鎢矽化物、鎳矽化物及鈦矽化物)或其多層的結合。閘極導體部44A可包括與閘極導體部44B相同的閘極導體材料或不同的閘極導體材料。在某些具體實施例中，閘極導體部44A可包括n型場效電晶體(nFET)閘極金屬，同時閘極導體部44B可包括p型場效電晶體(pFET)閘極金屬。在其它具體實施例中，閘極導體部44A可包括pFET閘極金屬，同時閘極導體部44B可包括nFET閘極金屬。 The gate conductor portion (44A, 44B) includes a gate conductor material. Any of the conductive materials used to set the gate conductor portions (44A, 44B) a gate conductor material comprising, for example, a doped polysilicon, a base metal (eg, tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, and platinum), an alloy of at least two base metals, and a base Metal nitrides (eg, tungsten nitride, aluminum nitride, and titanium nitride), base metal halides (eg, tungsten telluride, nickel telluride, and titanium telluride) or combinations thereof. The gate conductor portion 44A may include the same gate conductor material or a different gate conductor material as the gate conductor portion 44B. In some embodiments, the gate conductor portion 44A can include an n-type field effect transistor (nFET) gate metal, while the gate conductor portion 44B can include a p-type field effect transistor (pFET) gate metal. In other embodiments, the gate conductor portion 44A can include a pFET gate metal while the gate conductor portion 44B can include an nFET gate metal.

使用於設置閘極導體部(44A,44B)中的閘極導體材料能利用沉積處理形成，該沉積處理包含，舉例來說，化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)、物理氣相沉積(PVD)、濺鍍、原子層沉積(ALD)或其它類似沉積處理。當金屬矽化物形成時，施用現有矽化處理。當不同閘極導體材料使用於閘極導體部(44A,44B)時，能使用阻擋遮罩技術。在一個具體實施例中，使用在設置閘極導體部(44A,44B)中的閘極導體材料具有從1nm至100nm的厚度。小於或大於上述厚度範圍的其它厚度也能施用於使用在設置閘極導體部(44A,44B)中的閘極導體材料。 The gate conductor material used in the provision of the gate conductor portions (44A, 44B) can be formed by a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD). ), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD) or other similar deposition processes. When the metal halide is formed, the existing deuteration treatment is applied. When different gate conductor materials are used for the gate conductor portions (44A, 44B), a barrier mask technique can be used. In a specific embodiment, the gate conductor material used in the provision of the gate conductor portions (44A, 44B) has a thickness of from 1 nm to 100 nm. Other thicknesses smaller or larger than the above thickness range can also be applied to the gate conductor material used in the provision of the gate conductor portions (44A, 44B).

若存在，閘極蓋帽部包括閘極蓋帽材料。設置各閘極蓋帽部的閘極蓋帽材料可包含用於硬遮罩材料 的上述介電材料的其中之一。在一個具體實施例中，各閘極蓋帽部包括二氧化矽、氮化矽及/或矽氧氮化物。設置各閘極蓋帽部的介電材料能利用如舉例來說為化學氣相沉積或電漿增強化學氣相沉積的現有沉積處理而形成。設置各閘極蓋帽部的介電材料能具有從5nm至20nm的厚度。小於或大於上述厚度範圍的其它厚度也能施用於設置各閘極蓋帽部的介電材料的厚度。 If present, the gate cap portion includes a gate cap material. The gate cap material for each gate cap portion may be included for the hard mask material One of the above dielectric materials. In a specific embodiment, each of the gate cap portions includes hafnium oxide, hafnium nitride, and/or hafnium oxynitride. The dielectric material that sets the gate cap portions can be formed using existing deposition processes such as, for example, chemical vapor deposition or plasma enhanced chemical vapor deposition. The dielectric material of each of the gate cap portions can have a thickness of from 5 nm to 20 nm. Other thicknesses less than or greater than the above thickness range can also be applied to the thickness of the dielectric material in which the respective cap portions are disposed.

各功能閘極結構(40A,40B)能通過設置從底至頂為閘極介電材料、閘極導體材料及若存在的閘極蓋帽材料的功能閘極材料堆疊而形成。功能閘極材料堆疊能接著圖案化。在本發明的一個具體實施例中，圖案化功能閘極材料堆疊可利用微影及蝕刻進行。 Each of the functional gate structures (40A, 40B) can be formed by providing a stack of functional gate materials from bottom to top for the gate dielectric material, the gate conductor material, and the gate cap material present. The functional gate material stack can then be patterned. In one embodiment of the invention, the patterned functional gate material stack can be performed using lithography and etching.

在本發明的其它具體實施例中，第一及第二犧牲閘極結構為非首先設置的第一及第二功能閘極結構(40A,40B)。在另一具體實施例中，能首先設置跨矽鰭片(34A,34B)組中的其中之一者的至少一個功能閘極結構，且能形成跨矽鰭片(34A,34B)組中的其中之另一者的至少一個犧牲閘極結構。 In other embodiments of the invention, the first and second sacrificial gate structures are first and second functional gate structures (40A, 40B) that are not first disposed. In another embodiment, at least one functional gate structure of one of the sets of fins (34A, 34B) can be first disposed and can be formed in a group of fins (34A, 34B) At least one of the sacrificial gate structures of the other of them.

“犧牲閘極結構”意指作用為隨後形成功能閘極結構的占位組件的材料或材料堆疊。在這樣的處理中，功能閘極結形貌成在已形成的源極/汲極結構後。在這樣的具體實施例中，功能閘極結構的閘極介電部可為U形。“U形”意指包含底部水平表面及從該底部水平表面延伸向上的側壁表面的材料。當施用時，犧牲閘極結構可 包含犧牲閘極介電部、犧牲閘極材料部及犧牲閘極蓋帽部。在某些具體實施例中，可省略犧牲閘極介電部及/或犧牲閘極蓋帽部。犧牲閘極介電部包含用於上述閘極介電部(42A,42B)的介電材料的其中之一。犧牲閘極材料部包含用於上述閘極導體部(44A,44B)的閘極導體材料的其中之一。犧牲閘極蓋帽部包含用於上述閘極蓋帽部的閘極蓋帽材料的其中之一。犧牲閘極結構能通過沉積各種材料層且接著通過利用舉例為微影及蝕刻來圖案化組合的犧牲材料堆疊而形成。 By "sacrificial gate structure" is meant a material or stack of materials that function as a placeholder component that subsequently forms a functional gate structure. In such a process, the functional gate junction is shaped after the formed source/drain structure. In such a specific embodiment, the gate dielectric of the functional gate structure can be U-shaped. "U-shaped" means a material comprising a bottom horizontal surface and a sidewall surface extending upward from the bottom horizontal surface. The sacrificial gate structure can be applied when applied A sacrificial gate dielectric portion, a sacrificial gate material portion, and a sacrificial gate cap portion are included. In some embodiments, the sacrificial gate dielectric and/or the sacrificial gate cap can be omitted. The sacrificial gate dielectric portion includes one of dielectric materials for the gate dielectric portion (42A, 42B). The sacrificial gate material portion includes one of the gate conductor materials for the gate conductor portions (44A, 44B). The sacrificial gate cap portion includes one of the gate cap materials for the gate cap portion described above. The sacrificial gate structure can be formed by depositing various layers of material and then patterning the combined sacrificial material stack by, for example, lithography and etching.

在形成閘極結構(功能及/或犧牲閘極結構)後，源極/汲極區域(未顯示)能利用磊晶生長處理從未受閘極結構保護的第一及第二鰭片(34A,34B)的暴露部形成；源極/汲極區域將位於由該第12圖進入或出所說明的附圖的平面內。源極/汲極區域包括任何半導體材料，其包含，舉例來說，矽、鍺或矽鍺合金。提供予源極/汲極區域的半導體材料是以本技術領域的技術人員現有的n型摻質或p型摻質摻雜。摻雜可在設置源極/汲極區域的半導體材料的磊晶生長期間或在本質半導體材料通過利用離子植入或氣相摻雜的磊晶生長後而達到。 After forming the gate structure (functional and/or sacrificial gate structure), the source/drain regions (not shown) can utilize the epitaxial growth process to treat the first and second fins (34A) that have never been protected by the gate structure. The exposed portion of 34B) is formed; the source/drain region will be in the plane of the drawing illustrated or entered in FIG. The source/drain regions include any semiconductor material including, for example, tantalum, niobium or tantalum alloys. The semiconductor material provided to the source/drain regions is doped with existing n-type dopants or p-type dopants by those skilled in the art. Doping can be achieved during epitaxial growth of the semiconductor material in which the source/drain regions are disposed or after epitaxial growth of the intrinsic semiconductor material by ion implantation or gas phase doping.

在某些具體實施例中，且在形成源極/汲極區域之前，閘極間隔件(也未顯示)能形成在閘極結構(功能閘極結構及/或犧牲閘極結構)的暴露側壁上。閘極間隔件能通過沉積閘極間隔件材料且接著通過利用間隔件蝕刻來蝕刻沉積的閘極間隔件材而形成，該閘極間隔件材料舉例 來說為介電氧化材。 In some embodiments, and prior to forming the source/drain regions, a gate spacer (also not shown) can be formed on the exposed sidewalls of the gate structure (functional gate structure and/or sacrificial gate structure) on. The gate spacer can be formed by depositing a gate spacer material and then etching the deposited gate spacer by etching with a spacer, the gate spacer material being exemplified It is a dielectric oxide material.

現在參照第13圖，其說明在依據本發明的另一具體實施例移除上覆於第二裝置區域100B的阻擋遮罩18後的第4圖的示例半導體結構。阻擋遮罩18能利用任何以第5圖的從示例半導體結構的頂上移除阻擋遮罩18的上述技術而移除。 Referring now to Figure 13, an exemplary semiconductor structure of Figure 4 after removal of the barrier mask 18 overlying the second device region 100B is illustrated in accordance with another embodiment of the present invention. The blocking mask 18 can be removed using any of the above techniques of removing the barrier mask 18 from the top of the example semiconductor structure of FIG.

現在參照第14圖，其說明在形成第二深度的第二埋入硼摻雜區域20B及在第二硼摻雜矽部具有第三摻質濃度後的第13圖的示例半導體結構，其中，第二深度大於第一深度。既然不存在阻擋遮罩，第二埋入摻雜區域形成在留存的第一硼摻雜矽部的部分內，第一硼摻雜矽部直接位於第一埋入硼摻雜區域20A下。在說明的具體實施例中，組件20A’通過本發明的具體實施例而存在於形成在第一裝置區域100A中的第一硼摻雜區域及第二硼摻雜區域的組合。在此具體實施例中，第二埋入硼摻雜區域20B的最底表面與埋入硼摻雜區域20A’的最底表面共平面。第二埋入硼摻雜區域20B及存在第一裝置區域100A中的埋入硼摻雜區域20A’的下部能如上述以提供第二硼摻雜區域20B予本發明的第6圖所顯示的示例半導體結構的方式而形成。 Referring now to FIG. 14, there is illustrated an exemplary semiconductor structure of FIG. 13 after forming a second buried boron doped region 20B of a second depth and a third dopant concentration at the second boron doped germanium portion, wherein The second depth is greater than the first depth. Since there is no blocking mask, the second buried doped region is formed in the portion of the remaining first boron doped germanium, and the first boron doped germanium is directly under the first buried boron doped region 20A. In the illustrated embodiment, component 20A' is present in a combination of a first boron doped region and a second boron doped region formed in first device region 100A by a particular embodiment of the present invention. In this embodiment, the bottommost surface of the second buried boron doped region 20B is coplanar with the bottommost surface of the buried boron doped region 20A'. The second buried boron doped region 20B and the lower portion of the buried boron doped region 20A' present in the first device region 100A can be as described above to provide the second boron doped region 20B to be shown in FIG. 6 of the present invention. Formed by way of an exemplary semiconductor structure.

現在參照第15圖，其說明在進行陽極處理以將存在於第一裝置區域100A(例如，硼摻雜區域20A’)中的第一埋入硼摻雜區域及下方的第二埋入摻質區域轉化成第一深度的第一多孔矽區域26A及將第二裝置區域100B 中的第二埋入硼摻雜區域20B轉化成第二深度的第二多孔矽區域26B並同時移除犧牲溝槽隔離結構16後的第14圖的示例半導體結構。本發明的本具體實施例的陽極處理包含在先前本發明具體實施例的上述陽極處理。在本發明的本具體實施例中，存在於第一及第二多孔矽區域(26A,26B)下的鄰近的硼摻雜矽部14P的高度為相同。 Referring now to Figure 15, there is illustrated a second buried dopant in the first buried boron doped region and below that is performed in the first device region 100A (e.g., boron doped region 20A'). The region is converted into a first porous tantalum region 26A of a first depth and a second device region 100B The second buried boron doped region 20B is converted into the second porous germanium region 26B of the second depth and simultaneously removes the example semiconductor structure of FIG. 14 after the sacrificial trench isolation structure 16. The anodizing treatment of this embodiment of the invention comprises the above described anode treatment of a particular embodiment of the invention. In this embodiment of the invention, the heights of adjacent boron-doped jaws 14P present under the first and second porous tantalum regions (26A, 26B) are the same.

現在參照第16圖，其說明在進行氧化退火以將第一多孔矽區域26A轉化成第一深度的第一埋入氧化結構30A且將第二多孔矽區域26B轉化成第二深度的第二埋入氧化結構30B後的第15圖的示例半導體結構。本發明的具體實施例的氧化退火包含本發明先前具體實施例的上述氧化退火。在本具體實施例，第一埋入氧化結構30A具有位於第二埋入氧化結構30B的最頂表面上方的最頂表面。並且，在此具體實施例中，第一埋入氧化結構30A的最底表面與第二埋入氧化結構30B的最底表面共平面。進一步且在本發明的具體實施例中，存在於第一及第二埋入氧化結構(30A,30B)下的鄰近的硼摻雜矽部14P的高度相同。 Referring now to Figure 16, there is illustrated a first embodiment in which an oxidation anneal is performed to convert a first porous tantalum region 26A into a first depth of the first buried oxide structure 30A and a second porous tantalum region 26B to a second depth. An exemplary semiconductor structure of Fig. 15 after embedding the oxidized structure 30B. Oxidation annealing of a particular embodiment of the invention comprises the above-described oxidation annealing of a prior embodiment of the invention. In the present embodiment, the first buried oxide structure 30A has a topmost surface above the topmost surface of the second buried oxide structure 30B. Also, in this embodiment, the bottommost surface of the first buried oxide structure 30A is coplanar with the bottommost surface of the second buried oxide structure 30B. Further and in a particular embodiment of the invention, the adjacent boron-doped crucibles 14P present under the first and second buried oxide structures (30A, 30B) are of the same height.

現在參照第17圖，其說明在形成先前包含犧牲溝槽隔離結構16的溝槽的底部內的隔離結構32後的第16圖的示例半導體結構。本發明的本具體實施例的隔離結構32包含與上述先前本發明的本具體實施例的隔離結構32相同的材料。並且，本發明的本具體實施例的隔離結構32能利用在形成顯示在本發明的第10圖的隔離結構32 的上述技術而形成。 Referring now to Figure 17, an exemplary semiconductor structure of Figure 16 after forming the isolation structure 32 in the bottom of the trench previously containing the sacrificial trench isolation structure 16 is illustrated. The isolation structure 32 of the present embodiment of the present invention comprises the same material as the isolation structure 32 of the previous embodiment of the present invention. Moreover, the isolation structure 32 of the present embodiment of the present invention can utilize the isolation structure 32 formed in the tenth diagram of the present invention. The above technology is formed.

現在參照第18圖，其說明在圖案化留存的最頂第一硼摻雜矽部22A以在第一埋入氧化結構30A上設置第一高度的第一矽鰭片34A及圖案化留存的最頂第二硼摻雜矽部22B以在第二埋入氧化結構30B上設置第二高度的第二矽鰭片34B後的第17圖的示例半導體結構，其中，第二高度大於第一高度，又各第一矽鰭片34A及各第二矽鰭片34B的最頂表面是彼此共平面。本發明的本具體實施例的圖案化處理能包含用於設置顯示於本發明的第11圖的示例半導體結構內的第一及第二矽鰭片(34A,34B)的上述圖案化處理的其中之一者。 Referring now to FIG. 18, the first top boron doped germanium portion 22A remaining in the patterning is provided to provide a first first fin fin 34A on the first buried oxide structure 30A and the pattern retention. The top second boron-doped germanium portion 22B is an example semiconductor structure of FIG. 17 after the second germanium fin 34B is disposed on the second buried oxide structure 30B, wherein the second height is greater than the first height, Further, the topmost surfaces of the first fin fins 34A and the second fin fins 34B are coplanar with each other. The patterning process of the present embodiment of the present invention can include the above-described patterning process for setting the first and second skiliaries (34A, 34B) displayed in the exemplary semiconductor structure of Figure 11 of the present invention. One of them.

現在參照第19圖，其說明在形成跨各第一矽鰭片34A的第一功能閘極結構40A及跨各第二矽鰭片34B的第二功能閘極結構40B後的第18圖的示例半導體結構。本發明的具體實施例的第一及第二功能閘極結構(40A,40B)包含與本發明的先前具體實施例的上述第一及第二功能閘極結構(40A,40B)相同的材料。並且，本發明的本具體實施例的第一及第二功能閘極結構(40A,40B)能利用在形成顯示於本發明的第12圖的第一及第二功能閘極結構(40A,40B)的上述技術而形成。在某些具體實施例中且也如上述的至少一個功能閘極結構(40A,40B)能為犧牲閘極結構，其在形成源極/汲極區域後以功能閘極結構替換。 Referring now to Figure 19, an example of Figure 18 after forming a first functional gate structure 40A across each first fin fin 34A and a second functional gate structure 40B across each second fin fin 34B is illustrated. Semiconductor structure. The first and second functional gate structures (40A, 40B) of a particular embodiment of the present invention comprise the same materials as the first and second functional gate structures (40A, 40B) of the previous embodiment of the present invention. Furthermore, the first and second functional gate structures (40A, 40B) of the present embodiment of the present invention can be utilized in forming the first and second functional gate structures (40A, 40B) shown in Fig. 12 of the present invention. The above technique is formed. The at least one functional gate structure (40A, 40B), in some embodiments and also as described above, can be a sacrificial gate structure that is replaced with a functional gate structure after forming the source/drain regions.

僅管本發明具有已對應其較佳具體實施例而特定顯示且描述，本發明將由本技術領域的技術人員理 解為可在不背離本發明的精神及範疇下作出先前及形式或細節的其它改變。因此有意的是本發明不限於所描述及說明但落在所附加申請專利範圍的範疇內的精確形式及細節。 The present invention will be specifically shown and described in connection with the preferred embodiments thereof, and the present invention will be understood by those skilled in the art Other changes in the form and the form or details may be made without departing from the spirit and scope of the invention. It is therefore intended that the invention not be limited to the details and details of the invention

Claims (20)

一種形成半導體結構的方法，該方法包括：提供塊體半導體基板，其從底至頂為具有p型導電性和第一摻質濃度的矽基層、以及具有小於該第一摻質濃度的第二摻質濃度的硼摻雜矽層；在該硼摻雜矽層內形成犧牲溝槽隔離結構以定義第一硼摻雜矽部及第二硼摻雜矽部；在該第一硼摻雜矽部中及位於該第一硼摻雜矽部的留存的最頂部下方形成第一深度的第一多孔矽區域，且在該第二硼摻雜矽部中及位於該第二硼摻雜矽部的留存的最頂部下方形成第二深度的第二多孔矽區域，其中，該第二深度大於該第一深度；轉化該第一多孔矽區域成該第一深度的第一埋入氧化結構且轉化該第二多孔矽區域成該第二深度的第二埋入氧化結構；以及圖案化該第一硼摻雜矽部的該留存的最頂部以在該第一埋入氧化結構上設置第一高度的第一矽鰭片，且圖案化該第二硼摻雜矽部的該留存的最頂部以在該第二埋入氧化結構上設置第二高度的第二矽鰭片，其中，該第二高度大於該第一高度，但各第一矽鰭片及各第二矽鰭片的該最頂表面是彼此共平面。 A method of forming a semiconductor structure, the method comprising: providing a bulk semiconductor substrate from bottom to top of a germanium base layer having p-type conductivity and a first dopant concentration, and a second having a concentration less than the first dopant concentration a dopant-doped boron-doped germanium layer; a sacrificial trench isolation structure is formed in the boron-doped germanium layer to define a first boron-doped germanium portion and a second boron-doped germanium portion; Forming a first porous germanium region of a first depth below the topmost portion of the first boron-doped germanium portion, and in the second boron-doped germanium portion and the second boron-doped germanium portion Forming a second porous second region of the second depth below the topmost portion of the portion, wherein the second depth is greater than the first depth; converting the first porous germanium region to the first buried oxidation of the first depth Structure and converting the second porous germanium region to the second buried oxide structure of the second depth; and patterning the remaining topmost portion of the first boron doped germanium to be on the first buried oxide structure Forming a first height fin of the first fin and patterning the second boron doping The remaining top portion of the portion is provided with a second height fin second fin on the second buried oxide structure, wherein the second height is greater than the first height, but each first fin and each The topmost surfaces of the second fins are coplanar with each other. 如申請專利範圍第1項所述的方法，其中，移除該犧牲溝槽隔離結構以在形成該第一多孔矽區域及該第二多孔矽區域的期間設置溝槽。 The method of claim 1, wherein the sacrificial trench isolation structure is removed to provide a trench during formation of the first porous germanium region and the second porous germanium region. 如申請專利範圍第2項所述的方法，還包括在該溝槽的底部內形成隔離結構。 The method of claim 2, further comprising forming an isolation structure in the bottom of the trench. 如申請專利範圍第1項所述的方法，其中，形成該第一多孔矽區域及該第二多孔矽區域包括：以任何次序在該第一硼摻雜矽部中形成該第一深度且具有大於該第二摻質濃度的第三摻質濃度的第一埋入硼摻雜區域，且在該第二硼摻雜矽部中形成該第二深度且具有該第三摻質濃度的第二埋入硼摻雜區域；以及進行陽極處理以將該第一埋入硼摻雜區域轉化成該第一多孔矽區域且將該第二埋入硼摻雜區域轉化成該第二多孔矽區域。 The method of claim 1, wherein the forming the first porous tantalum region and the second porous tantalum region comprises: forming the first depth in the first boron doped germanium in any order And a first buried boron doped region having a third dopant concentration greater than the second dopant concentration, and forming the second depth in the second boron doped germanium and having the third dopant concentration a second buried boron doped region; and anodizing to convert the first buried boron doped region into the first porous germanium region and converting the second buried boron doped region into the second plurality Hole area. 如申請專利範圍第1項所述的方法，其中，該形成該第一多孔矽區域及該第二多孔矽區域包括：形成上覆於該第二硼摻雜矽部的阻擋遮罩；將硼植入該第一硼摻雜矽部以設置該第一深度及第三摻質濃度的第一埋入硼摻雜區域；從該第二硼摻雜矽部的頂上移除該阻擋遮罩；形成上覆於該第一硼摻雜矽部的另一阻擋遮罩；將硼植入該第二硼摻雜矽部以設置該第二深度及該第三摻質濃度的第二埋入硼摻雜區域；移除該另一阻擋遮罩；以及進行陽極處理以轉化該第一埋入硼摻雜區域成該第一多孔矽區域，且轉化該第二埋入硼摻雜區域成該 第二多孔矽區域。 The method of claim 1, wherein the forming the first porous germanium region and the second porous germanium region comprises: forming a barrier mask overlying the second boron doped germanium; Implanting boron into the first boron doped germanium to set the first buried boron doped region of the first depth and the third dopant concentration; removing the blocking mask from the top of the second boron doped germanium a mask; forming another blocking mask overlying the first boron doped germanium; implanting boron into the second boron doped germanium to set the second depth and the second buried dopant concentration Into the boron doped region; removing the other blocking mask; and performing anodization to convert the first buried boron doped region into the first porous germanium region, and converting the second buried boron doped region Into The second porous tantalum region. 如申請專利範圍第1項所述的方法，其中，形成該第一多孔矽區域及該第二多孔矽區域包括：形成上覆於該第二硼摻雜矽部的阻擋遮罩；將硼植入該第一硼摻雜矽部以設置該第一深度及第三摻質濃度的第一埋入硼摻雜區域；從該第二硼摻雜矽部的頂上移除該阻擋遮罩；將硼植入該第二硼摻雜矽部以設置該第二深度及第三導電性的第二埋入硼摻雜區域，並同時形成直接在該第一埋入硼摻雜區域下方的該第二深度的另一埋入硼摻雜區域；以及進行陽極處理以轉化該第一埋入硼摻雜區域及該另一埋入硼摻雜區域為該第一多孔矽區域且轉化該第二埋入硼摻雜區域為該第二多孔矽區域。 The method of claim 1, wherein the forming the first porous germanium region and the second porous germanium region comprises: forming a barrier mask overlying the second boron doped germanium; Boron implanting the first boron doped germanium to set the first buried boron doped region of the first depth and the third dopant concentration; removing the blocking mask from the top of the second boron doped germanium Implanting boron into the second boron doped germanium to set the second buried boron doped region of the second depth and the third conductivity, and simultaneously forming directly under the first buried boron doped region Another buried boron doped region of the second depth; and performing anodization to convert the first buried boron doped region and the another buried boron doped region into the first porous germanium region and converting the The second buried boron doped region is the second porous germanium region. 如申請專利範圍第1項所述的方法，其中，轉化該第一多孔矽區域為該第一埋入氧化結構且轉化該第二多孔矽區域為該第二埋入氧化結構包括氧化退火。 The method of claim 1, wherein converting the first porous germanium region to the first buried oxide structure and converting the second porous germanium region to the second buried oxide structure comprises oxidation annealing . 如申請專利範圍第1項所述的方法，其中，該第一埋入氧化結構的最底表面位於該第二埋入氧化結構的最底表面的上方或與該第二埋入氧化結構的該最底表面共平面。 The method of claim 1, wherein the bottommost surface of the first buried oxide structure is above the bottommost surface of the second buried oxide structure or the second buried oxide structure The bottom surface is coplanar. 如申請專利範圍第8項所述的方法，其中，該第一埋入氧化結構的最頂表面位於該第二埋入氧化結構的最頂表面的上方。 The method of claim 8, wherein the topmost surface of the first buried oxide structure is above the topmost surface of the second buried oxide structure. 如申請專利範圍第1項所述的方法，還包括形成跨該第一矽鰭片的第一閘極結構及跨該第二矽鰭片的第二閘極結構。 The method of claim 1, further comprising forming a first gate structure spanning the first fin and a second gate structure spanning the second fin. 如申請專利範圍第10項所述的方法，其中，該第一閘極結構及該第二閘極結構都是功能閘極結構。 The method of claim 10, wherein the first gate structure and the second gate structure are both functional gate structures. 如申請專利範圍第10項所述的方法，其中，該第一閘極結構及該第二閘極結構都是犧牲閘極結構，該犧牲閘極結構在形成源極/汲極區域於該第一矽鰭片及該第二矽鰭片的暴露部上後以功能閘極結構替換。 The method of claim 10, wherein the first gate structure and the second gate structure are both sacrificial gate structures, and the sacrificial gate structure is formed in the source/drain region A fin and an exposed portion of the second fin are replaced by a functional gate structure. 如申請專利範圍第1項所述的方法，其中，圖案化該第一硼摻雜矽部的該留存的最頂部及該第二硼摻雜矽部的該留存的最頂部包括側壁影像轉移處理。 The method of claim 1, wherein the remaining topmost portion of the first boron-doped germanium portion and the remaining topmost portion of the second boron-doped germanium portion comprise sidewall image transfer processing . 一種半導體結構，其包括：第一矽鰭片，具有第一高度且位於第一埋入氧化結構上；第二矽鰭片，具有第二高度且位於第二埋入氧化結構上，該第二埋入氧化結構與該第一埋入氧化結構隔開，其中，該第二矽鰭片的第二高度大於該第一矽鰭片的第一高度，但該第一矽鰭片的最頂表面與該第二矽鰭片的最頂表面共平面；鄰近的硼摻雜矽部，其直接接觸該第一埋入氧化結構的最底表面及該第二埋入氧化結構的最底表面；以及矽基層，具有直接接觸該鄰近的硼摻雜矽部的最 底表面的最頂表面，其中，該矽基層具有p型導電性及大於存在於該硼摻雜矽部中的硼的濃度的摻質濃度。 A semiconductor structure comprising: a first fin fin having a first height and located on the first buried oxide structure; and a second fin fin having a second height and located on the second buried oxide structure, the second The buried oxide structure is spaced apart from the first buried oxide structure, wherein the second height of the second fin fin is greater than the first height of the first fin fin, but the top surface of the first fin fin Coplanar with a topmost surface of the second skiliary fin; an adjacent boron-doped germanium directly contacting the bottommost surface of the first buried oxide structure and the bottommost surface of the second buried oxide structure; a ruthenium base layer having the most direct contact with the adjacent boron-doped ruthenium The topmost surface of the bottom surface, wherein the base layer has a p-type conductivity and a dopant concentration greater than a concentration of boron present in the boron-doped crotch portion. 如申請專利範圍第14項所述的半導體結構，還包括隔離結構，其側向位於該第一埋入氧化結構與該第二埋入氧化結構之間且接觸該第一埋入氧化結構與該第二埋入氧化結構的側壁表面。 The semiconductor structure of claim 14, further comprising an isolation structure laterally between the first buried oxide structure and the second buried oxide structure and contacting the first buried oxide structure and the The second buried surface of the sidewall of the oxidized structure. 如申請專利範圍第14項所述的半導體結構，其中，該第一埋入氧化結構的最頂表面位於該第二埋入氧化結構的最頂表面上方。 The semiconductor structure of claim 14, wherein a topmost surface of the first buried oxide structure is above a topmost surface of the second buried oxide structure. 如申請專利範圍第16項所述的半導體結構，其中，該第一埋入氧化結構的最底表面位於該第二埋入氧化結構的最底表面上方。 The semiconductor structure of claim 16, wherein a bottommost surface of the first buried oxide structure is above a bottommost surface of the second buried oxide structure. 如申請專利範圍第16項所述的半導體結構，其中，該第一埋入氧化結構的最底表面與該第二埋入氧化結構的最底表面共平面。 The semiconductor structure of claim 16, wherein a bottommost surface of the first buried oxide structure is coplanar with a bottommost surface of the second buried oxide structure. 如申請專利範圍第14項所述的半導體結構，其中，位於該第一埋入氧化結構下的該硼摻雜矽部的高度大於或相同於位於該第二埋入氧化結構下的該硼摻雜矽部的高度。 The semiconductor structure of claim 14, wherein the boron-doped germanium portion under the first buried oxide structure has a height greater than or equal to the boron-doped layer under the second buried oxide structure. The height of the chowder. 如申請專利範圍第14項所述的半導體結構，還包括跨該第一矽鰭片的第一功能閘極結構及跨該第二矽鰭片的第二功能閘極結構。 The semiconductor structure of claim 14, further comprising a first functional gate structure spanning the first fin and a second functional gate structure spanning the second fin.
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