508676 A7 B7 五、發明說明（ 發明領域: 經濟部智慧財產局員工消費合作社印製 本發明係有關於一種高功率半導體元件的製造方法， 特別是有關於一種具不同厚度閘氧化層之高功率電晶體 元件的製造方法。 發明背景： 雙載子連接電晶體（BJT)為現今最重要的半導體元件 之一’這種元件雖然可作為高功率元件及高速邏輯電路之 用，但是在操作的過程之中，其最大的缺點為會消耗大量 的能量。目前’金氧半場效電晶體（M〇SFET)的發展，已經 逐漸取代了雙載子電晶體之應用。由於其能節省電能的緣 .故，金氧半場效電晶體已成為積體電路中最常被使用的半 導體元件。 在一般技術之中，所稱的功率金氧半場效電晶體 (POWER MOSFET)基本操作和任何的金氧半場效電晶體相 同，但是其電流處理能力可達數安培，且其汲極至源極所 可耐受的阻隔電壓可高達約20 V〜1200V或是更高。功率金 氧半場效電晶體的優點是可以使用小控制電壓於耗費低功 率的狀況下來操作元件。 請參閱第1圖，其顯示一般常見之功率電晶體結構。 其主要結構包含重摻雜N型（或p型）半導體基材1〇〇與 一層N型矽磊晶矽層1 1 0。在N型矽磊晶矽層1 1 〇之上具 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閱 讀 背 面 之 注 意 事 項 Μ 頁i I訂 508676 ^^_I___ 經濟部智慧財產局員工消費合作社印製 A7 B7 發明說明（） 有閘氧化層1 4 〇與複晶石夕閘極1 5 0。在N型磊晶石夕層丨1 ( 之中，具有一輕摻雜P井區1 2 0，作為功率金氧半場效電 晶體的通道區（Body)。而在輕摻雜p井區12〇之中，尚 包含兩個重摻雜N井區1 30,作為功率半導體元件的源極， 中間以一重摻雜P井區1 8 0做為金屬層丨7 〇與輕摻雜p井 區1 2 0之接觸連接點。在複晶石夕閘極1 5 〇的上方具有一層 删填石夕玻璃 160 (Borophosphosilicate Glass，BPSG)，作 為複晶石夕閘極150的絕緣層。此外，在硼磷矽玻璃16〇之 上，具有一金屬層17 0用以接觸重摻雜N井區丨3 〇，作為 源極導線。 依照第1圖的元件設計，整個元件的操作是以重摻雜 N井區130作為源極，而輕摻雜p井區丨2〇是作為通道區。 然後再以重摻雜N型梦基材1〇0作為元件的汲極，電子進 入源極區，並橫向通過閘極下反轉層而到N型摻雜磊晶矽 層11〇,電子將垂直流經N型摻雜磊晶矽層u〇到達汲極。 在功率半導體元件的操作過程之中’電流經由通道區域流 動於源極與没極之間，若有較大的通遒寬度，則玎增加電 流傳導能力與降低夹擊電阻的大小，但卻增加了元件尺 寸。所以，如何在不增加元件尺寸情況下降低電阻的大小， 變成-個重要關鍵。除此之外力率半導體元件的閘氧化 層之厚度-般約為數百至數千埃，由於此閑氧化層非常接 近元件的主動接面（Active Junction)與通道，因此元件之 閑極與沒極間會形成一相當大的没閘電容。此沒閘電容將 限制元件之切換速度（Switching Speed)，而造成切換損 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 508676 A7 B7 五、發明說明（） 失。因此，亦需要一種改良之高功率半導體元件製程方法 以解決元件切換速度不足的問題。 發明目的及概述： 經濟部智慧財產局員工消費合作社印製 鑑於 一係為一 製造方法 本發 不同之摻 低汲極與 本發 不同之摻 之累積電 本發 所述： 於一 矽層，接 磊晶矽層 裸露之蟲 程，其中 層其他部 進行一熱 化石夕層。 上述發明背景中所指出之缺點，本發明的目的之 種具有不同閘氧化層厚度的高功率半導體元件之 〇 明的另一目的係為於高功率半導體元件中，利用 雜濃度以增加沒極與閘極間閘氧化層之厚度，降 閘極間之電容，並增強閘電極充電速度。 明的次一目的係為於高功率半導體元件中，利用 雜濃度以形成不同厚度之閘氧化層，以降低元件 阻與夾擊電阻。 明揭露一種高功率半導體元件，其製造方法如下 半導體基材上形成與其相同電性之一第一型磊晶 著形成一圖案化光阻層於磊晶矽層上，用以裸露 之第一部份。其次，以圖案化光阻層為幕罩，對 晶矽層第一部份進行第一型電性之離子佈植製 磊晶矽層第一部份所摻雜之離子濃度高於磊晶矽 分之離子摻雜濃度。接著於移除圖案化光阻層後 製程，以於磊晶矽層上同步形成具不同厚度之氧 更明確而言，磊晶矽層第一部份上方所形成之氧 請 先 閱 讀 背 & 之 注 意 事 項 再 填 寫 本 頁 本紙張尺度適用中國眉家標準（CNS)A4規格（210x 297公f ) 508676 A7 B7_ 五、發明說明（） 化矽層厚度大於其他部分所形成之氧化矽層厚度約 1.5 倍。之後，形成一導電層用以覆蓋不同厚度之氧化石夕層， 接著再定義蝕刻導電層與氧化矽層，使最後形成之閘極結 構，涵蓋蟲晶石夕層第一部分上方具有厚度較厚的閘氧化 層。接下來的製程就依照傳統的方式，分別完成源極區域 的離子佈植與驅入、閘極結構的絕緣護層製程、定義閘極 結構間之接觸窗，以及金屬内連線層等製程，以完成本發 明之具有不同厚度閘氧化層的功率半導體元件。 圖式簡單說明： 由以下本發明中較佳具體實施例之細節描述，可以對 本發明之目的、觀點及優點有更佳的了解，同時參考下列 本發明之圖式加以說明： 第1圖描述先前技術中高功率半導體元件的結構剖面 圖； 第2-4圖係根據本發明一較佳實施例之一種高功率電 晶體的製造流程剖面圖。 圖號對照說明： 100 半導體基材 110 矽磊晶層 120 輕摻雜P井區 130 重摻雜N井區 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ) (請先閱讀背面之注意事項再填寫本頁)508676 A7 B7 V. Description of the invention (Field of invention: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This invention relates to a method for manufacturing a high-power semiconductor element, and more particularly to a high-power electric device with a gate oxide layer of different thickness Manufacturing method of crystal element Background of the invention: BJT is one of the most important semiconductor elements today. 'Although this element can be used for high-power components and high-speed logic circuits, The biggest drawback is that it will consume a lot of energy. At present, the development of 'metal oxide half field effect transistor (MOSFET) has gradually replaced the application of the bipolar transistor. Because it can save electricity. The metal-oxide-semiconductor field-effect transistor has become the most commonly used semiconductor element in integrated circuits. In general technology, the so-called power metal-oxide-semiconductor (POWER MOSFET) basic operation and any metal-oxide-semiconductor half-field effect The transistor is the same, but its current handling capacity can reach several amps, and its block-to-source block voltage can withstand up to about 20 V ~ 1 200V or higher. The advantage of power metal-oxide-semiconductor field-effect transistor is that it can use a small control voltage to operate the element under the condition of low power consumption. Please refer to Figure 1, which shows the common power transistor structure. Its main structure It includes a heavily doped N-type (or p-type) semiconductor substrate 100 and an N-type silicon epitaxial silicon layer 1 1 0. Above the N-type silicon epitaxial silicon layer 1 1 0, the paper size is applicable to the country of China Standard (CNS) A4 specification (210 X 297 mm) Please read the notice on the back page M i 508676 ^^ _ I___ Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 Description of the invention () There is a gate oxide layer 1 4 〇 and polycrystalline stone gate 150. In the N-type epitaxial stone layer 丨 1 (, there is a lightly doped P well region 1 2 0, as the channel region of the power metal-oxygen half field effect transistor (Body). In the lightly doped p-well region 120, there are still two heavily doped N-well regions 1 30, which are used as the source of the power semiconductor device, and a heavily doped P-well region 1 80 is used in the middle. Is the contact connection point between the metal layer and the lightly doped p-well region 1 2 0. At the polycrystalline stone gate 15 Above it is a layer of Borophosphosilicate Glass 160 (BPSG), which serves as an insulating layer for the polycrystalite gate 150. In addition, a borophosphosilicate glass 160 is provided with a metal layer 170 for contact The heavily doped N-well region is used as the source wire. According to the element design of FIG. 1, the operation of the entire device is based on the heavily-doped N-well region 130 as the source and the lightly doped p-well region. It is used as the channel region. Then the heavily doped N-type dream substrate 100 is used as the drain of the element, and the electrons enter the source region and pass through the gate inversion layer laterally to the N-type doped epitaxial silicon layer. At 110, electrons will flow vertically through the N-type doped epitaxial silicon layer uO to the drain. During the operation of the power semiconductor element, 'current flows between the source and the non-electrode via the channel region. If there is a large pass width, the current conduction capacity is reduced and the size of the pinch resistance is increased, but it is increased. Component size. Therefore, how to reduce the size of the resistor without increasing the component size becomes an important key. In addition, the thickness of the gate oxide layer of the power semiconductor device is generally about several hundred to several thousand angstroms. Because this free oxide layer is very close to the active junction and the channel of the device, the free and non-active parts of the device A considerable amount of on-capacitance is formed between the electrodes. This on-off capacitor will limit the switching speed of the component, which will cause switching loss. The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 508676 A7 B7 5. The description of the invention () is missing. Therefore, there is also a need for an improved method for manufacturing high-power semiconductor devices to solve the problem of insufficient device switching speed. Purpose and summary of the invention: Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The exposed parasite of the epitaxial silicon layer, a thermal fossil layer was performed in the other part of the middle layer. The disadvantages pointed out in the background of the invention mentioned above. Another object of the present invention is to provide a high-power semiconductor device with a different gate oxide layer thickness. Another object of the invention is to use a heteroconcentration in a high-power semiconductor device to increase the anode and The thickness of the gate oxide layer between the gates reduces the capacitance between the gates and enhances the charging speed of the gate electrodes. Ming's secondary objective is to use impurity concentrations to form gate oxide layers of different thicknesses in high power semiconductor devices to reduce device resistance and pinch resistance. The invention discloses a high-power semiconductor device. The manufacturing method is as follows. A first type epitaxy is formed on a semiconductor substrate with the same electrical properties. A patterned photoresist layer is formed on the epitaxial silicon layer for exposing the first part. Serving. Secondly, the patterned photoresist layer is used as the screen cover. The first part of the crystalline silicon layer is implanted with a first type of ion implantation to produce the epitaxial silicon layer. The first part has a higher doping ion concentration than the epitaxial silicon. Percent ion doping concentration. Then, after removing the patterned photoresist layer, a process is performed to synchronize the formation of oxygen with different thicknesses on the epitaxial silicon layer. More specifically, the oxygen formed above the first part of the epitaxial silicon layer is described in the back & Note: Please fill in this page again. The paper size is applicable to Chinese Standard (CNS) A4 (210x 297 male f) 508676 A7 B7_ 5. Description of the invention () The thickness of the siliconized layer is greater than the thickness of the silicon oxide layer formed in other parts. 1.5 times. After that, a conductive layer is formed to cover the stone oxide layers of different thicknesses, and then the conductive layer and the silicon oxide layer are defined to etch, so that the gate structure finally formed covers a thicker layer above the first part of the wormite layer. Gate oxide layer. The following processes follow the traditional methods to complete the processes of ion implantation and drive-in in the source region, the insulation coating process of the gate structure, the definition of the contact window between the gate structures, and the metal interconnect layer. In order to complete the power semiconductor device of the present invention, the gate oxide layers have different thicknesses. Brief description of the drawings: The following detailed description of the preferred embodiments of the present invention can better understand the purpose, perspectives and advantages of the present invention, while referring to the following drawings of the present invention to illustrate: Figure 1 describes the previous A cross-sectional view of the structure of a high-power semiconductor element in the technology; FIGS. 2-4 are cross-sectional views of a manufacturing process of a high-power transistor according to a preferred embodiment of the present invention. Description of drawing numbers: 100 semiconductor substrate 110 silicon epitaxial layer 120 lightly doped P well region 130 heavily doped N well region (Read the notes on the back and fill out this page)
訂 i;----- 經濟部智慧財產局員工消費合作社印製 508676 A7 B7 五、發明說明（ 140 160 180 210 220 240 250 閘氧化層 爛鱗梦玻璃 重捧雜P井區 蠢晶句7層 光阻圖案層 閘層氧化層 閘層複晶矽層 150 170 200 212 230 242 複晶石夕閘極 金屬層 半導體基材 蟲晶石夕層第一部份 輕摻雜N型井區 閘層氧化層 請 先 閱 讀 背 Sj 之 注 意 事 項 發明詳細說明 經濟部智慧財產局員工消費合作社印製 本 明藉由 化層， 並且降 幽 高功率 適當阻 導體基 體基材 接著在 N-型磊 濃度為 其 f明揭露一種高功率半導體元件的製造方法。本發 磊晶矽層不同的摻雜濃度以形成具不同厚度之閘氧 降低汲極與閘極間之電容，增強閘電極充電速度， 低ν功率半導體元件中的累積電阻與夹擊電阻。 第2圖至第4圖係根據本發明一較佳實施例之一種 電晶體的製造流程剖面圖。如第2圖所示，提供一 值之矽基材200’此基‘材可以是N +型或是p +型的半 材，以本發明之一較佳實施例中此基材為N +型半導 200，以作為所欲形成的半導體元件之汲極區域。 此N型半導體基材2 00上形成一層具有適當阻值之 晶矽層2 1 〇，於本發明之較佳實施例中該離子摻雜 1〇丨4〜1015 cm’2。 次，如第2圖所示，以圖案化後的光阻層22〇為罩 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐）Order i; ----- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 508676 A7 B7 V. Description of the invention (140 160 180 210 220 240 250 Layer photoresist pattern layer gate layer oxide layer gate layer polycrystalline silicon layer 150 170 200 212 230 242 polycrystalline stone gate metal layer semiconductor substrate insectite layer first lightly doped N-type well region gate layer The oxide layer, please read the note of Sj first. Detailed description of the invention. The Intellectual Property Bureau of the Ministry of Economic Affairs, the Employees Cooperative Co., Ltd. printed this note. A method for manufacturing a high-power semiconductor device is disclosed. Different doping concentrations of the epitaxial silicon layer of the present invention to form gate oxides with different thicknesses reduce the capacitance between the drain and the gate, enhance the gate electrode charging speed, and low ν power. Cumulative resistance and pinch resistance in a semiconductor device. Figures 2 to 4 are cross-sectional views of the manufacturing process of a transistor according to a preferred embodiment of the present invention. As shown in Figure 2, a silicon substrate with a value is provided. The 200 'this base' material may be an N + -type or p + -type half material. In a preferred embodiment of the present invention, the substrate is an N + -type semiconductor 200, which is used as a semiconductor element to be formed. Drain region. A crystalline silicon layer 2 1 0 with an appropriate resistance value is formed on the N-type semiconductor substrate 2000. In a preferred embodiment of the present invention, the ion is doped from 10 to 1015 cm'2. Next, as shown in Figure 2, the patterned photoresist layer 22 is used as the cover. The paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm).
I訂 « I I 經濟部智慧財產局員工消費合作社印製 508676 A7 B7_ 1、發明說明（） 幕，以暴露出N型磊晶矽層210之第一部份212，並於N 型磊晶矽層210之第一部份212上進行與半導體基材200 相同極性之摻雜。以本發明之較佳實施例中係利用N型雜 質進行摻雜，需特別強調的是，此N型雜質使用濃度較高 之摻雜濃度。於本發明之實施例中該N型雜質之摻雜濃度 為1018〜1〇ι9 cm-2，由於此第一部份212的掺雜濃度比N型 蟲晶矽層2 1 0其他部分之摻雜濃度為高，因此可降低高功 率半導體元件之夾擊電阻。 請參閱第3圖所描述，於去除光阻層220之後，進行 一道熱製程，以形成一閘層氧化層2 4 0。由於N蜜磊晶矽 層2 1 0之第一部份2 1 2具有比該層其他部分較濃的n型摻 雜濃度。因此’於進行熱製程以形成一閘層氧化層240的 過程中’將於N型磊晶矽層210表面同步形成具有不同厚 度的閘層氧化層240。更明確地說，於N型磊晶矽層210 之第一部份212表面上其所形成的閘層氧化層242之厚度 具有比N型磊晶矽層2 1 0其他部份表面上所形成的閘層氧 化層厚度來的厚（其厚度大約數百埃），大約厚15倍之多。 除此之外’於上述之熱製程過程中，前述於N型磊晶 矽層2 1 0之第一部份2 1 2所摻雜之N型雜質將被驅入]vi型 磊晶矽層2 1 0中’而形成較周圍濃度為高的輕摻雜N型井 區230。也由於此輕掺雜N型井區23〇的離子摻雜濃度較 濃，因此可以有效降低功率半導體元件之累積電阻以及夾 擊電阻。 之後’繼續參閱第3圖所示，在閘層氧化層240上沉 乂請先閱讀背面之注意事項再#寫本頁) tr--------- 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ'297 公t) 經濟部智慧財產局員工消費合作社印製 508676 A7 B7 五、發明說明（） 積一層複晶石夕層 2 5 0，以做為閘極之用。於本發明之一較 佳實施例中，係利用N型離子（例如：磷或砷）作為此複晶 矽層2 5 0之摻質。接著，如第4圖所描述，定義並蝕刻出 閘層複晶矽層2 5 0與閘氧化層240，以形成元件之閘極結 構。需再次說明的是，利用本發明所揭露之製程，其形成 之閘極結構具有不同厚度之閘層氧i化層 242。亦即，閘極 結構中位於輕摻雜N型井區230上方的閘氧化層242具有 較閘極結構兩邊閘氧化層約1 .5倍的厚度。 換言之，本發明可以僅僅利用一道製程便可同步形成 具有不同厚度之閘極結構，此於輕摻雜N型井區2 3 0上方 具有較大厚度的閘氧化層242將可增加汲極與閘極間閘氧 化層之厚度，以降低汲極與閘極間之電容（汲閘電容與閘氧 化層之厚度呈反比），而此汲閘電容之降低將可進一步增加 元件之切換速度，減少元件開關時之切換損失。此外，本 發明的另一個特點也在於因為利用一道熱製程便可形成不 同厚度之閘極結構，相較傳統需要兩道熱製程以形成不同 厚度之閘極結構來說·，本發明製程之熱預算不但可以實質 有效地降低，而且亦可以減少因多次加熱所引起對元件其 他部分區域的損傷。 接下來的製程，與一般傳統製程相同，陸續完成高功 率半導體元件的基底區域、源極區域、閘極絕緣層、接觸 窗及金屬連線等製程，如第4圖所示。 由上述可知，依據本發明的方法所製作的高功率半導 體元件，藉由輕摻雜磊晶矽層不同的摻雜濃度而形成不同 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) ----— lit----装·-------訂--------- (請先閱讀背面之泫意事項再填寫本頁) 508676 A7 B7 五、發明說明（） 厚度之閘 電極的充 本發 子電性， 於本發明 如熟 佳實施例 本發明之 後，凡其 更動潤飾 在下述之 層氧化 電能力 明之較 可以用 的較佳 悉此技 僅用於 精神， 它未脫 及等效 申請專 層，以 ，並降 佳實施 與本較 實施例 術之人 藉以幫 而熟悉 離本發 之改變 利範圍 降低汲 低元件 例中， 佳實施 所舉出 員所瞭 助了解 此領域 明所揭 或修飾 及其等 極與閘 之累積 用以分 例中相 者。 解的， 本發明 技藝者 示之精 ，其專 同領域 極間之電容，祕 增強閘 電阻與夾擊電随。 別進行離子植 诅入之離 反的電性，並 亚不限定 以上所述本發明之較 之實施’非用以限定 於領悟本發明之精神 神下’所完成之些許 利保護範圍當視包含 而定。 經濟部智慧財產局員工消費合作社印製 9 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐）I order «II Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 508676 A7 B7_ 1. Description of the invention () screen to expose the first part 212 of the N-type epitaxial silicon layer 210 and the N-type epitaxial silicon layer The first portion 212 of 210 is doped with the same polarity as the semiconductor substrate 200. In a preferred embodiment of the present invention, N-type impurities are used for doping. It should be particularly emphasized that this N-type impurity uses a higher doping concentration. In the embodiment of the present invention, the doping concentration of the N-type impurity is 1018 to 10 cm-2. Because the doping concentration of the first portion 212 is higher than that of other portions of the N-type worm-crystal silicon layer 2 10 The impurity concentration is high, so the pinch resistance of high-power semiconductor elements can be reduced. Referring to FIG. 3, after the photoresist layer 220 is removed, a thermal process is performed to form a gate oxide layer 2 40. Since the first portion 2 1 2 of the N honey epitaxial silicon layer 2 10 has a n-type doping concentration that is thicker than the other portions of the layer. Therefore, during the thermal process to form a gate oxide layer 240, gate oxide layers 240 having different thicknesses will be formed on the surface of the N-type epitaxial silicon layer 210 simultaneously. More specifically, the thickness of the gate oxide layer 242 formed on the surface of the first portion 212 of the N-type epitaxial silicon layer 210 is greater than that formed on the surface of the other portion of the N-type epitaxial silicon layer 210. The thickness of the oxide layer of the gate is about 15 times thicker (its thickness is about several hundred angstroms). In addition to this, during the above-mentioned thermal process, the aforementioned N-type impurities doped in the first part 2 1 2 of the N-type epitaxial silicon layer 2 1 0 will be driven into] the vi-type epitaxial silicon layer 2 10 ′, and a lightly doped N-type well region 230 having a higher concentration than the surroundings is formed. Because the ion doping concentration of the lightly doped N-type well region 23 is relatively high, the cumulative resistance and pinch resistance of the power semiconductor element can be effectively reduced. Afterwards, continue to refer to Figure 3, please read the notes on the back before sinking on the gate oxide layer 240. tr --------- This paper size applies Chinese national standards ( CNS) A4 specification (210 χ'297 g t) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 508676 A7 B7 V. Description of the invention () A layer of polycrystalline stone layer 2 50 is used as the gate. In a preferred embodiment of the present invention, N-type ions (such as phosphorus or arsenic) are used as the dopants of the polycrystalline silicon layer 250. Next, as described in FIG. 4, a gate polycrystalline silicon layer 250 and a gate oxide layer 240 are defined and etched to form a gate structure of the device. It should be explained again that the gate structure formed by using the process disclosed in the present invention has a gate oxide layer 242 with different thicknesses. That is, the gate oxide layer 242 above the lightly doped N-type well region 230 in the gate structure has a thickness of about 1.5 times greater than that of the gate oxide layers on both sides of the gate structure. In other words, the present invention can use only one process to simultaneously form gate structures with different thicknesses. The gate oxide layer 242 having a larger thickness above the lightly doped N-type well region 230 can increase the drain and gate. The thickness of the gate-to-gate oxide layer reduces the capacitance between the drain and the gate (the thickness of the gate-drain capacitor is inversely proportional to the thickness of the gate-oxide layer), and the reduction of the gate-drain capacitor will further increase the switching speed of the device and reduce the device. Switching loss when switching. In addition, another feature of the present invention is that gate structures of different thicknesses can be formed by using one thermal process. Compared with the traditional process, which requires two thermal processes to form gate structures of different thicknesses, the heat of the process of the present invention Not only can the budget be effectively reduced, but it can also reduce damage to other parts of the component caused by repeated heating. The next process is the same as the conventional process, and successively completes the processes of the base region, source region, gate insulation layer, contact window and metal connection of high-power semiconductor devices, as shown in Figure 4. From the above, it can be known that the high-power semiconductor elements manufactured according to the method of the present invention are formed with different doping concentrations of lightly doped epitaxial silicon layers. This paper size is applicable to China National Standard (CNS) A4 (210 X 297) (T) -------- lit ---- installation ------- order --------- (please read the intention on the back before filling this page) 508676 A7 B7 5 、 Explanation of the invention () The electrical property of the gate electrode of the thickness of the gate electrode. After the present invention, such as a good example, the present invention, it is better to use this technology if it can be modified and retouched in the following layers. It is only used for the spirit. It does not remove the equivalent application special layer, and reduces the implementation of this example. People who are familiar with this example will be familiar with it. Name the members to help understand the open or modified in this field and the accumulation of their poles and gates used to separate the examples. The solution shows that the artist of the present invention has the expertise in the field of inter-electrode capacitance, enhanced gate resistance and pinch voltage. Do not perform the reversible electrical properties of the ion implantation, and do not limit the above-mentioned comparative implementation of the present invention 'not for the purpose of limiting the understanding of the spirit of the present invention'. set. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 9 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)