經濟部中央揉率局貝工消费合作社印裝 i 4 5 5 8 7 a7 5773twf-d〇c/006 五、發明説明（/ ) 本發明是有關於一種功率金氧半場效電晶體（Power MOSFET)之製造方法，且特別是有關於一種雙擴散式金氧 半場效電晶體之製造方法。 功率金氧半場效電晶體係可用以放大功率、並且處理 高電壓和大電流的半導體元件。典型的功率金氧半場效電 晶體可以依照其結構而區分爲雙擴散式功率金氧半場效電 晶體與溝渠式金氧半場效電晶體等數種。 習知一種雙擴散式功率金氧半場效電晶體的結構如第 1D圖所示。 請參照第1D圖，典型的雙擴散式功率金氧半場效電 晶體的閘極106a係彤成於具有磊晶層102的基底1〇〇之 上。雙擴散式功率金氧半場效電晶體的源極區112係位於 閘極106ii兩側以外的井區110之中，其彼此之間係藉由金 屬層118來加以連接；而汲極區則位於基底100的底部。 當施加於閘極106a的電壓(Vg)大於起始電壓(V,)時， 此元件會在井區110產生強反轉層，而在閘極106a下方形 成通道，使元件在適當的偏壓之下轉變爲開啓的狀態。由 於一個閘極106a可以構成兩個雙擴散式功率金氧半場效 電晶體，因此，此種功率金氧半場效電晶體其每一個單元 (Cell)係由兩個金氧半場效電晶體所組成。 第1A至1D圖係繪示上述之雙擴散式功率金氧半場效 電晶體之製造流程的剖面示意圖。 請參照第1A圖，典型的雙擴散式功率金氧半場效電 晶體的製作方法，係在具有磊晶層102的基底100上形成 3 (請先閲讀背面之注意事項再歧本頁)Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, i 4 5 5 8 7 a7 5773twf-d〇c / 006 V. Description of the Invention (/) The present invention relates to a power metal-oxide-semiconductor field-effect transistor (Power MOSFET) The invention relates to a manufacturing method, and more particularly to a manufacturing method of a double-diffused metal-oxide half-field-effect transistor. Power metal-oxide-semiconductor field-effect transistor systems can be used to amplify power and handle high-voltage and high-current semiconductor components. Typical power metal-oxide-semiconductor FETs can be classified into double-diffused power metal-oxide MOSFETs and trench-type metal-oxide MOSFETs according to their structure. The structure of a conventional double-diffused power metal-oxide half-field-effect transistor is shown in FIG. 1D. Referring to FIG. 1D, the gate 106a of a typical double-diffusion power metal-oxide-semiconductor field-effect transistor is formed on a substrate 100 having an epitaxial layer 102. The source region 112 of the double-diffused power metal-oxide half field effect transistor is located in the well region 110 outside the two sides of the gate electrode 106ii, which are connected to each other by a metal layer 118; and the drain region is located in The bottom of the substrate 100. When the voltage (Vg) applied to the gate 106a is greater than the starting voltage (V,), this element will generate a strong inversion layer in the well region 110, and a channel is formed under the gate 106a, so that the element is at an appropriate bias The bottom turns into an open state. Since one gate 106a can constitute two double-diffused power MOSFETs, each cell (Cell) of such a power MOSFET is composed of two MOSFETs . Figures 1A to 1D are schematic sectional views showing the manufacturing process of the above-mentioned double-diffused power metal-oxide half-field-effect transistor. Please refer to Fig. 1A. A typical method for making a double-diffused power metal-oxide-semiconductor field-effect transistor is formed on a substrate 100 having an epitaxial layer 102. (Please read the precautions on the back before moving to this page)
本紙張尺度逍用中國國家揉丰（CNS ) A4規格（2丨0X297公嫠） A7 B7 4455 87 5773twf.doc/006 五、發明説明（丫） 氧化層104與複晶矽層106，之後，以微影與蝕刻技術定 義複晶矽層106之圖案以形成複晶矽閘極層l〇6a ’第1B 圖所示者。其後進行離子植入步驟108,以在磊晶層1〇2 中形成井區110。 接著，請參照第1C圖，在基底100上形成光阻層（未 繪示），並以光阻層爲植入罩幕，進行離子植入製程，以 在井區110中形成源極區112。之後，在基底100上形成 一層介電層114。 其後，請參照第1D圖，利用微影與蝕刻技術，在介 電層114之中形成接觸窗開口 116，再於基底100上形成 並定義一層金屬層118，以電性連接源極區112。 上述的方法在形成接觸窗開口 116的過程中，一旦發 生錯誤對準(Misalignment)，很可能導致金屬層118與閘極 106a不正常的電性連接。爲了避免發生錯誤對準，典型的 製程必須在製作源極區時預留邊界，以使接觸窗能著陸於 於極區。但是預留邊界將會佔用較多的晶片面積，使元件 的密度無法提昇，而導致兀件朝向高積集度(Integration)之 目標受到限制。 因此，本發明之目的就在於提供一種功率金氧半場效 電晶體的製作方法，可以避免在形成接觸窗開口的過程 中，因爲錯誤對準所造成的不正常電性導通問題。 本發明之另一目的在於提供一種功率金氧半場效電晶 體的製作方法，可用以增加微影製程的空間。 本發明之再一目的在於提供一種功率金氧半場效電晶 4 0¾ (請先閲讀背面之注項再V.V本頁) 、-β 經濟部中央梯準局貝工消费合作杜印製 本紙張尺度適用中國國家標準（〇奶）六4規格（210父297公釐） A7 B7 4455 8 7The dimensions of this paper are in accordance with Chinese National Standards (CNS) A4 (2 丨 0X297 male) A7 B7 4455 87 5773twf.doc / 006 5. Description of the invention (Ya) The oxide layer 104 and the polycrystalline silicon layer 106, and then, Lithography and etching techniques define the pattern of the polycrystalline silicon layer 106 to form the polycrystalline silicon gate layer 106a 'shown in FIG. 1B. Thereafter, an ion implantation step 108 is performed to form a well region 110 in the epitaxial layer 102. Next, referring to FIG. 1C, a photoresist layer (not shown) is formed on the substrate 100, and the photoresist layer is used as an implant mask to perform an ion implantation process to form a source region 112 in the well region 110. . Thereafter, a dielectric layer 114 is formed on the substrate 100. Thereafter, referring to FIG. 1D, a lithography and etching technique is used to form a contact window opening 116 in the dielectric layer 114, and then a metal layer 118 is formed and defined on the substrate 100 to electrically connect the source region 112 . In the process of forming the contact window opening 116 described above, once misalignment occurs, it is likely to cause abnormal electrical connection between the metal layer 118 and the gate electrode 106a. In order to avoid misalignment, a typical process must reserve a boundary when making the source region so that the contact window can land on the region. However, the reserved boundary will occupy a larger area of the chip, making it impossible to increase the density of the components, which will limit the orientation of the components toward the goal of high integration. Therefore, an object of the present invention is to provide a method for manufacturing a power metal-oxide half-field-effect transistor, which can avoid abnormal electrical conduction problems caused by misalignment during the process of forming a contact window opening. Another object of the present invention is to provide a method for manufacturing a power metal-oxide half-field-effect electric crystal, which can be used to increase the space of the lithography process. Another object of the present invention is to provide a power metal-oxide-semiconductor half-field-effect transistor 4 0¾ (please read the note on the back first, and then VV page), -β, the central government of the Ministry of Economic Affairs, the cooperation of shellfish consumer cooperation, and the printing of this paper. Applicable to Chinese National Standard (〇 奶) 6 4 specifications (210 father 297 mm) A7 B7 4455 8 7
5773twf-doc/OOG 五、發明説明（s ) 體的製作方法，可以增加元件的密度，提高元件的積集度。 根據本發明之目的，提出一種功率金氧半場效電晶體 之製造方法。此方法係在嘉晶層上形成閘極介電層、複晶 矽閘極層與頂蓋層之後，在具有磊晶層中形成井區與源極 區，其後將一物種植入於磊晶層之表面，使磊晶層之氧化 速率減緩，接著，再進行熱氧化製程，以使複晶矽閘極層 之側壁氧化而形成氧化間隙壁。最後，在基底上形成介電 層，並進行自動對準接觸窗開口製程，以在介電層中形成 裸露出源極之接觸窗開口，然後，再於接觸窗開口與介電 層之表面形成金屬層，以電性連接源極區。 依照本發明實施例所述，上述植入於磊晶層之物種包 括氮氣陽離子，其植入的方法包括離子植入法，植入的劑 量爲每平方公分1E15至3E16個離子，能量爲25KeV-150KeV 。 由於氮氣陽離子植入於磊晶層其表面之後，可以減緩 或抑制磊晶層發生氧化的現象，因此，在後續的熱氧化的 過程中，複晶矽閘極層其側壁發生氧化的速率遠大於磊晶 層其氧化之速率，所以，複晶矽閘極之側壁形成厚度約爲 2000埃至5000埃的氧化間隙壁時，磊晶矽層發生氧化的 量非常有限。 依照本發明所述，上述之頂蓋層其材質包括氮化矽； 介電層之材質包括硼磷矽玻璃。由於氮化矽頂蓋層與硼磷 矽玻璃介電層具有不同蝕刻速率，且在複晶矽閘極之側壁 具有氧化間隙壁，因此，利用氮化矽與硼磷矽玻璃具有不 本紙張尺度適用中國國家標準（CNS ) A4说格（2丨0 X 297公釐） 裝------訂------線 (請先閲讀背面之注意事項再本頁〕 經濟部中央標準局貝工消貪合作社印策 經濟部中央標準局貝工消費合作社印装 4455 8 7 5773twf,doc/006 五、發明説明（0) 同蝕刻速率的特性，以及氧化間隙壁可以保護複晶矽閘極 之優點，可以透過自動對準接觸窗之製程方式，於介電層 中形成裸露出源極區之接觸窗。 由於本發明之接觸窗係以自動對準接觸窗之製程所形 成者，因此，本發明可以增加製程之空間。而且，由於基 底並不需要預留錯誤對準的空間，因此，本發明可以減少 源極區預留邊界的面積，進而達到提昇元件密度之目的。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如下： 圖式之簡單說明： 第1A至1D圖係繪示習知溝渠式閘極功率金氧半場效 電晶體之製造流程的剖面示意圖。 第2A至2F圖係繪示依據本發明之較佳實施例，一種 功率金氧半場效電晶體之製造流程的剖面示意圖。 圖式之標記說明： 100、200 :基底 102、202 :磊晶層 104 :氧化層 106、106a :複晶砂層 108、212、218、222 :離子植入步驟 110、214 :井區 112、220 :源極區 114、204、228 :介電層 116 :接觸窗開口 6 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） I- .~ 装 „ τ11.# (請先閱讀背面之注意事吼再>*本頁) 經濟部中央橾隼局貝工消费合作社印製 44s^^7d〇c/0Q6_^____ 五、發明説明（Γ〉 118、232 :金屬層 206、206a :導體層 208、208a :緩衝層 210、210a :頂蓋層 216 :光阻層 224 :物種 226:氧化間隙壁 230 :自動對準接觸窗開口 實施例 本發明之實施例係以具有η型摻雜之砂基底、η型磊 晶矽、ρ型井區以及η型之功率金氧半場效電晶體作爲說 明。然而，在實際的應用上，本發明亦可以依照製程的調 配與改變，而並非限定於此。 第2Α至2F圖係繪示依據本發明之較佳實施例，一種 功率金氧半場效電晶體之製造流程的剖面示意圖。 請參照第2Α圖，首先，提供具有晶晶層202之砂基 底200。磊晶層202之材質譬如是具有η型摻雜的矽，且 其摻雜的濃度較低於矽基底200之摻雜濃度。之後，在基 底200上依序形成介電層204、導體層206與頂蓋層210。 上述之介電層204係作爲閘極介電層之用，其材質例 如爲氧化矽，形成的方法以熱氧化法較佳，厚度約爲400 至埃左右。導體層206之材質譬如爲複晶矽，形成 的方法例如爲化學氣相沉積法，其厚度約爲3000埃至70〇〇 埃°頂蓋層210之材質係與後續沉積之介電層具有不同倉虫 7 本纸&尺度逍用肀家標率（CNS)八4规格（210χ297公嫠1 — ----------搫-----.--11------銹！ C請先έ讀背面之注意事1再庐务頁) 4455 8 7 五、發明説明（6) 刻速率者，其較佳之材質例如爲氮化矽，形成的方法例如 爲化學氣相沉積法，厚度則約爲600埃至2000埃左右。 當頂蓋層210之材質爲氮化矽、導體層206之材質爲複晶 矽時’較佳的方法則會在進行氮化矽沉積步驟之前，先進 行熱氧化製程，使複晶矽材質之導體層206發生氧化而形 成-層厚度約爲100埃至400埃的緩衝層208，以增加氮 化矽頂蓋層210與複晶矽導體層20纟之介面特性。 請參照第2B圖，以微影與蝕刻技術定義上述之頂蓋 層210、緩緩衝層208與導體層206,以形成由頂蓋層210a、 緩衝層208a與閘極導體層2(]6a所組成之堆疊閘極。 之後，進行離子植入步驟212，以將雜質植入於磊晶 層202中’然後進行熱驅入步驟，以將離子植入步驟212 所植入之雜質驅入於磊晶層202之中，而形成井區214。 以磊晶層202爲具有n型之摻雜型態爲例，離子植入步驟 212所植入之離子以ρ型砸較佳。 經濟部中央揉率局員工消費合作社印裝 (請先閲讀背面之注項再1<,本頁) 請參照第2C圖，在基底200上形成一層光阻層216， 以覆盖頂寇層210以及部分的介電層204，裸露出預定形 成源極區220之區域。之後，以光阻層216爲罩幕層，進 行離子植入步驟218，以將雜質植入於磊晶層202的井區 214之中’用以形成源極區220。以井區214爲ρ型之摻雜 型態爲例，離子植入步驟218所植入之離子以η型砷較佳， 其植入的里約爲每平方公分6Ε15個原子，植入的能量 約爲 80KeV。 _ 之後’請參照第2D圖，去除光阻層216，並進行淸洗 8 本紙張尺度遙用中國國家樣準（CNS ) Α4規格（210X297公釐） A7 B7 5 7 7 3 twf . doc/0 0 6 五、發明説明（”） (請先聞讀背面之注意事項再气本頁) 步驟。去除光阻層216的方法例如是以電漿灰化的方式。 然後，進行熱驅入（Drive-in)製程，以使離子植入步驟2]8 所植入的雜質驅入於磊晶層202之中並且使其均勻分布， 而形成源極區220。 之後，進行離子植入步驟222，以在磊晶層202之中 植入一物種224,使磊晶層202在後續的製程中不易氧化。 離子植入步驟222所植入之物種224以氮氣陽離子（N2+)較 佳，其植入的劑量約爲每平方公分1E15至3E16個離子， 植入的能量約爲25KeV至150KeV。 請參照第2E圖，進行熱氧化製程，以使閘極導體層206a 之側壁發生氧化，而形成氧化矽間隙壁226，此氧化間隙 壁226之厚度約爲2000埃至5000埃左右。由於本發明在 進行熱氧化製程之前，已先進行一道離子植入步驟222， 使磊晶層202不易發生氧化的物種224植入於磊晶層202 之中，因此，當閘極導體層206a其側壁形成厚度約爲2000 埃至5000埃的氧化間隙壁226時，磊晶層202的表面發生 氧化的量非常有限。 經濟部中央揉率局貝工消費合作社印裂 之後，在基底200上形成一層介電層228，介電層228 之材質例如爲不具有摻雜之氧化矽層與硼磷矽玻璃 (BPSG)。不具摻雜之氧化矽層的厚度約爲1〇〇〇埃，硼磷 矽玻璃約爲5000埃。較佳的方法會在硼磷矽玻璃層沉積 之後進行高溫熱流(Therma丨Flow)製程，以使硼磷矽玻璃經 由熱流而平坦化。 ^ 其後，進行微影與非等向性蝕刻製程，以去除部分的 9 本紙張尺度逍用中國國家橾準（CNS > A4規格（210X297公釐) 經濟部中央標準局貝工消费合作社印« 4455 8 7 A7 5 7 73twf . doc / 0 06 B7 五、發明説明（P) 頂蓋層210a，從而在頂蓋層210a中形成裸露出緩衝層208a 之開口區（未繪示出）。 請參照第2F圖，以微影與蝕刻技術，進行自動對準 接觸窗製程（Self-Align Contact Process)，以在介電層228 之中形成裸露出源極區220之自動對準接觸窗開口 230。 自動對準接觸窗製程之飩刻的方法例如是先以濕式蝕刻法 去除源極區220上方之部分介電層228,再以乾式蝕刻法 進行蝕刻製程蝕刻源極區220上方之介電層228，以形成 裸露出源極區220之自動對準接觸窗開口 230。之後，再 於基底200上形成一層金屬層232，並定義其圖案，以電 性連接源極區220。金屬層232之材質例如爲鋁，其形成 的方法例如爲濺鍍法或化學氣相沉積法。 由於氮化矽頂蓋層與硼磷矽玻璃介電層具有不同蝕刻 速率，且在複晶矽閘極之側壁具有氧化間隙壁’因此’利 用氮化矽與硼磷矽玻璃具有不同蝕刻速率的特性’以及氧 化間隙壁可以保護複晶矽閘極之優點’可以透過自動對準 接觸窗之製程方式，於介電層中形成裸露出源極區之接觸 窗。 由於本發明之接觸窗係以自動對準接觸窗之製程所形 成者，因此，本發明可以增加製程之空間。而且’由於基 底並不需要預留錯誤對準的空間，因此’本發明可以以減 少源極區預留邊界的面積，進而達到提昇元件密度之目 的。 雖然本發明已以一較佳實施例揭露如上’然其並非用 本紙張尺度適用中國國家樣準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再'本頁) 音'· 4 455 8 A7 B7 5 77 3 twf . doc /0 〇6 五、發明説明（y) 請 先 鬩 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 背 之 注 意 事 項- 再 t % 經濟部中央標率局員工消费合作社印装 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨OX297公釐）5773twf-doc / OOG 5. The method of making the (s) body of the invention can increase the density of components and increase the degree of component accumulation. According to the purpose of the present invention, a method for manufacturing a power metal-oxide half field-effect transistor is proposed. In this method, a gate dielectric layer, a polycrystalline silicon gate layer, and a cap layer are formed on a Jiajing layer, and then a well region and a source region are formed in an epitaxial layer, and then a species is implanted in the epitaxial layer. The surface of the crystal layer slows down the oxidation rate of the epitaxial layer. Then, a thermal oxidation process is performed to oxidize the sidewall of the polycrystalline silicon gate layer to form an oxidation barrier. Finally, a dielectric layer is formed on the substrate, and a contact window opening process is automatically performed to form a contact window opening with the source electrode exposed in the dielectric layer. Then, the contact window opening and the surface of the dielectric layer are formed. The metal layer is electrically connected to the source region. According to the embodiment of the present invention, the species implanted in the epitaxial layer include nitrogen cations. The implantation method includes ion implantation. The implanted dose is 1E15 to 3E16 ions per square centimeter, and the energy is 25KeV- 150KeV. Since nitrogen cations are implanted on the surface of the epitaxial layer, the phenomenon of epitaxial layer oxidation can be slowed down or suppressed. Therefore, in the subsequent thermal oxidation process, the rate of oxidation of the sidewalls of the polycrystalline silicon gate layer is much greater than that of the epitaxial layer. The epitaxial layer has an oxidation rate. Therefore, when an oxide spacer having a thickness of about 2000 angstroms to 5000 angstroms is formed on the sidewall of the polycrystalline silicon gate, the amount of oxidation of the epitaxial silicon layer is very limited. According to the present invention, the material of the above capping layer includes silicon nitride; the material of the dielectric layer includes borophosphosilicate glass. Because the silicon nitride top cap layer and the borophosphosilicate glass dielectric layer have different etch rates, and there are oxidized spacers on the side walls of the polycrystalline silicon gate, the use of silicon nitride and borophosphosilicate glass has a different paper size. Applicable to China National Standard (CNS) A4 grid (2 丨 0 X 297 mm) Packing --- order --- line (Please read the precautions on the back before this page) Central Standard of the Ministry of Economic Affairs Bureau Sheller Anti-corruption Cooperative, India Policy, Central Standards Bureau Shell Economy Consumer Cooperative, Printing 4455 8 7 5773twf, doc / 006 V. Description of the Invention (0) The characteristics of the same etching rate, and the oxidation barrier can protect the polycrystalline silicon gate The advantage is that the contact window with exposed source region can be formed in the dielectric layer through the process of automatically aligning the contact window. Since the contact window of the present invention is formed by the process of automatically aligning the contact window, The invention can increase the manufacturing process space. Moreover, because the substrate does not need to reserve space for misalignment, the invention can reduce the area of the reserved boundary of the source region, thereby achieving the purpose of increasing the density of the components. Invention The purpose, features, and advantages can be more clearly understood. The preferred embodiments are described below in detail with the accompanying drawings as follows: Brief description of the drawings: Figures 1A to 1D show the conventional ditch 2A to 2F are schematic sectional views showing a manufacturing process of a power metal-oxide half field-effect transistor according to a preferred embodiment of the present invention. Description of the formula: 100, 200: substrate 102, 202: epitaxial layer 104: oxide layer 106, 106a: polycrystalline sand layer 108, 212, 218, 222: ion implantation steps 110, 214: well area 112, 220: Source regions 114, 204, 228: Dielectric layer 116: Contact window opening 6 This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) I-. ~ Installation „τ11. # (Please read the back Attention!> This page) 44s ^^ 7d〇c / 0Q6 _ ^ ____ Printed by the Central Government Bureau of Shellfish Consumer Cooperatives V. Description of the invention (Γ> 118, 232: Metal layer 206, 206a: Conductor Layers 208, 208a: buffer layers 210, 210a: top cover layer 216: photoresist layer 224: species 22 6: Oxidation spacer 230: Example of automatically aligning the contact window opening. The embodiment of the present invention uses a n-type doped sand substrate, n-type epitaxial silicon, p-type well area, and n-type power metal-oxygen half field effect. The transistor is used as an illustration. However, in practical applications, the present invention can also be adjusted and changed according to the manufacturing process, and is not limited to this. Figures 2A to 2F show a preferred embodiment of a power gold according to the present invention. A schematic cross-sectional view of the manufacturing process of an oxygen half field effect transistor. Referring to FIG. 2A, first, a sand substrate 200 having a crystal layer 202 is provided. The material of the epitaxial layer 202 is, for example, silicon with n-type doping, and its doping concentration is lower than that of the silicon substrate 200. Thereafter, a dielectric layer 204, a conductor layer 206, and a cap layer 210 are sequentially formed on the substrate 200. The above-mentioned dielectric layer 204 is used as a gate dielectric layer, and its material is, for example, silicon oxide, and the formation method is preferably a thermal oxidation method, and the thickness is about 400 to Angstroms. The material of the conductor layer 206 is, for example, polycrystalline silicon, and the formation method is, for example, chemical vapor deposition. The thickness of the conductive layer 206 is about 3000 angstroms to 70,000 angstroms. The material of the capping layer 210 is different from that of the subsequently deposited dielectric layer. Cang Chong 7 Paper & Standards Family Standard Rate (CNS) 8 4 specifications (210 × 297 males 1 — ---------- 搫 -----.-- 11 ---- -Rust! C Please read the notes on the back 1 first, and then the service page) 4455 8 7 V. Description of the invention (6) For those with a high engraving rate, the preferred material is, for example, silicon nitride, and the forming method is, for example, chemical gas. The phase deposition method has a thickness of about 600 to 2000 angstroms. When the material of the cap layer 210 is silicon nitride and the material of the conductor layer 206 is polycrystalline silicon, a better method is to perform a thermal oxidation process before the silicon nitride deposition step, so that the material of the polycrystalline silicon is The conductive layer 206 is oxidized to form a buffer layer 208 with a layer thickness of about 100 angstroms to 400 angstroms to increase the interface characteristics of the silicon nitride cap layer 210 and the polycrystalline silicon conductive layer 20A. Referring to FIG. 2B, the above-mentioned cap layer 210, buffer layer 208, and conductor layer 206 are defined by lithography and etching techniques, so as to be formed by the cap layer 210a, buffer layer 208a, and gate conductor layer 2 () 6a. Then, an ion implantation step 212 is performed to implant impurities in the epitaxial layer 202 ', and then a thermal drive step is performed to drive the impurities implanted in the ion implantation step 212 into Lei. The well layer 214 is formed in the crystal layer 202. Taking the epitaxial layer 202 as an n-type doped type as an example, it is better that the ions implanted in the ion implantation step 212 are ρ-type. Central Ministry of Economic Affairs Printed by the consumer co-operative of the bureau (please read the note on the back and then 1 <, this page) Please refer to Figure 2C to form a photoresist layer 216 on the substrate 200 to cover the top layer 210 and part of the dielectric Layer 204, exposing the region where the source region 220 is to be formed. Then, using the photoresist layer 216 as a mask layer, an ion implantation step 218 is performed to implant impurities into the well region 214 of the epitaxial layer 202 ' Used to form the source region 220. Taking the well region 214 as a p-type doped pattern as an example, the ion implantation step 218 is implanted. The ion to be implanted is preferably n-type arsenic. The implanted iris is about 6E15 atoms per square centimeter, and the implanted energy is about 80KeV. _ Afterwards, please refer to Figure 2D, remove the photoresist layer 216, and perform 淸Wash 8 This paper uses China National Standard (CNS) A4 specifications (210X297 mm) A7 B7 5 7 7 3 twf .doc / 0 0 6 V. Description of the invention (") (Please read the notes on the back first (Refill this page) step. The method for removing the photoresist layer 216 is, for example, plasma ashing. Then, a drive-in process is performed to make the ion implantation step 2] 8 implanted. The impurities are driven into the epitaxial layer 202 and uniformly distributed to form the source region 220. Then, an ion implantation step 222 is performed to implant a species 224 in the epitaxial layer 202 to make the epitaxial layer. 202 is not easy to be oxidized in the subsequent process. The species 224 implanted in the ion implantation step 222 is preferably nitrogen cation (N2 +), and the implanted dose is about 1E15 to 3E16 ions per square centimeter, and the implanted energy is about 25KeV to 150KeV. Please refer to FIG. 2E to perform a thermal oxidation process to make the gate conductor layer 206a The sidewalls are oxidized to form silicon oxide spacers 226. The thickness of the oxidation spacers 226 is about 2000 angstroms to 5000 angstroms. Because the present invention performs an ion implantation step 222 before performing the thermal oxidation process, The species 224 in which the crystal layer 202 is not susceptible to oxidation is implanted in the epitaxial layer 202. Therefore, when the gate conductor layer 206a has an oxidation spacer 226 having a thickness of about 2000 angstroms to 5000 angstroms, The amount of oxidation on the surface is very limited. After the printing of the Shellfish Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs, a dielectric layer 228 is formed on the substrate 200. The material of the dielectric layer 228 is, for example, a doped silicon oxide layer and borophosphosilicate glass (BPSG). The thickness of the undoped silicon oxide layer is about 1,000 angstroms, and the borophosphosilicate glass is about 5000 angstroms. A better method is to perform a high-temperature heat flow process after the borophosphosilicate glass layer is deposited, so that the borophosphosilicate glass is planarized by the heat flow. ^ Thereafter, lithographic and anisotropic etching processes were performed to remove a portion of the 9 paper sizes used by the Chinese National Standard (CNS > A4 size (210X297 mm)) printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs «4455 8 7 A7 5 7 73twf. Doc / 0 06 B7 V. Description of the invention (P) The top cover layer 210a forms an open area (not shown) in the top cover layer 210a which exposes the buffer layer 208a. Please Referring to FIG. 2F, a self-aligning contact process is performed using lithography and etching techniques to form an auto-aligning contact window opening 230 in the dielectric layer 228 that exposes the source region 220. A method for automatically aligning the contact window process is, for example, first removing a portion of the dielectric layer 228 above the source region 220 by a wet etching method, and then performing an etching process by a dry etching method to etch the dielectric above the source region 220. Layer 228 to form an automatic alignment contact window opening 230 that exposes the source region 220. After that, a metal layer 232 is formed on the substrate 200 and a pattern is defined to electrically connect the source region 220. The metal layer 232 The material is, for example, aluminum. The method is, for example, a sputtering method or a chemical vapor deposition method. Since the silicon nitride top cap layer and the borophosphosilicate glass dielectric layer have different etch rates, and the sidewalls of the polycrystalline silicon gate have oxidation spacers, they are therefore used Silicon nitride and borophosphosilicate glass have different etch rate characteristics, and the advantages of oxidized spacers can protect the polycrystalline silicon gate. The exposed source can be formed in the dielectric layer through the process of automatically aligning the contact window. Contact window in the area. Since the contact window of the present invention is formed by the process of automatically aligning the contact window, the present invention can increase the process space. Moreover, 'the substrate does not need to reserve space for misalignment, so 'The present invention can reduce the area of the reserved boundary of the source region, thereby achieving the purpose of increasing the density of the components. Although the present invention has been disclosed as above with a preferred embodiment', it is not applicable to the Chinese national standard (CNS) ) A4 specification (210X297 mm) (Please read the precautions on the back before 'this page') Tone '· 4 455 8 A7 B7 5 77 3 twf .doc / 0 〇6 V. Description of the invention (y) Please To limit the invention first, anyone skilled in the art can make various modifications and retouches without departing from the spirit and scope of the invention. Therefore, the scope of protection of the invention should be defined by the scope of the attached patent application. Note for the back-t%% The printed paper size of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs applies the Chinese National Standard (CNS) A4 specification (2 丨 OX297 mm)