TW448544B - Method to generate a memory-cells arrangement - Google Patents

Method to generate a memory-cells arrangement Download PDF

Info

Publication number
TW448544B
TW448544B TW089109566A TW89109566A TW448544B TW 448544 B TW448544 B TW 448544B TW 089109566 A TW089109566 A TW 089109566A TW 89109566 A TW89109566 A TW 89109566A TW 448544 B TW448544 B TW 448544B
Authority
TW
Taiwan
Prior art keywords
notch
isolation
substrate
transistor
scope
Prior art date
Application number
TW089109566A
Other languages
English (en)
Chinese (zh)
Inventor
Franz Hofmann
Josef Willer
Hans Reisinger
Till Schlosser
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Application granted granted Critical
Publication of TW448544B publication Critical patent/TW448544B/zh

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/038Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
TW089109566A 1999-05-20 2000-05-18 Method to generate a memory-cells arrangement TW448544B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19923262A DE19923262C1 (de) 1999-05-20 1999-05-20 Verfahren zur Erzeugung einer Speicherzellenanordnung

Publications (1)

Publication Number Publication Date
TW448544B true TW448544B (en) 2001-08-01

Family

ID=7908699

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089109566A TW448544B (en) 1999-05-20 2000-05-18 Method to generate a memory-cells arrangement

Country Status (3)

Country Link
DE (1) DE19923262C1 (de)
TW (1) TW448544B (de)
WO (1) WO2000072377A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6573137B1 (en) 2000-06-23 2003-06-03 International Business Machines Corporation Single sided buried strap
US6339241B1 (en) * 2000-06-23 2002-01-15 International Business Machines Corporation Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch
DE10038728A1 (de) * 2000-07-31 2002-02-21 Infineon Technologies Ag Halbleiterspeicher-Zellenanordnung und Verfahren zu deren Herstellung
US6498061B2 (en) * 2000-12-06 2002-12-24 International Business Machines Corporation Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation
DE10321496B4 (de) * 2003-05-13 2006-07-27 Infineon Technologies Ag Herstellungsverfahren für einen einseitig angeschlossenen Grabenkondensator

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0824166B2 (ja) * 1986-11-26 1996-03-06 松下電子工業株式会社 半導体装置の製造方法
US4794434A (en) * 1987-07-06 1988-12-27 Motorola, Inc. Trench cell for a dram
US4945069A (en) * 1988-12-16 1990-07-31 Texas Instruments, Incorporated Organic space holder for trench processing
JPH0384924A (ja) * 1989-08-29 1991-04-10 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US5529944A (en) * 1995-02-02 1996-06-25 International Business Machines Corporation Method of making cross point four square folded bitline trench DRAM cell
US5937296A (en) * 1996-12-20 1999-08-10 Siemens Aktiengesellschaft Memory cell that includes a vertical transistor and a trench capacitor

Also Published As

Publication number Publication date
DE19923262C1 (de) 2000-06-21
WO2000072377A1 (de) 2000-11-30

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GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees