Α7 丨 -- Β7 修正 (請先閲讀背面之注意事項再填寫本頁> 本發明係關於記憶胞配置之產生方法，特別是dram 晶胞（c e 11)配置之產生方法，其記憶胞各有一個電晶體和 一個電容器。 在此種DRAM晶胞配置中，記憶胞之資訊是以電荷之 形式儲存在電容器上。記憶胞之電晶體和電容器須互相 連接，使得在以字元線來控制電晶體時電容器之電荷可 經由位元線而讀出。 通常是力求產生一種DRAM晶胞配置，其具有很高之 封裝密度，即，每一記憶胞有很小之空間需求。 在歐洲專利文件EP0852396中描述一種DRAM晶胞配 置，其中爲了提高此封裝密度，則記憶胞之電晶體須配 置於記憶胞之電容器上方。記憶胞之主動（active)區是由 隔離結構所圍繞|隔離結構配置在基板中。在基板中每 一記憶胞須有一個凹口’此凹口之下部區中配置此記憶 經濟部智慧財產局員工消費合作社印製 此電晶體之閘 道區和下部源 下部源極/汲 相連接。該隔 一側面相面 。位元線鄰接於 了製成此種 。在基板之表 擴散至基板而 構而產生上述 電容器之記憶節點且凹口之上部區中配置 極電極《電晶體之上部源極/汲極區，通 極/汲極區是上下重疊地配置於基板中》 極區在此凹口之第一側面中是與記憶節點 離結構連接於此凹口之第二側面（其與第 對），使記憶節點在該處不與基板相鄰接 上部源極/汲極區且在基板上方延伸。爲 DRAM晶胞配置，首先須產生該隔離結構 面上產生位元線。藉由摻雜物質由位元線 產生上部源極/汲極區。鄰接於此隔離結 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Δ A Q R ,/1 »► w ·_···, 經濟部智慧財產局員工消費合作杜印製 A7 __B7__ 五、發明說明（^ ) 之凹口。此凹口之側面設有電容器介電質。此凹口中塡 入一種摻雜之多晶矽直至第一高度（其位於隔離結構之 區域中）爲止。去除此電容器介電質之裸露的部份。然 後此凹口中塡入一種摻雜之多晶矽直至第二高度（其較 第一高度還高且位於隔離結構之區域中），使多晶矽形成 該記憶節點，此記憶節點在基板上之第一高度和第二高 度之間鄰接於此凹口之第一側面。下部源極/汲極區是 由於摻雜物質由記憶節點擴散至基板而形成。 在 Ya-Chi'n King et a] "Sub-Snm Multiple-Thickness Gate Oxide Technology Using Oxygen Implantation" 1 I E D M 9 8，5 8 5中描述--種方法，藉此方法可在基板上產 生一些閘極介電質厚度不同之電晶體。在電晶體之閘極 介電質產生處之這些位置上此基板之表面須以氧或氮植 入。因此須使用一些遮罩，上述這些位置具有不同之摻 雜物質濃度。然後進行一種熱氧化作用。熱氧化物之生 長是與摻雜物質濃度及慘雜物質有關。 本發明之目的是提供一種方法以產生一種記憶胞配 置，其封裝密度較先前技藝者還大。 此目的是藉由一種記憶胞配置之產生方法來達成|首 先在基板中產生至少一個凹口。在此凹口中產生一種厚 度均勻之隔離區，其覆蓋此凹口之側面直至一種高度（其 低於基板之表面）爲止。此凹U中塡入一種導電性材料 直至此種高度爲止=以氧來進行之植入須對此表面形成 一種角度來進行，使此凹口之第一側面所受到之摻雜較 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -t-----：----訂·-------線 (請先閲讀背面之注意事項再填寫本頁y 經濟部智慧財產局員工消費合作社印製 448544 A7 _ B7 五、發明說明（4 ) 第二側面（其與第一側面相面對）者還大。藉由熱氧化 作用而產生一種隔離結構，其在凹口之第-側面上較隔 離區還厚而在凹口之第二側面上較隔離區還薄《藉由一 種非遮罩式之飩刻使隔離區之配置於第二側面上之部份 被去除，然後由第二種導電性材料所取代，以便在凹口 中由該導電性材料和第二種導電性材料來產生一種導電 性結構，其鄰接於此基板。在基板中產生記憶胞之至少 一個電晶體之下部源極/汲極區，其鄰接於該導電性結 構。在基板之表面上在下部源極/汲極區上方鄰接於此 凹口之第二側面上產生此電晶體之上部源極/汲極區。 在導電性結構上方在此凹口中產生此電晶體之閘極電極 (其與基板、導電性結構均相隔離）。 由於只在凹口之第二側面上去除該隔離區之一部份， 則可在此凹口之與第一側面直接相鄰區中配置另一組件 (例如’相鄰記憶胞之電晶體）而不會在電晶體和該組 件之間造成漏電流。此組件與電晶體之間的隔離作用是 藉由凹口第一側面上之隔離區來達成。在此凹口之第— 側面上一種位於此凹口外部之隔離結構（其使電晶體與 該組件相隔離）是不需要的，使此記億胞配置可具有一 種特別高之封裝密度。 本方法所需費用極少，這是因爲隔離區之-部份可藉 由非遮罩式之蝕刻而被去除。此種非遮罩式之蝕刻由於 下述原因而成爲可能：隔離結構可保護第一側面上之隔 離區’這是因爲其在第一側面上較隔離區還厚。此種隔 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） I--I I I I I I I I — IT 士又· I I - - ! I I 一-SJallllIEt — _(請先閱讀背面之注意事項再填寫本頁) 448544 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（4 ) 離結構在第一側面和第二側面上之厚度不同是藉由以氧 來進行之植入所達成。在第一側面上較高之氧濃度會在 熱氧化時在該處使該隔離結構生長得特別快。 一種高的封裝密度例如可以下述方式達成：須以一種 類似於該電晶體之另一電晶體來產生一種類似於該凹口 之另一凹口，使此另一凹口之第-·側面是與該凹口之第 二側面相面對。須產生此電晶體之上部源極/汲極區， 使其鄰接於該另一凹口之第一側面。 只在各凹口之第二側面上去除此隔離區之一部份時可 產生各記憶胞之電晶體之上部源極/汲極區，使其鄰接 於一些相鄰之凹口而不會在各電晶體之間造成短路現 象。因此可緊密相鄰地產生各記憶胞之電晶體，這表示 此記憶胞配置之封裝密度較高。 上述之隔離結構例如可由Si02構成。 隔離區之一部份例如可藉由等向性之蝕刻來去除。若 隔離區由一種和隔離結構不同之材料所構成，則此種等 向性蝕刻可選擇性地對隔離結構來進行。隔離區例如可 由氮化矽來構成。在此種情況下例如可使用磷酸作爲蝕 刻劑。 但隔離區亦可藉由S i 0 2之共形（C ο n f 〇 r m )沈積而產生。 由於所沈積之氧化物和熱生長之氧化物所具有之厚度不 同。沈積而成之氧化物之蝕刻劑所造成之侵蝕刻作用較 熱生長之氧化物之蝕刻劑之侵蝕作用大很多。在此種情 況下此種等向性蝕刻因此是以非選擇性地對該隔離結構 -6 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^-----„----訂---------線 (請先閱讀背面之注音？事項再填寫本頁 4485 4 4 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（π ) 來進行，雖然該隔離結構幾乎不會受到侵蝕。 非遮罩式之蝕刻亦可藉由非等向性之蝕刻來進行。隔 離區之一部份因此可被去除，在此種情況下此第二側面 上之隔離結構較佳是特別薄，使隔離結構能以欠（under) 蝕刻方式來進行。此隔離結構在第二側面上須較薄，使 其下之隔離區在蝕刻時不會受到保護。這是由於··非等 向性之蝕刻並非只在垂直方向中進行。第二側面上之隔 離結構之厚度較佳是小於5ιιηι。由於在氧化作用時基板 之矽會嵌入氧化物中，則該隔離結構可較該隔離區更突 入於基板中，使得在非等向性蝕刻時隔離結構之厚度大 約只有一半必須被欠（U n d e r)蝕刻。 若導電性材料是由摻雜之多晶矽所構成，則在此導電 性材料上亦會生長一種氧化物。在此種情況下須對此氧 化物進行蝕刻，直至該隔離區裸露於凹口之第二側面爲 止，因此隨後可去除該隔離區之一部份。此種氧化物之 蝕刻可在非遮罩式蝕刻期間進行。另一方式是首先以第 一蝕刻劑來對此氧化物進行蝕刻，在該隔離區裸露之後 以第二側面劑來對該隔離區進行蝕刻。 爲了使第一側面上之隔離結構之厚度與第二側面上之 隔離結構之厚度之間的差異變大’則可在該隔離結構產 生之前利用氮以對此表面形成某種角度之方式來進行一 種植入，使此凹口之第二側面所受之摻雜度較此凹口之 第一側面者還大。由於氮會妨礙熱氧化物之生長，則第 二側面上之隔離結構在此情況下特別薄。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Α7 丨-Β7 correction (please read the notes on the back before filling in this page> The present invention is about the generation method of memory cell configuration, especially the method of generating the dram cell (ce 11) configuration, each of which has its own memory cell A transistor and a capacitor. In this DRAM cell configuration, the information of the memory cell is stored on the capacitor as a charge. The transistor and capacitor of the memory cell must be connected to each other so that the word is used to control the electricity. The charge of the capacitor in the crystal can be read out through the bit line. It is usually sought to produce a DRAM cell configuration with a high packing density, that is, each memory cell has a small space requirement. In European patent document EP0852396 Describes a DRAM cell configuration, in order to increase the packaging density, the transistor of the memory cell must be arranged above the capacitor of the memory cell. The active area of the memory cell is surrounded by an isolation structure | The isolation structure is arranged on the substrate Medium. Each memory cell in the substrate must have a notch. 'This notch is configured in the lower area of the memory. The Intellectual Property Bureau of the Ministry of Economic Affairs' employee consumption cooperation The gate area of this transistor is printed with the lower source / source connection of the lower source. The side faces are opposite to each other. The bit lines are adjacent to make this. The surface of the substrate diffuses to the substrate to produce the above. The capacitor's memory node is provided with an electrode in the upper region of the notch "source / drain region above the transistor, and the pass / drain region is arranged on the substrate in an overlapping manner." Among the sides is the second side (its pair) that is connected to the notch from the memory node, so that the memory node does not connect to the upper source / drain region adjacent to the substrate and extends above the substrate. The DRAM cell configuration must first generate bit lines on the isolation structure surface. The upper source / drain region is generated from the bit lines by the dopant material. Adjacent to this isolation junction, the paper dimensions are applicable to Chinese national standards (CNS ) A4 specification (210 X 297 mm) Δ AQR, / 1 »► w · _ ···, consumer cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs, printed A7 __B7__ 5. Notch of the description of the invention (^). This recess A capacitor dielectric is provided on the side of the mouth. A doped polycrystalline silicon up to the first height (it is located in the area of the isolation structure). The exposed portion of the capacitor dielectric is removed. Then a doped polycrystalline silicon is inserted into the recess up to the second height (which is more than The first height is also high and is located in the region of the isolation structure), so that the polycrystalline silicon forms the memory node, which is adjacent to the first side of the notch between the first height and the second height on the substrate. The lower source The / drain region is formed by the diffusion of the dopant material from the memory node to the substrate. In Ya-Chi'n King et a] " Sub-Snm Multiple-Thickness Gate Oxide Technology Using Oxygen Implantation " 1 IEDM 9 8, 5 8 Described in 5-a method by which some transistors with different gate dielectric thicknesses can be produced on the substrate. The surface of this substrate must be implanted with oxygen or nitrogen at these locations where the gate dielectric of the transistor is generated. Therefore, some masks must be used. These locations have different dopant concentrations. Then a thermal oxidation is performed. The growth of thermal oxides is related to the concentration of dopant substances and miscellaneous substances. It is an object of the present invention to provide a method for generating a memory cell configuration with a higher packing density than previous artisans. This goal is achieved by a method of generating memory cell configurations. First, at least one notch is created in the substrate. An isolating region of uniform thickness is created in this notch, which covers the sides of this notch up to a height (which is lower than the surface of the substrate). A conductive material is inserted into the recess U until such a height = implantation with oxygen must be performed at an angle to this surface, so that the doping on the first side of the recess is less than -4- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) -t -----: ---- Order · ------- Line (Please read the precautions on the back before Fill out this page y Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 448544 A7 _ B7 V. Description of the invention (4) The second side (which faces the first side) is still large. It is produced by thermal oxidation. Isolation structure, which is thicker than the isolation area on the first side of the notch and thinner than the isolation area on the second side of the notch. The isolation area is arranged in the second by a non-masked engraving. The part on the side is removed and then replaced by a second conductive material to create a conductive structure in the notch from the conductive material and the second conductive material, which is adjacent to the substrate. Lower source / drain region of at least one transistor in a memory cell, which is adjacent to A conductive structure. The upper source / drain region of the transistor is created on the second side of the substrate above the lower source / drain region adjacent to the notch. Above the conductive structure is in this notch. The gate electrode of the transistor is generated (which is isolated from the substrate and the conductive structure). Since only a part of the isolation region is removed on the second side of the notch, it can be connected to the first Another component (such as the transistor of the adjacent memory cell) is arranged in the directly adjacent area on the side without causing leakage current between the transistor and the component. The isolation between this component and the transistor is through the concave This is achieved by the isolation zone on the first side of the mouth. On the first side of this notch, an isolation structure outside the notch (which isolates the transistor from the component) is not needed, making this a billion cells. The configuration can have a particularly high packaging density. This method requires very little cost because part of the isolation area can be removed by non-masked etching. This non-masked etching is due to the following Caused by: Isolation Structure Can protect the isolation area on the first side 'This is because it is thicker than the isolation area on the first side. This paper size is applicable to the Chinese National Standard < CNS) A4 (210 X 297 mm) I- -IIIIIIII — IT Scholar and II--! II I-SJallllIEt — _ (Please read the notes on the back before filling out this page) 448544 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (4) The difference in thickness of the separation structure on the first and second sides is achieved by implantation with oxygen. A higher oxygen concentration on the first side will cause the isolation structure to grow particularly fast there during thermal oxidation. A high packing density can be achieved, for example, in such a way that another transistor similar to the transistor must be used to create another notch similar to the notch, so that the--side of the other notch Is facing the second side of the notch. The source / drain region above the transistor must be created so as to abut the first side of the other notch. When only a part of this isolation region is removed on the second side of each notch, the upper source / drain region of the transistor of each memory cell can be generated, so that it is adjacent to some adjacent notches and does not A short circuit occurs between the transistors. Therefore, the transistors of the memory cells can be generated in close proximity, which means that the packing density of the memory cell configuration is high. The above-mentioned isolation structure may be formed of, for example, SiO 2. A part of the isolation region can be removed, for example, by isotropic etching. If the isolation region is made of a material different from the isolation structure, this isotropic etching can be selectively performed on the isolation structure. The isolation region may be formed of, for example, silicon nitride. In this case, for example, phosphoric acid can be used as an etchant. However, the isolation region can also be generated by the conformal (C ο n f om r) deposition of S i 0 2. Due to the different thicknesses of the deposited oxide and the thermally grown oxide. The etching effect of the oxide of the deposited oxide is much greater than that of the oxide of the thermally grown oxide. In this case, this isotropic etching is therefore non-selective for the isolation structure-6-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ^ ----- „---- Order --------- line (please read the note on the back? Matters before filling out this page 4485 4 4 Printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (π ), Although the isolation structure is hardly eroded. Non-masked etching can also be performed by anisotropic etching. Part of the isolation area can therefore be removed, in which case this The isolation structure on the second side is preferably particularly thin, so that the isolation structure can be under-etched. This isolation structure must be thin on the second side so that the isolation area below it will not be etched. Protected. This is due to the fact that anisotropic etching is not performed only in the vertical direction. The thickness of the isolation structure on the second side is preferably less than 5 μm. Because the silicon of the substrate is embedded in the oxide during oxidation , The isolation structure can project more into the substrate than the isolation region So that only about half of the thickness of the isolation structure must be under-etched during anisotropic etching. If the conductive material is composed of doped polycrystalline silicon, a kind of Oxide. In this case, the oxide must be etched until the isolation region is exposed on the second side of the notch, so a part of the isolation region can be subsequently removed. The etching of this oxide can be performed at It is performed during non-masked etching. Another method is to first etch the oxide with a first etchant, and after the isolation region is exposed, the isolation region is etched with a second side agent. In order to make the first side surface The difference between the thickness of the isolation structure on the second side and the thickness of the isolation structure on the second side becomes larger. Then, before the isolation structure is created, nitrogen can be used to implant the surface at a certain angle, so that The second side of the notch is more doped than the first side of the notch. Since nitrogen can hinder the growth of thermal oxides, the isolation structure on the second side is in this case Particularly thin. This paper scales applicable Chinese National Standard (CNS) A4 size (210 X 297 mm)
I I------------t-八--I s l· I I I ^ - ---------- (請先闉讀背面之注意事項再填寫本頁V 448544 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（^ ) 在傾斜式植入氧或氮時上述角度之大小是與凹口之大 小有關。此種角度至少須夠大，使Η 口之相對應之側面 被摻雜直至此凹口中已塡入之導電性材料之高度處爲 止。此種角度因此至少是基板表面和此凹口中所塡入之 導電性材料所在之高度之間之距離除以第一和第二側面 之間的距離之反正切函數（taiT1)。 本發明之範圍亦包括：每個記憶胞中產生一個凹口。 此凹口例如具有另二個側面，此二個側面互相面對且隔 離區在此二個側面上較佳是像在第一側面中一樣同樣不 可去除。該導電性結構在此情況下用作此記憶胞之電容 器之記憶節點。在此種情況下須對這些凹口進行配置， 使二個相互間具有最小距離之凹口是互相配置在對角線 上。 記憶胞之各電容器可具有一個共同之電極，其可由基 板中之已摻雜之層所構成。在此種情況下各電晶體之上 部源極/汲極區是與位元線相連接，位元線是垂直於字 元線而延伸。字元線是與電晶體之閘極電極相連接。間 極電極可以是字兀線之一部份。 另一方式是：電容器之電極是與位元線相連接，位元 線可以基板中之條形之摻雜區來構成。 本發明之範圍包括；須產生一種凹口，使其具有-.個 與基板之表面相平行之橫切面，此橫切面是條形的。相 鄰而配置之各凹口互相平行而延仲。導電性結構在此種 情況下用作位元線。電晶體之上部源極/汲極區是與記 -8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I---t-----r---訂---I--111^. ΐ請先閱讀背面之注意事項再填寫本頁> 經濟部智慧財產局員工消費合作社印製 448544 A7 B7 五、發明說明（7) 億胞之電容器相連接。 下部源極/汲極區藉由退火步驟而產生，其中此摻雜 物質由導電性結構擴散至基板中且在基板中形成下部源 極/汲極區。 另一方式是在基板中產生摻雜之埋入層，由此層藉由 結構化而產生下部源極/汲極區。 本發明之實施例以下將依據圖式來描述。圖式簡單說 明： 第1圖在氧化物層、氮化物層、凹口 '電容器介電質 以及隔離區產生之後第-基板之橫切面。此外，亦顯示 氧之植入方向以及氮之植入方向。 第2圖在產生各隔離結構之後第1圖之橫切面。 第3圖在導電性結構產生之後第2圖之橫切面。 第4a圖在閘極介電質、上部源極/汲極區、字元線' 下部源極/汲極區和隔離層產生之後第3圖之橫切面。 第4b圖是第一基板之俯視圖’其中顯示各凹口、上部 源極/汲極區和隔離溝渠。 第5圖在產生凹口、氧化物層、隔離區、導電性結構' 字元線、上部源極/汲極區、下部源極/汲極區和隔離 層之後第二基板之橫切面。 這些圖式未依比例繪製。 在第·實施例中’設有.種由單晶矽所構成之第·基 板1。在第-·基板1中在基板1之表面F下方大約lym 處配置一種大約7 m厚之n -摻雜之埋入層P ° 本紙張尺度適用争國國家標準（CNS)A4規格（210 x 297公釐） I I ^1 ^1 ϋ ϋ ϋ n I .^1 ϋ ϋ I ϋ ϋ ϋ n I 一-0，· ft I (請先閲讀背面之注音^事項再填寫本頁〕 A 485 4 4 經濟部智慧財產局員Η消費合作社印製 A7 ___B7_ 五、發明說明（# ) 產生大約3 0 0 n m深之隔離溝梨S且以S i 0 2塡入（第4 b 圖此隔離溝渠S具有一種外翻區，外翻區具有一種正 方形（邊長大約1 0 0 n m )之水平橫切面。隔離溝渠S之 外翻區互相配置在大約1 00 n m之間距中。隔離溝渠S相 互間之距離大約是2 0 0 n m。 爲了產生氧化物層〇，須藉由熱氧化作用而產生厚度大 約是2 0 n m之S i 02，其上沈積厚度大約是5 0 n m之氮化 矽，以便產生一種氮化物層N (第1圖）。 然後在基板1中產生大約7 a m深之凹口 V，其水平橫 切面是正方形的且邊長大約是1 0 0 n m。凹口 V須鄰接於 隔離溝渠S，以便在第一基板1中形成矽島，其具有矩形 (邊長是1 〇 0 n m和2 0 0 n m )之橫切面。氮化物層N和氧 化物層〇因此被結構化。每一凹口 V具有第一側面F 1 和第二側面F 2 (其與第一側面F 1相面對），第二側面F 2 分別鄰接於各矽島中之一。此外，每一凹口具有另二個 互相面對之側面，其分別鄰接於隔離溝渠S中之一。 然後沈積厚度大約是5nm之氮化矽且使其一部份被氧 化，其上沈積厚度大約是300nm之同次（in situ)摻雜之晶 矽Y 1且進行回（back)蝕刻，使凹口 V中塡入多晶矽Y 1 (第1圖）直至下部高度處（未顯示）爲止。然後例如 以氫氟酸和CF4、〇2、N2使已氧化之氮化矽和其下方之 氮化矽之裸露之部份被去除。氮化矽和已氧化之氮化矽 之剩餘之部份形成電容器之介電質。 爲了產生各隔離區II，須以共形（con form)方式沈積厚 -10- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I I-----"-----Γ---訂-----I-- <請先闇讀背面之注意事項再填寫本頁-✓ Λ4Β544 A7 B7 五、發明說明（9 ) 度大約3 0 n m之S i 0 2且進行回蝕刻，使隔離區I丨只覆蓋 凹口 V之側面。 (請先閱讀背面之注意事項再填寫本頁> 然後沈積另--同次摻雜之多晶矽Y 2且進行回蝕刻直至 上部高度h (其位於下部高度上方大約400nm)處爲止。 隔離區Ϊ 1之裸露之部份例如以氫氟酸去除（第1圖）^ 然後以相對於第…基板1之表面F大約是7 0°之角度 將氧植入’使凹口 V之第一側面F 1被植入氧，而第二側 面F 2 (其與第一側面相面對）不植入氧。此種植入之角 度對這些與隔離溝渠S相鄰接之各凹.口 V之相面對之側 面而言是〇°。在第1圖中顯示的是氧之植入方向rl。 在凹口 V之第一側面F 1之區域中第一基板1之摻雜物 質濃度大約是i〇2lcnr3。 然後在相對於第一基板1之表面F大約是70°之角度 下進行氮之植入，使凹口 V之第二側面F 2中植入氮，但 凹口 V之第一側面F 1中不植入氮（第1圖）。此處該植 入方向r 2對這些與隔離溝渠S相鄰接之各凹口 V之相面 對的側面而言所形成之角度是0°。氧之植入方向r 1與 氮之植入方向r2之間的角度因此是4 0°。 經濟部智慧財產局員工消費合作社印製 在凹口 V之第二側面F2之區域中之第一基板1之氮之 摻雜物質濃度大約是10l8cm_3。 爲了產生這些隔離結構12 1須進行-·種熱氧化作用。 這些隔離結構12在凹η V之第一側面F !上由於較高之 氧濃度而使厚度大約是2 0 n m »在凹「」V之第二側面F2 上此隔離結構丨2由於氮之植入而只具有大約5 n m之厚度 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 A4S5 4 4 A7 _ B7 五、發明說明（、。） (第2圖）。 然後對Si02進行回（back)蝕刻大約50nm深，使凹口 V 中之多晶矽Y 2裸露出來以及隔離區I 1之配置於凹口 V 之第二側面F2上之這些部份亦裸露出來且此隔離區I 1 之鄰接於凹口 V之第二側面F 2上之這些部份被去除（第 3圖）° 隔離區Π之已去除之部份是由同次（i n s i t u )摻雜之多 晶矽所取代，其過程是須沈積厚度大約是2 0 n m之同次摻 雜之多晶矽且然後例如以KO Η進行濕式蝕刻。此種摻雜 之多晶矽與凹口 V中其餘巳摻雜之多晶矽Υ 1、Υ 2 —起 形成導電性結構L，其鄰接於第一基板1。 然後以垂直方式植入氧，使導電性結構L之上部以大 約10I9cm·3之摻雜物質濃度而被摻雜。 然後沈積一種光漆且以化學-機械方式而被拋光直节氮 化物層N裸露爲止，使凹口 V中塡入此種光漆。然後以 η -摻雜之離子進行一種植入，以便在矽島中產生各電晶體 之上部源極/汲極區S/D〇 (第4a圖）。各上部源極/汲 極區S/Do是藉由隔離溝渠S而互相隔離。 然後例如以磷酸來去除氮化物層N。 例如以氫氟酸來對Si02進行濕式蝕刻而使隔離結構12 之配置於凹D V之第二側面F 2上之這些部份被去除。 藉由熱氧化作用而產生電晶體之閘極介電質Gd ’這些 G d配置於凹口 V之第二側面F 2上且覆蓋此導電性結構 L。閘極介電質Gd由於以氧植入而在導電性結構L上具 -1 2- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^ -----„----訂---------線 -S請先閱讀背面之;i音？事項再填寫本頁> A7 5 4 _B7 _ 五、發明說明（"） 有大約200nm之厚度，而此Gd在凹口 V之第二側面F2 上之厚度只有5nm (第4a圖）。 在產生閘極介電質<3 d時，由於高的溫度使摻雜物質由 導電性結構L擴散至第·基板1中，以便產生電晶體之 與凹口 V之第二側面F 2相鄰接之下部源極/汲極區 S/Du。 爲了產生字元線W，須沈積厚度大約是1 00 n m之同次 (in situ)摻雜之多晶矽使塡入凹口 V中，此多晶矽上沈積 厚度大約是8 0 n m之矽化鎢。爲了產生一種隔離層I 3，須 沈積厚度大約是50nm之氮化矽》 藉助於條形之光漆遮罩（其條形大約1 OOnm寬，平行 於隔離溝渠而延伸且覆蓋各凹口 V )而選擇性地對Si02 來對氮化矽、矽化鎢和多晶矽進行蝕刻，直至氧化物層〇 裸露爲止。因此由矽化鎢和多晶矽而產生字元線W (第 4 a 圖）。 在上部源極/汲極區S/Do上在字元線W旁產生一些接 觸區（未顯示）。然後產生位元線（未顯示），這些位元 線垂直於字元線W而延伸且經由接觸區而與上部源極/ 汲極區S/Do相連接。 字元線W之此.部份（其配置於導電性結構L上方之 凹口 V中）用作電晶體之閘極電極。第一基板1之此一 部份（其配置於下部源極/汲極區s / D u和上部源極/汲 極區S/Do之間）用作電晶體之辱道區。導電性結構用作 電容器之記億節點。埋入層P用作電容器之共同之電極。 -I 3 - 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐） -- I— I n ϋ I I n - -1 —1 K - - I n I - - - 一5Ja - I - - - - I— - I ϋ (請先閱讀背面之注意事項再填寫本百' ) 經濟部智慧財產局員工消費合作社印製 4 485 4 4 、 A7 B7 五、發明說明（ο) 由上述方法所產生之dram晶胞配置中之記憶胞包含 一個電晶體及一個與此電晶體相連接之電容器。 {請先閱讀背面之法意事項再填寫本頁) 在第二實施例中設有--種由單晶矽所構成之第二基板 2。就像第一實施例一樣，須產生氧化物層和氮化物層（未 顯示）。 然後在基板2中產生大約50〇nm深之叩口 V'，其具有 條形之水平橫切面。這些凹口 V’因此具有溝渠之形式且 基本上是互相平行而延伸。這些凹口 V大約lOOnm寬且 相互間之距離大約是1 〇 〇 n m = 然後產生各隔離區Η' >其過程是以共形（conform)方式 沈積厚度大約30nm之Si02(第5圖）。 類似於第一實施例而產生各隔離區12’、導電性結構 L_、閘極介電質Gd1、上部源極/汲極區S/D〇|、下部源 極/汲極區S/Du_、閘極介電質Gd'、字元線W'以及隔離 層 13,。 在字元線W’上方產生電容器（未顯示），這些電容器分 別與電晶體之上部源極/汲極區S/Do_相連接》 導電性結構L'用作位元線。 經濟部智慧財產局員工消費合作社印製 由上述方法所產生之DRAM晶胞配置之記憶胞分別包 含一個電晶體以及-個與此電晶體相連接之電容器。 這些實施例可以有很多變型，其同樣在本發明之範圍 中。特別是上述各層，遮罩和凹口之大小可依據各別之 需求而調整。 藉由氧之氧直式植入而在導電性結構上生長閘極介電 -14- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公茇〉 448544 A7 B7 五、發明說明（Μ ) (請先閱讀背面之注意事項再填寫本頁^ 質之一部份’其特別厚，閘極電極因此可與導電性結構 電容性地（C a p a c it i V e 1 y)去耦合。此種方法之另—方式是 可在導電性結構產生之後以非共形之方式藉由H D P ()方 法而沈積S i 0 2 ’以便在各凹口之側面上沈積大約2 〇 n m之 S i 0 2以及在導電性結構上沈積大約6 0 n m之S i Ο 2。在去 除氮化物層之後對S i 0 2進行等向性蝕刻直至此種由H D P 方法所沈積之S i02由各隔離結構去除爲止。在導電性結 構上因此殘留一種大約3 0 n m厚之由S i Ο 2所構成之層。 各隔離結構之配置在凹口之第二側面上之這些部份如各 實施例中所述須去除。閘極介電質是由隨後之熱氧化所 產生且由於S i 0 2 (其配置在導電性結構上）而只覆蓋凹 口之第二側面之一部份。因此可省略氧之垂直式植入過 程。 經濟部智慧財產局員工消費合作社印數 符號說明 I 2…基板 F…表面 Fl，F2…側面 Gd，Gd1…間極介電質 h…高度 Π，II’…隔離區 12, T21…隔離結構 13, [3’…隔離層 Kd···電容器介電質 L, L'···導電性結構 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 448544 A7 __B7_ 五、發明說明（i4 ) N…氮化物層 0，0 '…氧化物層 P…埋入層 r】，r 2…植入方向 S…隔離溝渠 S/Do, S/Du, S/Do1, S/Du『…源極/汲極區 V，V，…凹口 w，W1···字元線 Y 1，Y2…多晶矽 I ί ----r----訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）I I ------------ t-eight--I sl · III ^----------- (Please read the notes on the back before filling in this page V 448544 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (^) The angle above is related to the size of the notch when the oxygen or nitrogen is implanted obliquely. This angle must be at least large enough so that The corresponding side of the opening is doped up to the height of the conductive material inserted into the notch. This angle is therefore at least between the surface of the substrate and the height of the conductive material inserted into the notch. The inverse tangent function (taiT1) of the distance divided by the distance between the first and second sides. The scope of the present invention also includes: generating a notch in each memory cell. This notch, for example, has two other sides, these two The sides are facing each other and the isolation area is preferably as indelible on both sides as in the first side. The conductive structure is in this case used as the memory node of the capacitor of the memory cell. These notches must be configured so that the two have a minimum distance from each other The notches are arranged diagonally to each other. Each capacitor of the memory cell may have a common electrode, which may be composed of a doped layer in the substrate. In this case, the source / drain above each transistor The area is connected to the bit line, which extends perpendicularly to the word line. The word line is connected to the gate electrode of the transistor. The intermediate electrode can be part of the word line. Another The method is: the electrode of the capacitor is connected to the bit line, and the bit line can be composed of strip-shaped doped regions in the substrate. The scope of the present invention includes: a notch must be generated so that it has-. And the substrate The surface is parallel to the cross-section, and the cross-section is strip-shaped. The adjacent notches are parallel to each other and extend. The conductive structure is used as a bit line in this case. The source above the transistor / Drain region is Yuji -8- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I --- t ----- r --- Order --- I-- 111 ^. Ϊ́Please read the notes on the back before filling out this page> Printed by Employee Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs 4485 44 A7 B7 V. Description of the invention (7) The capacitors of billion cells are connected. The lower source / drain region is generated by an annealing step, in which the doped substance diffuses from the conductive structure into the substrate and forms the lower portion in the substrate. Source / drain region. Another way is to create a doped buried layer in the substrate, so that the layer is structured to generate a lower source / drain region. Embodiments of the present invention will be described below according to the drawings Description. Brief description of the figure: Figure 1 shows the cross-section of the first substrate after the oxide layer, nitride layer, notch 'capacitor dielectric, and isolation region are created. In addition, the implantation direction of oxygen and the nitrogen Implantation direction. Figure 2 is a cross-section of Figure 1 after the isolation structures are created. FIG. 3 is a cross-section of FIG. 2 after the conductive structure is generated. FIG. 4a is a cross-section of FIG. 3 after the gate dielectric, the upper source / drain region, the word line 'lower source / drain region, and the isolation layer are generated. Figure 4b is a top view of the first substrate ', which shows the notches, upper source / drain regions, and isolation trenches. Fig. 5 is a cross section of the second substrate after the notch, oxide layer, isolation region, conductive structure 'word line, upper source / drain region, lower source / drain region, and isolation layer are generated. These figures are not drawn to scale. In the first embodiment, a first substrate 1 made of single crystal silicon is provided. In the first-substrate 1, a n-doped buried layer P of about 7 m thick is arranged at about lym below the surface F of the substrate 1. This paper size applies the national standard (CNS) A4 specification (210 x 297 mm) II ^ 1 ^ 1 ϋ ϋ ϋ n I. ^ 1 ϋ ϋ I ϋ ϋ ϋ n I One -0, · ft I (Please read the note on the back ^ before filling this page] A 485 4 4 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives A7 _B7_ V. Description of the Invention (#) Generates an isolation trench pear S with a depth of about 300 nm and enters it with S i 0 2 (Figure 4b. This isolation trench S has a Eversion area, the eversion area has a horizontal cross-section of a square (side length is about 100 nm). Isolation ditch S. The eversion area is arranged at a distance of about 100 nm from each other. The distance between the isolation ditch S is approximately It is 200 nm. In order to generate the oxide layer 0, it is necessary to generate Si02 with a thickness of about 20 nm by thermal oxidation, and deposit silicon nitride with a thickness of about 50 nm in order to generate a kind of nitrogen. Compound layer N (Fig. 1). Then a notch V having a depth of about 7 am is generated in substrate 1, the horizontal cross section of which is square and The side length is about 100 nm. The notch V must be adjacent to the isolation trench S in order to form a silicon island in the first substrate 1, which has a rectangular cross-section (side length is 100 nm and 2000 nm). The nitride layer N and the oxide layer 0 are thus structured. Each notch V has a first side F 1 and a second side F 2 (which face the first side F 1), and a second side F 2 Adjacent to one of the silicon islands respectively. In addition, each notch has two other sides facing each other, which respectively adjoin one of the isolation trenches S. Then, a silicon nitride having a thickness of about 5 nm is deposited and made A part is oxidized, and the in-situ doped crystalline silicon Y 1 with a thickness of about 300 nm is deposited thereon and back etched to inject polycrystalline silicon Y 1 into the recess V (FIG. 1) Up to the lower level (not shown). Then the exposed parts of the oxidized silicon nitride and the silicon nitride underneath are removed, for example, with hydrofluoric acid and CF4, 02, N2. The silicon nitride and the The remainder of the oxidized silicon nitride forms the dielectric of the capacitor. In order to generate each of the isolation regions II, it must be in a conformal manner Jiuhou-10- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I I ----- " ----- Γ --- Order ----- I- -< Please read the notes on the back covert before entering this page-✓ Λ4B544 A7 B7 V. Description of the invention (9) S i 0 2 with a degree of about 30 nm and etch back so that the isolation area I only covers the recess Side of mouth V. (Please read the precautions on the back before filling in this page> and then deposit another-the same doped polycrystalline silicon Y 2 and etch back until the upper height h (which is about 400nm above the lower height). Isolation area Ϊ The exposed part of 1 is removed, for example, with hydrofluoric acid (Fig. 1) ^ and then oxygen is implanted at an angle of about 70 ° relative to the surface F of the substrate 1 to make the first side F of the notch V 1 is implanted with oxygen, while the second side F 2 (which faces the first side) is not implanted with oxygen. The angle of this implantation is to each of these recesses adjacent to the isolation trench S. The phase of the opening V The facing side is 0 °. The implantation direction of oxygen is shown in Fig. 1. The doping concentration of the first substrate 1 in the region of the first side F 1 of the notch V is approximately i. 〇2lcnr3. Nitrogen implantation is then performed at an angle of about 70 ° relative to the surface F of the first substrate 1, so that nitrogen is implanted into the second side F 2 of the notch V, but the first side of the notch V Nitrogen is not implanted in F 1 (Fig. 1). Here, the implantation direction r 2 is opposite to the facing sides of the notches V adjacent to the isolation trench S. The angle formed is 0 °. The angle between the implantation direction of oxygen r 1 and the implantation direction of nitrogen r2 is therefore 40 °. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is printed on the second side of the notch V The concentration of the nitrogen doping substance of the first substrate 1 in the region of F2 is about 1018 cm_3. In order to produce these isolation structures 12 1-a kind of thermal oxidation is required. These isolation structures 12 are on the first side F of the recess η V! The thickness is about 20 nm due to the higher oxygen concentration. »The isolation structure on the second side F2 of the concave" V "2 has a thickness of about 5 nm due to the implantation of nitrogen. This paper is suitable for China National Standard (CNS) A4 Specification (210 X 297 mm) Printed by A4S5 4 4 A7 _ B7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (,.) (Figure 2). Then return to Si02 ( back) Etching about 50 nm deep, exposing the polycrystalline silicon Y 2 in the notch V and exposing these portions of the isolation region I 1 on the second side F 2 of the notch V and adjoining this isolation region I 1 These portions on the second side F 2 of the notch V are removed (Figure 3) The removed part of the isolation region Π is replaced by polycrystalline silicon doped in the same (insitu) process. The process is to deposit polycrystalline silicon with the same doping thickness of about 20 nm and then, for example, Wet etching is performed with KO Η. This doped polycrystalline silicon and the remaining 巳 -doped polycrystalline silicon Υ in the notch V together form a conductive structure L, which is adjacent to the first substrate 1. Then, in a vertical manner Oxygen is implanted so that the upper portion of the conductive structure L is doped at a doping substance concentration of about 10 I9 cm · 3. A varnish is then deposited and chemically-mechanically polished until the nitride layer N is exposed, so that the varnish is inserted into the recess V. An implantation is then performed with η-doped ions to generate the upper source / drain regions S / D0 of each transistor in the silicon island (Figure 4a). The upper source / drain regions S / Do are isolated from each other by an isolation trench S. The nitride layer N is then removed, for example, with phosphoric acid. For example, wet etching is performed on SiO 2 with hydrofluoric acid, so that these portions of the isolation structure 12 disposed on the second side surface F 2 of the recess D V are removed. The gate dielectric Gd 'which generates a transistor by thermal oxidation is disposed on the second side F 2 of the notch V and covers the conductive structure L. The gate dielectric Gd has -1 on the conductive structure L due to implantation with oxygen. 2- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ^ ----- „- --- Order --------- Line-S Please read the "i" on the back? Matters before filling out this page > A7 5 4 _B7 _ 5. Description of the invention (") It has a thickness of about 200nm And the thickness of this Gd on the second side F2 of the notch V is only 5 nm (Fig. 4a). When the gate dielectric < 3 d is generated, the doped substance is changed from the conductive structure L by the high temperature Diffusion into the first substrate 1 so as to generate the lower source / drain region S / Du adjacent to the second side F 2 of the notch V. In order to generate the word line W, the thickness to be deposited is approximately Polycrystalline silicon doped in the same situ at 100 nm is trapped in the notch V, and tungsten silicide is deposited on the polycrystalline silicon to a thickness of about 80 nm. In order to produce an isolation layer I 3, the thickness must be about 50 nm Silicon Nitride "The silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon oxide, silicon nitride, etc. are selectively selected by means of a strip-shaped varnish mask (the stripe is about 100 nm wide, extends parallel to the isolation trench and covers each notch V). The tungsten silicide and polycrystalline silicon are etched until the oxide layer 0 is exposed. Therefore, the word line W is generated from the tungsten silicide and the polycrystalline silicon (Figure 4a). On the upper source / drain region S / Do, the word line is formed. Some contact areas (not shown) are generated next to W. Then bit lines (not shown) are generated. These bit lines extend perpendicular to the word line W and are in contact with the upper source / drain area S / Do via the contact area. Connection. This part of the word line W (which is arranged in the notch V above the conductive structure L) is used as the gate electrode of the transistor. This part of the first substrate 1 (which is arranged in the lower source) Between the electrode / drain region s / D u and the upper source / drain region S / Do) is used as a transistor area. The conductive structure is used as the capacitor node. The buried layer P is used as the capacitor. Common electrode. -I 3-This paper size is applicable to National Standard (CNS) A4 (210 X 297 mm)-I— I n ϋ II n--1 —1 K--I n I- --I 5Ja-I----I—-I ϋ (Please read the notes on the back before filling in this hundred ') Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 485 4 4. A7 B7 5. Description of the invention (ο) The memory cell in the dram cell configuration produced by the above method contains a transistor and a capacitor connected to this transistor. {Please read the legal and legal matters on the back before (Fill in this page) In the second embodiment, a second substrate 2 composed of single crystal silicon is provided. As in the first embodiment, an oxide layer and a nitride layer (not shown) must be generated. A mouth V 'having a depth of about 50 nm is then generated in the substrate 2 and has a horizontal cross-section in the shape of a strip. These notches V 'therefore have the form of trenches and extend substantially parallel to each other. These notches V are about 100 nm wide and the distance between them is about 100 nm. Then, isolation regions Η 'are created. The process is to conformally deposit SiO 2 with a thickness of about 30 nm (Fig. 5). Similar to the first embodiment, each of the isolation regions 12 ', the conductive structure L_, the gate dielectric Gd1, the upper source / drain region S / D0 |, and the lower source / drain region S / Du_, The gate dielectric Gd ', the word line W', and the isolation layer 13 '. Capacitors (not shown) are generated above the word line W ', and these capacitors are connected to the source / drain regions S / Do_ above the transistor, respectively. The conductive structure L' is used as a bit line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the memory cells of the DRAM cell configuration generated by the above method include a transistor and a capacitor connected to this transistor, respectively. There are many variations to these embodiments, which are also within the scope of the invention. Especially for the above-mentioned layers, the sizes of the masks and notches can be adjusted according to individual needs. Gate Dielectric Growth on Conductive Structures by Oxygen-Oxygen Direct Implantation -14- This paper is sized for China National Standard (CNS) A4 (210 X 297 mm) 448544 A7 B7 V. Description of the invention ( Μ) (Please read the notes on the back before filling in this page ^ Part of the quality 'It is particularly thick, so the gate electrode can be capacitively decoupled from the conductive structure (C apac it i V e 1 y). Another method of this method is to deposit S i 0 2 ′ by HDP () method in a non-conformal manner after the conductive structure has been produced so as to deposit S i on the sides of each notch at about 20 nm. 0 2 and S i Ο 2 of approximately 60 nm deposited on the conductive structure. After removing the nitride layer, S i 0 2 is isotropically etched until such S i02 deposited by the HDP method is separated by each isolation structure. So far, a layer of S i 0 2 with a thickness of about 30 nm is therefore left on the conductive structure. These isolation structures are arranged on the second side of the notch as in the embodiments. The dielectric must be removed. The gate dielectric is generated by subsequent thermal oxidation and due to S i 0 2 (It is arranged on the conductive structure) and only covers a part of the second side of the notch. Therefore, the vertical implantation process of oxygen can be omitted. The symbol of the printed symbol I of the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs I 2 ... substrate F ... surface Fl, F2 ... side Gd, Gd1 ... intermediate dielectric h ... height II, II '... isolation area 12, T21 ... isolation structure 13, [3' ... isolation layer Kd ··· capacitor dielectric Electrical properties L, L '··· Conductive structure The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 448544 A7 __B7_ V. Description of the invention (i4) N ... nitride layer 0, 0' ... oxide layer P ... buried layer r], r 2 ... implantation direction S ... isolation trenches S / Do, S / Du, S / Do1, S / Du "... source / drain regions V, V, ... Notch w, W1 ... Character line Y 1, Y2 ... Polycrystalline silicon I ί ---- r ---- Order --------- line (Please read the precautions on the back before filling in this Page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm)