479314 經濟部智慧財產局員工消費合作社印製 A7 B7__ 五、發明說明（/ ) 發明背景 1 .技術領域 本發明傜關於一種半導體裝置，尤其是具有V型槽底部 之埋入式位元線，用以增加位元線的尺寸，但又不會增加 相鄰位元線之間的磁化率。 2 .相關技術説明 如習知之技術，半導體設計者和製造者曽經有一難題， 就是要減少半導體裝置的尺寸，但又要增加裝置的組件密 度。該半導體裝置又必需至少要保持上一代裝置的性能〇 具有較小單胞尺寸之高密度半導體記億體晶片已被製 造出來。例如，已被製造之唯讀記億體單胞具有僅2F2之 佈局面積，其中F為給定技術之最小特徵尺寸。具有小待 歡尺寸之記億體單胞經常採用垂直排列的組件以節省佈 局面積。例如，位元線可埋在位於垂直電晶體和儲存節點 下方之基板中。 參考第1圖，其圖示一唯讀記億體裝置（ROM)IG。R0M10 包含形成在淺矩形橫截面積溝渠1 4之中且沿著形成之埋 入式位元線1 2。上位元線1 6也以相同方式形成在基板2 0 的表面。位元線1 2和1 6鍍著一氣化物2 2，使位元線1 2和1 6 與形成在基板20之上和溝渠14之中的字元線24絶緣。當 活化時，字元線2 4致能毗鄰溝渠1 4側壁形成的電晶體通道 2 8。位元線1 2之部分1 8俗擴散進入基板2 0。部分1 8必須透 過位元線1 2充分提供足夠的傳導。在減少特徵尺寸方面， 會有問題發生。在溝渠1 4底部之擴散的位元線1 2可縮短 相鄰位元線12的距離。二擇其一地，可形成更窄尺寸之位 -3 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） L------------____ (請先閱讀背面之注意事項再填寫本頁) 訂---------線—— 479314 A7 B7 五、發明說明（> ) 元線1 2 ;但是，此會對裝置性能造成負面的衝擊。 位元線1 2和1 6係利用離子佈植而同時形成，而溝渠側 壁則用間隔層（未圖示）保護。該間隔層和後續佈植摻雜 物橫向擴散之厚度決定位元線1 2的電性活動寬度。若間 隔層太薄，會發生尺寸非常小的困難。換言之，若間隔層 太薄，位元線1 2會變的比較寬，且相鄰位元線1 2之間距 離縮短的可能性會增加。間隔層變寬會減少位元線1 2的 寬度，因此會增加電阻而超過可接受的程度。藉由製造較 厚的位元線，以減少位元線電阻也很困難，因爲每增加厚 度，就會減少垂直電晶體之通道2 8的通道長度。 因此，需要有一種裝置和方法，一種用以形成足夠寬的 位元線，但又不會增加相鄰位元線之間電位的方法。 發明總沭 含 包 置 裝 體 導 半 明 發 本 據 根 此 而’含 伸包 延都 向渠 方溝 一 個 第每 往。 渠面 溝表 〇 上 板的 具第 咅 底 基板面 之基表 中行底 其平的 在上部 成本底 形基此 渠向且 溝方而 有一 ’ 溝度 跟寬 係效 部有 底的 之線 成址 形定 該得 一 〇 值 列成 fch g形 向面 橫表 作底 面鄰 表毗 上線 的址 板定 基。 八、、 曷 對相 相渠 (請先閱讀背面之注意事項再填寫本頁) ··___ 訂---------線！ 經濟部智慧財產局員工消費合作社印製 渠 溝 於 大 離 距 此 且 而 離 距 面 表 底 的 間 之 壁 側 渠 溝。 著度 沿寬 爲的 板 中基 例。 施體 實憶 _ 記 另讀 在唯 爲 最 面 表 底 是 好 最 可露 置曝 裝含 體包 導面 半表 。 底 的而 V®板’ V基 是晶 好矽 r— I I I I I I . 的倍 面 之 中 其 比的 可線 度元 寬位 效和 有線 的元 線字 址含 定包 。可 線 址 定 約 大 度 寬 渠 溝 本 據 根 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^/9314 A7479314 Printed by A7 B7__ in the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics 5. Description of the Invention (/) Background of the Invention 1. Technical Field The present invention relates to a semiconductor device, especially a buried bit line with a V-groove bottom. In order to increase the size of the bit lines, but without increasing the magnetic susceptibility between adjacent bit lines. 2. Description of Related Technology As is known in the art, semiconductor designers and manufacturers have a problem that is to reduce the size of a semiconductor device, but to increase the density of the device components. The semiconductor device must at least maintain the performance of the previous generation device. A high density semiconductor memory chip with a small cell size has been manufactured. For example, the read-only record billion cells that have been manufactured have a layout area of only 2F2, where F is the minimum feature size for a given technology. Monolithic cells with small size are often equipped with vertically arranged components to save layout area. For example, bit lines can be buried in a substrate under the vertical transistors and storage nodes. Referring to FIG. 1, it illustrates a read-only memory device (ROM) IG. R0M10 includes a buried rectangular bit line 12 formed along a shallow rectangular cross-sectional area trench 14. The upper bit line 16 is also formed on the surface of the substrate 20 in the same manner. The bit lines 12 and 16 are plated with a vapor 22 to insulate the bit lines 12 and 16 from the word lines 24 formed on the substrate 20 and in the trenches 14. When activated, the word line 24 enables the transistor channel 28 formed adjacent to the sidewall of the trench 14. Part 18 of bit line 12 is diffused into substrate 20. Part 18 must provide sufficient conduction through bit line 12. Problems can occur in reducing feature size. The diffused bit lines 12 at the bottom of the trench 14 can shorten the distance between adjacent bit lines 12. Alternatively, it can form a narrower size -3-This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) L ------------____ ( Please read the precautions on the back before filling this page) Order --------- Line—— 479314 A7 B7 V. Description of the invention (>) Yuan line 1 2; However, this will cause negative performance to the device Shock. The bit lines 12 and 16 are formed by ion implantation at the same time, and the trench walls are protected by a spacer layer (not shown). The thickness of the lateral diffusion of the spacer layer and subsequent implanted dopants determines the width of the electrical activity of the bit line 12. If the compartment is too thin, difficulties of very small dimensions can occur. In other words, if the spacer layer is too thin, the bit lines 12 will become wider, and the possibility of shortening the distance between adjacent bit lines 12 will increase. The widening of the spacer layer reduces the width of the bit line 12 and therefore increases the resistance beyond an acceptable level. It is also difficult to reduce the resistance of the bit line by manufacturing a thicker bit line, because each increase in thickness reduces the channel length of the channel 28 of the vertical transistor. Therefore, there is a need for an apparatus and method for forming a bit line that is sufficiently wide without increasing the potential between adjacent bit lines. According to the invention, the package guide containing the package is semi-transparent, and according to this, the package extension and extension are all directed to the channel and the ditch. Channel surface and groove table 〇 The upper plate with the first base plate surface in the base table is flat at the bottom of the upper cost base and the channel is square and there is a 'groove degree with the width of the bottom line The shape of the address should be set to a value of 10 to form a fch g-shaped horizontal cross-table as the base of the address plate adjacent to the line on the adjacent table. Eight, 曷 Opposite phase phase channel (Please read the precautions on the back before filling this page) ·· ___ Order --------- line! The consumer co-operatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the trenches on the wall side of the trenches at a large distance from the bottom of the surface. The basic example of the slab with a width along the slope. Donor's memory _ Note Another reading is that the bottom of the top surface is the best and most exposed, and the half surface of the package surface is included. The bottom of the V® board ’s V-base is the multiples of crystallized silicon r— I I I I I I. The ratio of the available elements is wide-bandwidth, wide-band effect, and the wired element-line word address contains the fixed package. The address can be set to a large and wide trench. The paper size is based on the Chinese National Standard (CNS) A4 (210 X 297 mm) ^ / 9314 A7
經濟部智慧財產局員工消費合作社印製 五、發明說明（4 ) 發明，形成埋入參元線之方法，其步驟包含提供一具有 溝渠形成在其中之基板。溝渠往第一方向延伸一段距離， 而此第一方向平行基板的上表面。該步驟還包含在溝渠 側壁上形成間隔餍，蝕刻溝渠的底表面，將底表面延伸進 入V型凹槽，及摻雜毗鄰V型凹槽之基板，使形成位元線。 在另一種方法中，其步驟可包含將基板退火，以擴散和 活化位元線。將基板退火，以擴散和活化位元線之步'驟， 可包含採用快速熱氧化退火技術，將基板退火。該方法之 步驟還包含移除間隔層，和在溝渠側壁上形成閘極氧化 物。該方法之步驟也•可包含摻雜H比鄰溝 '渠間之上表面的 基板，以形成上位元線。該方法之步驟可包含在上位元線 之上和tt鄰v型凹槽、之位元線上，形成一介電質層。 該方法之步驟還包含在溝渠之中和在基板之上，形成字 元線。蝕刻溝渠底表面之步驟可包含非等向性濕鈾刻底 表面，以形成V型凹槽。非等向性濕蝕刻底·表面，以形成 V型凹槽之步驟可包含用氫氧化鉀作非等向性濕鈾刻。 在唯讀記億體中，形成埋入式位元線之方法，其步驟包 含提供一具有溝渠形成在其中之矽基板。溝渠在第一方 向延伸一段距離，而此第一方向平行基板的上表面。基板 的上表面係在（1 〇 〇 )面。該步驟還包含在溝渠側壁上形成 間隔層，及非等向性濕蝕刻溝渠的底表面，將底表面延伸 進入v型凹槽，使得底表面的表面係在（111)面。摻雜毗 鄰v型凹槽之基板和基板的上表面，以分別形成下位元線 和上位元線。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ·---- 訂---------線丨· 479314 A7 -----—_ B7 五、發明說明（4 ) (請先閱讀背面之注意事項再填寫本頁) 在另一種方法中，其步驟可包含將基板退火（如採用快 速熱氧化退火技術），以擴散和活化上和下位元線。該步 驟也可包含移除間隔層，和在溝渠側壁上形成閘極氧化 物。該方法可包含用氫氧化鉀非等向性濕蝕刻。 由下面參考相關圖式而詳細說明的實施例，本發明的這 些和其他的目的，特徵和優點將會更淸楚。 圖式簡沭 本發明將參考下面的圖式而詳細說明優選實施例於後， 其中： 第1圖爲根據習知技術之唯讀記憶體的橫截面圖； 第2圖爲根據本發明，製造具有形成在基板中之溝渠的 部分半導體裝置橫截预圖； 第3圖爲根據本發明，在第2圖之半導體裝置的溝渠側 面上，形成間隔層之橫截面圖； 線！ 第4圖爲根據本發明，在第3圖之半導體裝.置的基板中， 形成V型槽或V型凹槽之橫截面圖； 第5圖爲根據本發明，將第4圖之半導體裝置佈植摻雜 物，用以形成埋入式位元線之橫截面圖； 經濟部智慧財產局員工消費合作社印製 第6圖爲根據本發明，將第5圖之半導體裝置所佈植的 摻雜物，擴散和活化在基板中之橫截面圖；及 第7圖爲根據本發明，將第6圖之半導體裝置，在溝渠 中沈積字元線之橫截面圖。 優選實施例詳沭 本發明提供一種增加埋入式定址線，如位元線，之有效 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） 4 A7B7 五、發明說明（Γ) 寬度的方法和設備。形成之埋入式位元線係爲V槽橫截 ®形狀°此不僅增加有效寬度，也保持相鄰位元線之間的 分隔°根據本發明，位元線溝渠之間的距離可以縮減到小 於習知技術可達到之尺寸。現在將根據埋入式位元線更 詳細的說明本發明之製程和結構。 現在詳細參考圖式，其中在所有的幾個圖中，相同的參 考數字表示相似的或相同的組件，從第2圖開始，其圖示 部分製造的半導體裝置100。裝置100包含基板1〇2,雖 然可以採用其他的基板材料，如絕緣體上矽，但以單晶矽 基板較佳。將基板1 0 2製作圖案和蝕刻，以形成溝渠1〇 4。 在優選實施例中，可在基板1 〇 2的表面上，沈積一種或更 多的遮罩層106。遮、罩層1〇6可包含氮化物化合物，或其 他提供選擇蝕刻基板1 〇 2之材料的遮罩材料。製作遮罩 層106之圖案，以移除溝渠104位置之部分遮罩層106。 遮罩層1 0 6可用標準的微影製程技術製作圖案。遮罩層 1 06之功能係當作形成溝渠1 〇4之蝕刻遮罩。形成溝渠1 〇4， 可用非等向性蝕刻製程，如反應離子蝕刻。 參考第3圖，在溝渠1 〇 4的側壁1 1 0上，形成間隔層 1 0 8。間隔層1 0 8宜由和遮罩層1 〇 6相同的材料形成。間 隔層1 08係用抗蝕刻材料，共形鍍著遮罩層1 06的其餘部 分，溝渠1 0 4的側壁1 1 0和底部1 1 2而形成的，此將說明 於后。在優選實施例中，間隔層1 0 8係由具有足夠厚度之 氮化物形成的，以抵抗後面的蝕刻製程。 蝕刻製程，如反應離子蝕刻，係用以栘除溝渠1 04之底 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) I · · ϋ« ϋ Hi n .^1 ϋ a βϋ Bi 1 _1 線— · 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 479314 A7 B7__ 五、發明說明（t ) 部1 1 2的氮化物（或其他沈積的材料）。此蝕刻製程像選 擇基板102執行，而留下溝渠102中曝露的基板表面116。 部分的間隔層1 〇 8也可藉由此蝕刻製程移除，因此間隔層 1 〇 8的厚度應該要夠厚，才能抵抗此和其他的蝕刻製程。 參考第4圖，將曝露的基板表面1 1 6 (第3圖）曝露在高 非等向蝕刻製程下。對於單晶矽基板1 〇 2而言，非等向蝕 刻顯示跟晶體方向有關，而完成橫向排列的溝渠，如V型 槽溝渠118。V型槽溝渠118像形成在矽基板之中。若基 板102的表面120為具有（110)面方向之溝渠的（100)表 面，則根據本發明之非等向蝕刻將曝露形成對稱V型槽溝 渠之（111)表面（此為矽晶密度最高的面）。非等向蝕刻可 使用濕蝕刻執行，如使用氫氧化鉀。用其他的蝕刻製程可 完成其他的橫截面形狀。V型槽溝渠118之表面12 2會呈現 其他的橫截面形狀，如半圓形，多重V型（W型）或非對稱 V型槽。帶優選實施例中，表面122僳相對於表面12 0作橫 向排列。根據本發明，可藉由增加形成在表面1 2 2附近之 定址線（如位元線或字元線）的有效寬度，而達到性能的提 升。對具有（111)面曝露的矽而言，V型槽溝渠11 8産生約71° 之角度b。用其他的蝕刻製程和基板材料，可具有其他的 角度。 參考第5圖，最好利用蝕刻製程移除遮罩層1G6,以露出 基板1G2的表面120。部分的間隔層1G 8仍然沿著溝渠104 的側壁1 1 0，以免側壁1 1 0受到離子佈植。引入摻雜物且 將其植入基板102曝露的表面。基板曝露的表面包含表 面120和122。摻雜物偽藉由佈植製程植入，如離子佈植 -8 一 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Γ m i^i ·ϋ ^^1 ϋ ϋ— I 1_1 11 1 ϋ ·ϋ I I ϋ ϋ_ι 1_1 ^ ^ I ^^1 tmmm n ϋ 一口 (請先閱讀背面之注意事項再填寫本頁) 線丨·· ^/9314 五、 經濟部智慧財產局員工消費合作社印製 發明說明（7 製程。 參考第6圖，如參考第5圖和相關之說明，將佈植之摻 進物進一步擴散進入基板102,以形成上位元線ι26和下 位兀線1 2 8。上位兀線1 2 6和下位元線1 2 8的擴散和活 化宜用退火製程實行，且以快速熱氧化退火製程爲佳。 參考第7圖，自側壁1 1 〇移除間隔層丨〇 8，以曝露溝渠1 〇 4 的垂直表面。在側壁1 1 Q之上形成一^閘極氧化物1 3〇。 在位兀線1 2 6和1 2 8之上，形成一介電質層1 3 2 (以氧化 物爲佳），使上位元線126和下位元線128與沈積在溝渠 1 0 4 (和V型槽溝渠1 1 8 )之中和基板1 〇 2之上的導電材料 1 3 4電性絕緣。導電材料1 3 4形成字元線1 3 6。字元線1 3 6 和上位元線1 2 6 /下位元線丨2 8係透過形成在溝渠1 〇 4側 壁110之垂直通道138耦合。導電材料134可包含金屬， 多晶矽或其他那些習知技術中所知之材料。導電通道1 3 8 可包含調變摻雜，以提供已形成之垂直電晶體給定的臨限 電壓。 本發明已根據唯讀記憶體裝置（ROM )說明。尤其，其係 藉由不同的通道摻雜，調變垂直電晶體臨限電壓而規劃之 ROM。但是，本發明適用於各種半導體裝置。例如，記憶體 裝置，如利用本發明而具有埋入式位元線或字元線之動態 隨機存取記憶體（DRAM )裝置。本發明之優選實施例增加 下位元線1 2 6的有效寬度約1 . 7 3倍。其他的倍率也可達 成。1 · 7 3倍可使位元線之間的距離縮小很多，而且如此 可以提供一種致能更高密度記憶體單胞之方式。此外，在 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） l· I ---------------- 丨—訂--！丨！丨-線|-^||^ (請先閱讀背面之注意事項再填寫本頁) 479314 A7 B7 五、發明說明（，） 各位元線側面上之擴散部分可以減少很多，以消除或防止 任何相鄰位元線有彼此相互短路之風險。 本發明已說明具有改良埋入式位元線之半導體裝置的 優選實施例（其只是用以說明，但並侷限於此），注意，熟悉 技術之人士可依上述之技術作修正或變化。因此，應當明 瞭改變本發明之特定實施例，其仍在本發明所附申請專利 範圍的範圍和精神之中。因此本發明已應專利法之特殊 要求而詳細說明，所附之申請專利範圍希望受到專利權的 保護。 符號說明 !〇...唯讀記憶體裝置 1 2 ...埋入式位元線 1 4 ...溝渠 1 6 ...上位元線 1 8 ...部分 20 ...基板 2 2 ...氧化物 24...字元線 (請先閱讀背面之注意事項再填寫本頁) --------訂·------11^^ I. 道 通 經濟部智慧財產局員工消費合作社印製 置 裝 體 層層 導板渠罩隔 半基溝遮間 度適Θ國國家標準（CNS)A4規格（210 X 297公釐） 479314 A7 B7 五、發明說明（9 ) ο 2 6 8 02680246 22223333 8 3 渠 物 面溝 線線化層料 表槽 元元氧質材線 壁部板^j面面位位極電電元道 側底基 V 表表上下閘介導字通 (請先閱讀背面之注意事項再填寫本頁) 訂---------線i-^91. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297.公釐）Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (4) The method of inventing the method of burying the element line includes the steps of providing a substrate with a trench formed therein. The trench extends a distance toward the first direction, and the first direction is parallel to the upper surface of the substrate. This step also includes forming a spacer on the sidewall of the trench, etching the bottom surface of the trench, extending the bottom surface into the V-shaped groove, and doping the substrate adjacent to the V-shaped groove to form a bit line. In another method, the steps may include annealing the substrate to diffuse and activate the bit lines. The step of annealing the substrate to diffuse and activate the bit lines may include annealing the substrate using a rapid thermal oxidation annealing technique. The method further includes removing the spacer layer and forming a gate oxide on the trench sidewall. The steps of the method may also include doping a substrate on the upper surface of the H-by-ditch trench to form upper bit lines. The steps of the method may include forming a dielectric layer on the upper bit line and on the bit line adjacent to the v-shaped groove on the tt. The method also includes forming word lines in the trenches and above the substrate. The step of etching the bottom surface of the trench may include etching the bottom surface of the anisotropic wet uranium to form a V-shaped groove. The step of anisotropically wet-etching the bottom and surface to form a V-shaped groove may include anisotropic wet uranium etching using potassium hydroxide. In a read-only memory, a method of forming an embedded bit line includes the steps of providing a silicon substrate having a trench formed therein. The trench extends a distance in the first direction, and the first direction is parallel to the upper surface of the substrate. The upper surface of the substrate is on the (100) plane. This step also includes forming a spacer layer on the side wall of the trench and anisotropically wet-etching the bottom surface of the trench, extending the bottom surface into the v-shaped groove, so that the surface of the bottom surface is tied to the (111) plane. The substrate adjacent to the v-shaped groove and the upper surface of the substrate are doped to form lower bit lines and upper bit lines, respectively. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) · ---- Order --------- Line 丨 · 479314 A7 -----—_ B7 V. Description of the Invention (4) (Please read the notes on the back before filling this page) In another method, the steps may include annealing the substrate (such as using rapid thermal oxidation annealing) Technology) to diffuse and activate upper and lower bit lines. This step may also include removing the spacer layer and forming gate oxides on the trench sidewalls. The method may include anisotropic wet etching with potassium hydroxide. These and other objects, features, and advantages of the present invention will be made clearer by the embodiments described in detail below with reference to the related drawings. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described in detail with reference to the following preferred embodiments with reference to the following drawings, in which: FIG. 1 is a cross-sectional view of a read-only memory according to conventional technology; FIG. A cross-sectional plan view of a portion of a semiconductor device having a trench formed in a substrate; FIG. 3 is a cross-sectional view of a spacer layer formed on the side of the trench of the semiconductor device of FIG. 2 according to the present invention; FIG. 4 is a cross-sectional view of a V-shaped groove or a V-shaped groove formed in the substrate of the semiconductor device of FIG. 3 according to the present invention; FIG. 5 is a view of the semiconductor device of FIG. 4 according to the present invention. A dopant is implanted to form a cross-sectional view of an embedded bit line; printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. A cross-sectional view of debris, diffusion, and activation in a substrate; and FIG. 7 is a cross-sectional view of a word line in which the semiconductor device of FIG. 6 is deposited in a trench according to the present invention. The preferred embodiment is detailed. The present invention provides an embedded address line, such as a bit line, which is effective. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297). A7B7 V. Description of the invention (Γ ) Width method and equipment. The formed buried bit lines are V-groove cross-sections. This not only increases the effective width, but also maintains the separation between adjacent bit lines. According to the present invention, the distance between the bit line trenches can be reduced to Less than the size achievable by conventional techniques. The process and structure of the present invention will now be described in more detail based on embedded bit lines. Reference will now be made in detail to the drawings, wherein in all of the drawings, the same reference numerals indicate similar or identical components, starting from FIG. 2, which illustrates a partially manufactured semiconductor device 100. FIG. The device 100 includes a substrate 102. Although other substrate materials such as silicon on insulator can be used, a single crystal silicon substrate is preferred. The substrate 10 is patterned and etched to form a trench 104. In a preferred embodiment, one or more masking layers 106 may be deposited on the surface of the substrate 102. The masking and masking layer 10 may include a nitride compound, or another masking material that provides a material for selective etching of the substrate 102. The mask layer 106 is patterned to remove a part of the mask layer 106 at the position of the trench 104. The mask layer 106 can be patterned using standard lithographic process techniques. The mask layer 106 functions as an etch mask to form the trench 104. The trench 104 is formed, and an anisotropic etching process can be used, such as reactive ion etching. Referring to FIG. 3, a spacer layer 108 is formed on the sidewall 1 10 of the trench 104. The spacer layer 108 is preferably formed of the same material as the mask layer 106. The spacer layer 1 08 is formed of an anti-etching material, and is conformally plated with the rest of the masking layer 106, the side walls 1 10 of the trench 10, and the bottom 1 12, which will be described later. In a preferred embodiment, the spacer layer 108 is formed of a nitride having a sufficient thickness to resist subsequent etching processes. Etching process, such as reactive ion etching, is used to remove the bottom of the trench. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) I · · Ϋ ϋ ϋ Hi n. ^ 1 ϋ a βϋ Bi 1 _1 line — · Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economics 479314 A7 B7__ 5. Department of Invention (t) 1 1 2 of nitride (or other deposited material). This etching process is performed by selecting the substrate 102, leaving the substrate surface 116 exposed in the trench 102. Part of the spacer layer 108 can also be removed by this etching process, so the thickness of the spacer layer 108 should be thick enough to resist this and other etching processes. Referring to Fig. 4, the exposed substrate surface 1 1 6 (Fig. 3) is exposed to a high anisotropic etching process. For the single crystal silicon substrate 102, the anisotropic etching shows that it is related to the crystal direction, and the laterally arranged trenches, such as the V-shaped trenches 118, are completed. The V-shaped trenches 118 are formed in a silicon substrate. If the surface 120 of the substrate 102 is a (100) surface having trenches in a (110) plane direction, the non-isotropic etching according to the present invention will expose the (111) surface of a symmetrical V-shaped trench (this is the highest density of silicon crystals) Face). Anisotropic etching can be performed using wet etching, such as using potassium hydroxide. Other etching processes can be used to complete other cross-sectional shapes. The surface 12 2 of the V-groove trench 118 may present other cross-sectional shapes, such as semi-circular, multiple V-shaped (W-shaped) or asymmetric V-shaped grooves. In a preferred embodiment of the belt, the surface 122 'is arranged transversely with respect to the surface 120. According to the present invention, performance can be improved by increasing the effective width of an address line (such as a bit line or a word line) formed near the surface 1 2 2. For silicon with (111) plane exposure, the V-shaped trenches 118 produce an angle b of about 71 °. Other etch processes and substrate materials can have other angles. Referring to FIG. 5, it is preferable to remove the mask layer 1G6 by an etching process to expose the surface 120 of the substrate 1G2. Part of the spacer layer 1G 8 is still along the side wall 1 1 0 of the trench 104 to prevent the side wall 1 10 from being ion-implanted. Dopants are introduced and implanted on the exposed surface of the substrate 102. The exposed surface of the substrate includes surfaces 120 and 122. The dopants are implanted through the implantation process, such as ion implantation-8. A paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) Γ mi ^ i · ϋ ^^ 1 ϋ ϋ— I 1_1 11 1 ϋ · ϋ II ϋ ϋ_ι 1_1 ^ ^ I ^^ 1 tmmm n ϋ sip (please read the precautions on the back before filling out this page) line 丨 · ^ / 9314 V. Consumption by the Intellectual Property Bureau of the Ministry of Economic Affairs The cooperative prints a description of the invention (7 processes. Referring to FIG. 6, if referring to FIG. 5 and related descriptions, the implanted material is further diffused into the substrate 102 to form upper bit lines 26 and lower bit lines 1 2 8. The diffusion and activation of the upper line 1 2 6 and the lower bit line 1 2 8 should be performed by an annealing process, and a rapid thermal oxidation annealing process is preferred. Referring to FIG. 7, the spacer layer is removed from the sidewall 1 1 0. 8 To expose the vertical surface of the trench 104. A gate oxide 1 30 is formed on the side wall 1 1 Q. A dielectric layer 1 is formed on the bit lines 1 2 6 and 1 2 8 3 2 (preferably oxide), so that the upper bit line 126 and the lower bit line 128 and Shen are accumulated in the trench 1 0 4 (and the V-shaped trench 1 1 8) and The conductive material 1 3 4 on the substrate 1 0 2 is electrically insulated. The conductive material 1 3 4 forms a character line 1 3 6. The character line 1 3 6 and the upper bit line 1 2 6 / lower bit line 丨 2 8 series Coupling is through a vertical channel 138 formed in the trench 104 sidewall 110. The conductive material 134 may include metal, polycrystalline silicon, or other materials known in the art. The conductive channel 1 3 8 may include modulation doping to provide The threshold voltage given by the formed vertical transistor is described in the present invention according to a read-only memory device (ROM). In particular, it is a ROM planned by adjusting the threshold voltage of the vertical transistor by doping different channels. However, the present invention is applicable to various semiconductor devices. For example, a memory device, such as a dynamic random access memory (DRAM) device having embedded bit lines or word lines using the present invention. A preferred implementation of the present invention For example, increasing the effective width of the lower bit line 1 2 6 is about 1.73 times. Other magnifications can also be achieved. 1 · 73 times can make the distance between the bit lines much smaller, and this can provide a more effective High density memory single cell way. This In addition, the Chinese national standard (CNS) A4 specification (210 X 297 mm) applies to this paper size l · I ---------------- 丨 —Order--! 丨! 丨-线 |-^ || ^ (Please read the precautions on the back before filling this page) 479314 A7 B7 V. Description of the invention (,) The diffusion part on the side of each element line can be reduced a lot to eliminate or prevent any adjacent The bit lines run the risk of shorting to each other. The present invention has described a preferred embodiment of a semiconductor device having an improved embedded bit line (which is only used for illustration, but is not limited thereto). Note that those skilled in the art can make corrections or changes according to the above-mentioned technology. Therefore, it should be clear that the specific embodiment of the present invention is changed, which is still within the scope and spirit of the scope of the patent application attached to the present invention. Therefore, the present invention has been described in detail in accordance with the special requirements of the patent law. The scope of the attached patent application is expected to be protected by patent rights. Explanation of symbols! 0 ... Read-only memory device 1 2 ... Built-in bit line 1 4 ... Ditch 1 6 ... High bit line 1 8 ... Part 20 ... Substrate 2 2 ... Oxide 24 ... Character line (Please read the precautions on the back before filling this page) -------- Order · ------ 11 ^^ I. Ministry of Economic Affairs The Intellectual Property Bureau employee consumer cooperative printed the installation body layer guide plate canal cover half semi-ditch ditch cover θ national national standard (CNS) A4 specifications (210 X 297 mm) 479314 A7 B7 V. Description of the invention (9) ο 2 6 8 02680246 22223333 8 3 canal surface groove line linearized layer table surface element element oxygen material line wall plate ^ j plane surface position pole electric element side side base V table meter upper and lower gates mediate word communication (Please read the precautions on the back before filling out this page) Order --------- line i- ^ 91. Printed on paper standards of the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, China Paper Standard (CNS) A4 Specifications (210 X 297. mm)