WO2001017022A1

WO2001017022A1 - Semiconductor device with buried bitlines

Info

Publication number: WO2001017022A1
Application number: PCT/US2000/023341
Authority: WO
Inventors: Ulrich Zimmermann
Original assignee: Infineon Technologies North America Corp.
Priority date: 1999-08-27
Filing date: 2000-08-24
Publication date: 2001-03-08
Also published as: TW479314B

Abstract

A semiconductor device (100), in accordance with the present invention, includes a substrate (102) having trenches (104) formed therein. The trenches extend in a first direction, and the first direction is substantially parallel to a top surface of the substrate. Each trench includes a bottom portion (118), and the bottom portion has a bottom surface (122) transversely disposed relative to the top surface of the substrate. The bottom portion is formed in communication with the trench. An addressing line (128) is formed adjacent to the bottom surface such that an effective width of the addressing line is a distance along the bottom surface between side walls of the trench and the distance is greater than a width of the trench. A method for fabricating the semiconductor device with V-shaped notches is also disclosed.

Description

SEMICONDUCTOR DEVICE WITH BURIED BITLINES

BACKGROUND

1. Technical Field

This disclosure relates to semiconductor devices and more particularly, to a buried bitline having a V- grooved lower portion for increasing bitline size without increasing the susceptibility of shorting between adjacent bitlines .

2. Description of the Related Art

As is known in the art, an ever present challenge for semiconductor designers and manufacturers is to reduce the size of semiconductor devices while increasing the component density on the device. The semiconductor devices are also needed to at least maintain the performance of previous generations.

High density semiconductor memory chips are being manufactured with smaller cell sizes. For example, read only memory cells are being fabricated having a layout area of only 2F² where F is a minimum feature size for a given technology. Memory cells having small feature sizes often employ vertically disposed components to conserve layout area. For example, bitlines may be buried in a substrate below vertical transistors and storage nodes.

Referring to FIG. 1, a read only memory device (ROM) 10 is shown. ROM 10 includes buried bitlines 12 which are formed within and along shallow rectangular cross- section trenches 14. Upper bitlines 16 are also formed in a same manner at the surface of a substrate 20. Bitlines 12 and 16 are coated with an oxide 22 to isolate bitlines 12 and 16 from a wordline 24 formed over substrate 20 and in trenches 14. When activated, wordline 24 enables a transistor channel 28 formed adjacent to sidewalls of trench 14. A portion 18 of bitlines 12 is diffused into a substrate 20. Portion 18 must be sufficient to provide ample conduction through bitline 12. In reducing feature size, a problem arises. The diffused bitlines 12 at the bottom of trenches 14 may be shorted to adjacent bitlines 12. Alternately, bitlines 12 may be formed with more narrow dimensions; however, this negatively impacts performance.

The bitlines 12 and 16 are formed simultaneously by ion implantation while trench sidewalls are protected with a spacer (not shown) . The thickness of the spacer together with subsequent lateral diffusion of the implanted dopants determines the electrically active width of bitline 12. Difficulty arises for very small dimensions if the spacer is too thin. That is, if the spacer is too thin, bitline 12 becomes wider and the probability of a short between adjacent bitlines 12 is increased. Widening the spacer reduces the width of bitline 12 thus increasing resistance beyond acceptable levels. Reducing the bitline resistance by making the bitline thicker is also difficult since every increase in thickness reduces the channel length of channel 28 for a vertical transistor.

Therefore, a need exists for a device and method for forming sufficiently wide bitlines without increasing the potential for shorting between adjacent bitlines.

SUMMARY OF THE INVENTION

A semiconductor device, in accordance with the present invention, includes a substrate having trenches formed therein. The trenches extend in a first direction, and the first direction is substantially parallel to a top surface of the substrate. Each trench includes a bottom portion, and the bottom portion has a bottom surface transversely disposed relative to the top surface of the substrate. The bottom portion is formed in communication with the trench. An addressing line is formed adjacent to the bottom surface such that an effective width of the addressing line is a distance along the bottom surface between side walls of the trench and the distance is greater than a width of the trench.

In alternate embodiments, the bottom surface is preferably V-shaped. The semiconductor device may be a read only memory. The substrate is preferably a silicon crystal substrate and the bottom surface includes an exposed (111) plane. The effective width of the addressing line may be greater than about 1.7 times the width of the trench. The addressing line may include one of a wordline and a bitline.

A method for forming buried bitlines, in accordance with the present invention, includes the steps of providing a substrate having trenches formed therein. The trenches extend a distance in a first direction, and the first direction is parallel to a top surface of the substrate. The steps of forming spacers on side walls of the trenches, etching a bottom surface of the trenches to extend the bottom surface into a V-shaped notch and doping the substrate adjacent to the V-shaped notch to form a bitline are also included.

In alternate methods, the step of annealing the substrate to diffuse and activate the bitline may be included. The step of annealing the substrate to diffuse and activate the bitline may include annealing the substrate by employing a rapid thermal oxidation anneal. The method may further include the steps of removing the spacers and forming a gate oxide on the side walls of the trenches. The method may also include the step of doping the substrate adjacent to a top surface between the trenches to form upper bitlines. The method may include the step of forming a dielectric layer on the upper bitlines and the bitlines adjacent to the V-shaped notch.

The method may further include the step of forming a word line in the trenches and over the substrate. The step of etching a bottom surface of the trenches may include the step of anisotropically wet etching the bottom surface to form the V-shaped notch. The step of anisotropically wet etching the bottom surface to form the V-shaped notch may include anisotropically wet etching with potassium hydroxide .

A method for forming buried bitlines in read only memories includes the steps of providing a silicon substrate having trenches formed therein. The trenches extend a distance in a first direction, and the first direction is parallel to a top surface of the substrate. The top surface of the substrate is disposed in a (100) plane. The steps of forming spacers on side walls of the trenches, and anisotropically wet etching a bottom surface of the trenches to extend the bottom surface into a V-shaped notch such that surfaces of the bottom surface are disposed in (111) planes are also included. The substrate is doped adjacent to the V-shaped notch and the top surface of the substrate to form lower bitlines and upper bitlines, respectively.

In alternate methods, the step of annealing (e.g., by employing a rapid thermal oxidation anneal) the substrate to diffuse and activate the upper and lower bitlines may be included. The steps of removing the spacers and forming a gate oxide on the side walls of the trenches may also be included. The method may include anisotropically wet etching with potassium hydroxide.

These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings .

BRIEF DESCRIPTION OF DRAWINGS

This disclosure will present in detail the following description of preferred embodiments with reference to the following figures wherein:

FIG. 1 is a cross-sectional view of a read only memory in accordance with the prior art ;

FIG. 2 is a cross-sectional view of a partially fabricated semiconductor device showing trenches formed in a substrate in accordance with the present invention;

FIG. 3 is a cross-sectional view of the semiconductor device of FIG. 2 showing trenches having spacers formed on the side walls in accordance with the present invention;

FIG. 4 is a cross-sectional view of the semiconductor device of FIG. 3 showing V-grooved or V-shaped notches formed in the substrate in accordance with the present invention;

FIG. 5 is a cross-sectional view of the semiconductor device of FIG. 4 showing implanted dopants for forming buried bitlines in accordance with the present invention;

FIG. 6 is a cross-sectional view of the semiconductor device of FIG. 5 showing implanted dopants diffused and activated in the substrate in accordance with the present invention; and

FIG. 7 is a cross-sectional view of the semiconductor device of FIG. 6 showing a wordline deposited in the trenches in accordance with the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention provides a method and apparatus for increasing the effective width of buried addressing lines, e.g., bitlines. The buried bitlines are formed in a V-groove cross-sectional shape. This not only increases the effective width but also preserves the separation between adjacent bitlines. In accordance with the present invention, the distance between bitline trenches may be reduced below the dimensions achievable in the prior art. The process and structure of the present invention will now be illustratively described in greater detail in terms of buried bitlines.

Referring now in specific detail to the drawings in which like reference numerals identify similar or identical elements throughout the several views, and initially to FIG. 2, a partially fabricated semiconductor device 100 is shown. Device 100 includes a substrate 102, preferably a monocrystalline silicon substrate although other substrate materials may be employed, for example silicon-on insulator. Substrate 102 is patterned and etched to form trenches 104. In a preferred embodiment, one or more mask layers 106 may be deposited on a surface of substrate 102. Mask layer 106 may include a nitride compound or other masking materials which provide an etching material selective to the material of substrate 102. Mask layer 106 is patterned to remove portions of mask layer 106 at locations for trenches 104. Mask layer 106 may be patterned using standard photolithographic techniques. Mask layer 106 functions as an etch mask to form trenches 104. An anisotropic etch process, such as reactive ion etching may be employed to form trenches 104.

Referring to FIG. 3, spacers 108 are formed on side walls 110 of trenches 104. Spacers 108 are preferably formed from a same material as mask layer 106. Spacers 108 are formed by conformally coating remaining portions of mask layer 106, sidewalls 110 and a bottom portion 112 of trench 104 with a material resistant to etching, as will be explained below. In a preferred embodiment, spacers 108 are formed from a nitride having a sufficient thickness to withstand the etching processes which follow.

An etching process, for example reactive ion etching, is employed to remove nitride (or other deposited material) from bottom portion 112 of trench 104. This etch process is performed selective to substrate 102 and leaves an exposed substrate surface 116 in trench 102. Portions of spacers 108 may also be removed by the etching process and therefore, the thickness of spacers 108 should be sufficient to withstand this and other etching processes .

Referring to FIG. 4, exposed substrate surface 116 (FIG. 3) is exposed to a high anisotropic etch process. For a monocrystalline silicon substrate 102, the anisotropic etch preferably displays a dependance on crystal orientation to achieve a transversely disposed trench for example, a V- grooved trench 118. V-grooved trench 118 is formed in silicon. If a surface 120 of substrate 102 is a (100) surface with trench orientation in a (110) plane, then, the anisotropic etch in accordance with the invention will expose (111) surfaces (which is the most dense plane of the silicon crystal) forming a symmetrically V-groove trench. The anisotropic etch may be performed using a wet etch, for example using potassium hydroxide. Other cross-sectional shapes may be achieved with other etching processes. Surface 122 of V-grooved trench 118 may take on other cross- sectional shapes, such as a semicircular shape, multiple V shapes (W shape) or an asymmetrical V-groove. In preferred embodiments, surfaces 122 are transversely disposed relative to surface 120. An increase in performance in accordance with the present invention is achieved by the increase in effective width of addressing lines (e.g., bitlines or wordlines) formed adjacent to surfaces 122. V-grooved trench 118, for silicon with (111) planes exposed, yields an angle b of about 7lE. Other angles may be achieved with other etch processes and substrate materials.

Referring to FIG. 5, mask layer 106 is removed, preferably by an etching process to expose surface 120 of substrate 102. Portions of spacers 108 remain along side walls 110 of trenches 104 to protect side walls 110 from ion implantation. Dopants are introduced and implanted in exposed surfaces of substrate 102. Exposed surfaces of substrate include surfaces 120 and 122. Dopants are implanted by an implantation process, such as an ion implantation process.

Referring to FIG. 6, dopants implanted as described with reference to FIG. 5 and the accompanying text, are diffused further into substrate 102 to form upper bitlines 126 and lower bitlines 128. Diffusion and activation of upper bitlines 126 and lower bitlines 128 is preferably performed by employing an anneal process, and preferably a rapid thermal oxidation anneal process. Referring to FIG. 7, spacers 108 are removed from side walls 110 to expose vertical surfaces of trench 104. A gate oxide 130 is formed on side walls 110. A dielectric layer 132 (preferably an oxide) is formed over bitlines 126 and 128 to electrically isolate upper bitlines 126 and lower bitlines 128 from a conductive material 134 deposited in trenches 104 (and V-grooved trenches 118) and on substrate 102. Conductive material 134 forms a wordline 136. Wordlines 136 and upper bitlines 126/lower bitlines 128 are coupled through vertical channels 138 formed in sidewalls 110 of trenches 104. Conductive material 134 may include a metal, polysilicon or other materials known to those skilled in the art. Conductive channels 138 may include modulated doping to provide a given threshold voltage for the vertical transistors formed.

The present invention has been described in terms of a read only memory device (ROM) . Particularly, in terms of a ROM which is programmed by modulating a threshold voltage of vertical transistors by different channel dopings . However, the present invention is applicable to a wide variety of semiconductor devices. For example, memory devices, such as dynamic random access memory (DRAM) devices, with buried bitlines or wordlines may employ the present invention. A preferred embodiment of the present invention increases the effective width of lower bitline 126 by a factor of about 1.73. Other factors may be achieved. The factor of 1.73 enables the distance between bitlines to shrink considerably, and as such can provide a way to enable more dense memory cells. Further, diffused portions on sides of each bitline may be reduced considerably to eliminate or prevent any risk of adjacent bitlines from shorting out against one another. Having described preferred embodiments for a semiconductor device with improved buried bitlines (which are intended to be illustrative and not limiting) , it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments of the invention disclosed which are within the scope and spirit of the invention as outlined by the appended claims. Having thus described the invention with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.

Claims

WHAT IS CLAIMED IS;

1. A semiconductor device comprising: a substrate having trenches formed therein, the trenches extending in a first direction, the first direction being substantially parallel to a top surface of the substrate; each trench including a bottom portion, the bottom portion having a bottom surface transversely disposed relative to the top surface of the substrate, the bottom portion being formed in communication with the trench; and an addressing line formed adjacent to the bottom surface such that an effective width of the addressing line is a distance along the bottom surface between side walls of the trench and the distance is greater than a width of the trench.

2. The device as recited in claim 1, wherein the bottom surface is V-shaped.

3. The device as recited in claim 1, wherein the semiconductor device is a read only memory.

4. The device as recited in claim 1, wherein the substrate is a silicon crystal substrate and the bottom surface includes an exposed (111) plane.

5. The device as recited in claim 1, wherein the effective width of the addressing line is greater than about 1.7 times the width of the trench.

6. The device as recited in claim 1, wherein the addressing line includes one of a wordline and a bitline.

7. A method for forming buried bitlines comprising the steps of : providing a substrate having trenches formed therein, the trenches extending a distance in a first direction, the first direction being parallel to a top surface of the substrate; forming spacers on side walls of the trenches; etching a bottom surface of the trenches to extend the bottom surface into a V-shaped notch; and doping the substrate adjacent to the V-shaped notch to form a bitline.

8. The method as recited in claim 7, further comprising the step of annealing the substrate to diffuse and activate the bitline.

9. The method as recited in claim 8, wherein the step of annealing the substrate to diffuse and activate the bitline includes annealing the substrate by employing a rapid thermal oxidation anneal.

10. The method as recited in claim 7, further comprising the steps of removing the spacers and forming a gate oxide on the side walls of the trenches.

11. The method as recited in claim 7, further comprising the step of doping the substrate adjacent to a top surface between the trenches to form upper bitlines.

12. The method as recited in claim 11, further comprising the step of forming a dielectric layer on the upper bitlines and the bitlines adjacent to the V-shaped notch.

13. The method as recited in claim 12, further comprising the step of forming a word line in the trenches and over the substrate.

14. The method as recited in claim 7, wherein the step of etching a bottom surface of the trenches includes the step of anisotropically wet etching the bottom surface to form the V-shaped notch.

15. The method as recited in claim 14, wherein the step of anisotropically wet etching the bottom surface to form the V-shaped notch includes anisotropically wet etching with potassium hydroxide.

16. A method for forming buried bitlines in read only memories comprising the steps of: providing a silicon substrate having trenches formed therein, the trenches extending a distance in a first direction, the first direction being parallel to a top surface of the substrate, the top surface of the substrate being disposed in a (100) plane; forming spacers on side walls of the trenches; anisotropically wet etching a bottom surface of the trenches to extend the bottom surface into a V-shaped notch such that surfaces of the bottom surface are disposed in (111) planes; and doping the substrate adjacent to the V-shaped notch and the top surface of the substrate to form lower bitlines and upper bitlines, respectively.

17. The method as recited in claim 16, further comprising the step of annealing the substrate to diffuse and activate the upper and lower bitlines.

18. The method as recited in claim 17, wherein the step of annealing the substrate includes annealing the substrate by employing a rapid thermal oxidation anneal.

19. The method as recited in claim 16, further comprising the steps of removing the spacers and forming a gate oxide on the side walls of the trenches.

20. The method as recited in claim 16, wherein the step of anisotropically wet etching includes anisotropically wet etching with potassium hydroxide.