JPH0384924A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0384924A JPH0384924A JP1221987A JP22198789A JPH0384924A JP H0384924 A JPH0384924 A JP H0384924A JP 1221987 A JP1221987 A JP 1221987A JP 22198789 A JP22198789 A JP 22198789A JP H0384924 A JPH0384924 A JP H0384924A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- mask
- semiconductor substrate
- ions
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 150000002500 ions Chemical class 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000005468 ion implantation Methods 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 abstract description 6
- 230000001681 protective effect Effects 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 4
- 239000005365 phosphate glass Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 3
- 238000001459 lithography Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置の製造方法に関すん従来の技術
近If、 5urrounded Capacito
r Ce1l (以下SCCと称す)構造のDRAMの
開発が行われている(特開昭60−198076号公報
)。第2図は従来のSCC構造を用いたDRAMのセル
部分の製造方法を示す工程断面図であも
半導体基板1としてP0シリコン基板上に第1保護膜2
として約50nmの熱酸化膜および第2保護膜3として
約220nmのポリシリコン膜およびマスク用絶縁膜4
として約190nmのリンガラス膜を形威すも次にマス
ク用絶縁膜4をマスクとして半導体基板l上の素子分離
領域に第1の溝5を形成する(第2図(a)〉。次に既
知のりソグラフィ技術を用いて第1の溝5と素子領域2
6が同時に露出するようにレジスト29をバターニング
する(第2図(b))。レジスト29とマスク用絶縁膜
4をマスクとして半導体基板1表面の法線に対して約7
°の角度から後の工程で形成されるノード電極となるn
3層19とトランジスタのソース22を接続する接続n
″″層27を形成するためのn0層形成イオン30とし
てAsイオンを注入すも この暇 第1の溝5の接続n
9層27が形成されている側壁の反対側の側壁(友 レ
ジスト29でマスクされているためイオン注入されない
(第2図(C))。第2図(b)中に示すY−Y’線に
沿った断面の一部が第2図(C)であも その上に第1
の溝側壁材料形成用絶縁膜6として約180nmのCV
D酸化膜を堆積しく第2図(d))、垂直方向に異方性
のあるエツチング法により第1の溝側壁材料形成用絶縁
膜6を第1の溝5の側面だけに残留させ、第1の溝側壁
材料7とする(第2図(e))。第1の溝5中の半導体
基板1表面が露出した部分をさらに深くエツチングして
第2の溝8を形成し マスク用絶縁膜4と第1の溝側壁
材料7をマスクとして半導体基板1表面の法線に対して
約7°の角度からノード電極形成用のAsイオン17を
注入し第2の溝8の側壁だけにノード電極となるn0層
19を形成する(第2図(f))。次に第2の溝8の両
側のn゛層19を分離するために第2の溝8を約300
nm掘り下(デ、次に半導体基板1とn°層19の電気
的分離を確実にするための90層20を形成するために
半導体基板1の表面の法線に対して約7°の角度からB
イオン18を注入する(第2図(g))。次に容量酸化
膜9として約10nmの薄い熱酸化膜を形成し セルプ
レート電極材料10としてポリシリコン膜をCVD法等
を用いて堆積する(第2図(h)〉。次にセルプレート
電極材料10を第1の溝5の底面程度までエラチンブレ
マスク用絶縁膜4を除去する(第2図(i))。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device.
A DRAM having an r Ce1l (hereinafter referred to as SCC) structure is being developed (Japanese Patent Application Laid-open No. 198076/1983). FIG. 2 is a process cross-sectional view showing a method of manufacturing a cell part of a DRAM using a conventional SCC structure.
A thermal oxide film of approximately 50 nm as a second protective film 3, a polysilicon film of approximately 220 nm as a second protective film 3, and an insulating film 4 for a mask.
Then, using the mask insulating film 4 as a mask, a first groove 5 is formed in the element isolation region on the semiconductor substrate l (see FIG. 2(a)). The first groove 5 and the device region 2 are formed using known lithography techniques.
The resist 29 is patterned so that 6 is exposed at the same time (FIG. 2(b)). Using the resist 29 and the mask insulating film 4 as a mask, the distance is approximately 7 mm relative to the normal to the surface of the semiconductor substrate 1.
n, which will become the node electrode formed in a later process from the angle of °.
Connection n connecting the third layer 19 and the source 22 of the transistor
During this time, As ions are implanted as n0 layer forming ions 30 to form the ``'' layer 27.
The side wall opposite to the side wall on which the 9th layer 27 is formed is masked by the resist 29, so ions are not implanted (Fig. 2 (C)). A part of the cross section along is shown in Figure 2 (C).
CV of about 180 nm as the insulating film 6 for forming groove side wall material.
In order to deposit the D oxide film (FIG. 2(d)), the insulating film 6 for forming the first trench sidewall material is left only on the side surfaces of the first trench 5 using an etching method with vertical anisotropy. 1 (FIG. 2(e)). The exposed portion of the semiconductor substrate 1 surface in the first trench 5 is further etched to form a second trench 8, and the semiconductor substrate 1 surface is etched using the mask insulating film 4 and the first trench sidewall material 7 as a mask. As ions 17 for forming a node electrode are implanted at an angle of about 7° to the normal line to form an n0 layer 19 that will become a node electrode only on the side wall of the second groove 8 (FIG. 2(f)). Next, the second groove 8 is cut approximately 300 times in order to separate the n layer 19 on both sides of the second groove 8.
nm digging (de, then at an angle of approximately 7° to the normal to the surface of the semiconductor substrate 1 to form a 90 layer 20 to ensure electrical isolation between the semiconductor substrate 1 and the n° layer 19). From B
Ions 18 are implanted (FIG. 2(g)). Next, a thin thermal oxide film of about 10 nm is formed as a capacitive oxide film 9, and a polysilicon film is deposited as a cell plate electrode material 10 using a CVD method (see Fig. 2 (h)). 10, the insulating film 4 for the eraser mask is removed to about the bottom of the first groove 5 (FIG. 2(i)).
次に第1の溝5を埋め込み材料14を用いて周知の方法
により平坦化し 通常のMO3FET作戒工程に上りド
レイン21.ソース22.ゲート23を有するMOS)
ランジスタを形成する(第2図(j))。Next, the first groove 5 is flattened using a filling material 14 by a well-known method, and then the drain 21. Source 22. MOS with gate 23)
A transistor is formed (FIG. 2(j)).
発明が解決しようとする課題
従来の製造方法でCヨ イオン注入したい領域以外の
部分すべてにイオン注入マスクを形成していたたム 溝
5の寸法が微細になるとレジスト29の溝5上の開口部
50も狭くなり、マスク29の所望の開口部50がフォ
ト工程では形成不可能となも 節板 レジスト29の微
細パターンを溝5の一部を覆って正確に形成すること(
よ 溝5の寸法がフォトグラフィ工程の極限に近い微細
なものになると不可能となも このようになると溝5内
の一部にレジストパターン29の形成が行なわれない力
\ または第3図に示すように開口部の底部及び側壁部
のイオン注入すべき一部にレジストが残りこれがマスク
となって溝5の側壁に十分な接続n0層27が形成され
ず、ノード電極n0層19とソース22が接続されない
という問題があった さらにこの問題は溝のアスペクト
比が大きくなるにつれ益々顕著になん またこの問題は
DRAMの製造に限ら哄 溝の所望する側壁部にイオン
注入する半導体装置の製造一般に共通の問題であも フ
ォトリソグラフィの解像度が上がってもその分率導体装
置が微細になるた△ 溝のアスペクト比が増しDRAM
等の超LSIの製造において避けては通れない課題の一
つであっtら
本発明(よ 上述の問題点に鑑みてなされたもので半導
体装置が微細になっても溝の所望する側壁部にイオン注
入でき、素子性能の良好な半導体装置が得られる半導体
装置の製造方法を提供することを目的とすa
課題を解決するための手段
本発明は上述の課題を解決するた△ 半導体基板に溝を
形成する工程と、前記溝よりも大きな開口を有するイオ
ン注入マスクを形成する工程と、前記イオン注入マスク
を用いて前記半導体基板表面の法線に対して斜めの一方
向より前記開口した溝の側壁の一部にイオン注入を行う
工程とを備えた半導体装置の製造方法であも
作用
本発明は上述の構成により、一方向からのイオン注入に
より、イオンの直進性を用いて、溝より十分大きく開口
したイオン注入マスクをマスクとして溝の側壁の一方に
のみ不純物をドーピングヒ確実に所望の不純物層を形成
できも
実施例
第1図は本発明の一実施例におけるSCC構造を用いた
DRAMセルの製造方法を示す工程断面図であも 以下
第1図を用いて実施例を説明す4半導体基板lとしてP
型シリコン基板上に第1保護膜2として約50nmの熱
酸化膜及び第2保護膜3として220nmのCVDポリ
シリコンを形成し マスク用絶縁膜4として約190n
mのリンガラス膜をCVD法により堆積すも 次にマス
ク用絶縁jl!4をマスクとして半導体基板lの素子分
離領域に深さがlllQOnmと一定であり、最小溝幅
が600nmの第1の溝5を形成する(第1図(a))
。次に既知のりソグラフィ技術を用いて接続02層を形
威したい第1の溝の部分溝5よりも十分大きな開口部1
00を持ち第1の溝5の一部と素子領域26が同時に露
出するようにレジスト39をパターニングする(第1図
(b))。レジスト39とマスク用絶縁膜4をマスクと
して半導体基板lの表面の法線に対して約7°の角度で
第1n0層形戊イオン30をAsイオンを一方向から1
50KeVで2.0xlO”cr”注入し接続n0層2
7を形成する(第1図(C))。第1図(b)中に示す
x−x’線に沿った断面の一部が第1図(C)であ瓜
これらの接続n0層27ハ 後の工程で形成されるノ
ード電極n0層19とトランジスタのソース22を接続
するものであも 一方向からのイオン注入30を用いる
たム 開口部100が溝5のイオン注入すべき所望領域
よりも大きくても接続n0層27が形成でき瓜本実施例
ではn0層形成イオン30としてAsイオンを用いたが
これはAsイオンを用いると注入の際制御性が良いこと
と、後工程に於ける熱処理において拡散しに(1,t、
ためであも
次にレジスト29を除去し その上に第1の溝側壁材料
形成用絶縁膜6として約180nmのCVD酸化膜を堆
積する(第1図(d))。その上からCHhガスを用い
たカソードカップリング平行平板型ドライエツチング装
置(以下RIE法と称す)により第1の溝側壁材料形成
用絶縁膜6を第1の溝5の側面だけに残留させ、第1の
溝側壁材料7とする(第1図(e)〉。第1図(e)に
おいて第1の溝5中の半導体基板1表面が露出した部分
を再び5iC14とCH2F2ガスを用いたRIE法に
より約1.5層mの深さまでさらに深くエツチングして
第2の溝8を形威し マスク用絶縁膜4と第1の溝側壁
材料7をマスクとして半導体基板Iの表面の法線に対し
て約7°の角度からノード電極形成用のAsイオン17
を80Kevで2.0xlO”cm−’注入し第2の溝
8の側壁だケニノード電極となるn0層19を形成した
後(第1図(f))、第2の溝8の両側のn0層19を
分離するために第2の溝8を約300nmエツチングし
第2の溝8の底部の11層層19を除去し 半導体基板
1とn1層19の電気的分離を確実にするためかつチャ
ンネルストッパ層兼素子領域の半導体基板lからの電気
的浮き上がりを防止するために半導体基板1の表面の法
線に対して約7°の角度からBイオン18を50KeV
で7゜0xiO”cm−”注入り、、n”層19より深
い領域に93層20を形成する(第1図(g))。溝8
の周囲に不純物層を形成する必要性があるたべ ここで
はAsイオン17. Bイオン18注入は4回ステップ
イオン注入を用いも 次に容量酸化膜9として約10n
mの薄い熱酸化膜を形成し セルプレート電極材料10
としてポリシリコン膜をCVD法等を用いて第1の溝5
及び第2の溝8に十分埋まる程度例えば約190nm堆
積する(第1図(h))。次にマスク用絶縁膜4を素子
領域26のエツチングストッパ兼マスクとしてセルプレ
ート電極材料10を第1の溝5の底面程度までエツチン
グ服 次にマスク用絶縁膜4を除去する(第1図(i)
)。次に第1の溝5の埋め込み材料14としてCVD法
等により酸化膜を堆積し 周知の方法により平坦化した
後、通常のMOS F ET作成工程によりドレイン2
1.ソース22.ゲート23を有するMO8)ランジス
タを形成する(第1図(j))。Problems to be Solved by the Invention In the conventional manufacturing method, an ion implantation mask was formed in all areas except the area where ions were to be implanted. 50 becomes narrower, and the desired opening 50 of the mask 29 cannot be formed in the photo process.
However, if the dimensions of the groove 5 become extremely small, close to the limits of the photolithography process, this may become impossible. As shown, resist remains on the bottom and sidewalls of the opening where ions should be implanted, and this serves as a mask, so that a sufficient connection n0 layer 27 is not formed on the sidewalls of the trench 5, and the node electrode n0 layer 19 and source 22 Furthermore, this problem becomes more and more pronounced as the aspect ratio of the trench increases.Also, this problem is not limited to the manufacturing of DRAMs, but is common to the manufacturing of semiconductor devices in general, where ions are implanted into the desired sidewalls of the trench. Even if the resolution of photolithography increases, the conductor device becomes finer and the aspect ratio of the groove increases.
This is one of the problems that cannot be avoided in the manufacturing of VLSIs, and the present invention was made in view of the above-mentioned problems. It is an object of the present invention to provide a method for manufacturing a semiconductor device that allows ion implantation and provides a semiconductor device with good device performance. forming an ion implantation mask having an opening larger than the groove; and using the ion implantation mask to open the opened groove from one direction oblique to the normal to the surface of the semiconductor substrate. The present invention is also applicable to a method of manufacturing a semiconductor device, which includes a step of implanting ions into a part of the sidewall. Using an ion implantation mask with a large opening as a mask, the impurity is doped only on one sidewall of the trench to ensure the formation of the desired impurity layer. Hereinafter, an example will be explained using FIG. 1. As a semiconductor substrate l, P
A thermal oxide film of approximately 50 nm as a first protective film 2 and a CVD polysilicon of 220 nm as a second protective film 3 are formed on a mold silicon substrate, and a CVD polysilicon film of approximately 190 nm is formed as a mask insulating film 4.
A phosphorus glass film of m is deposited by the CVD method, but then mask insulation jl! 4 as a mask, a first trench 5 having a constant depth of 11QOnm and a minimum trench width of 600 nm is formed in the element isolation region of the semiconductor substrate 1 (FIG. 1(a)).
. Next, using known lithography techniques, an opening 1 is formed that is sufficiently larger than the partial groove 5 of the first groove in which the connection 02 layer is to be formed.
00, and the resist 39 is patterned so that a part of the first groove 5 and the element region 26 are exposed at the same time (FIG. 1(b)). Using the resist 39 and the mask insulating film 4 as a mask, the first n0 layered ions 30 are irradiated with As ions from one direction at an angle of about 7° to the normal to the surface of the semiconductor substrate l.
2.0xlO"cr" implanted at 50KeV to connect n0 layer 2
7 (Fig. 1(C)). A part of the cross section along the line xx' shown in Fig. 1(b) is shown in Fig. 1(C).
These connection n0 layers 27c are for connecting the node electrode n0 layer 19 to be formed in a later step and the source 22 of the transistor. The connection n0 layer 27 can be formed even if the area is larger than the desired region to be implanted.In this embodiment, As ions were used as the n0 layer forming ions 30, but this is because using As ions provides better controllability during implantation. , during the heat treatment in the post-process (1, t,
For this reason, the resist 29 is then removed, and a CVD oxide film of about 180 nm is deposited thereon as the insulating film 6 for forming the first trench sidewall material (FIG. 1(d)). Then, the insulating film 6 for forming the first trench sidewall material is left only on the side surfaces of the first trench 5 using a cathode coupling parallel plate dry etching device (hereinafter referred to as RIE method) using CHh gas. 1 (FIG. 1(e)). In FIG. 1(e), the exposed portion of the semiconductor substrate 1 surface in the first trench 5 is again subjected to RIE using 5iC14 and CH2F2 gas. The second trench 8 is formed by further etching to a depth of about 1.5 m by using the mask insulating film 4 and the first trench sidewall material 7 as a mask, with respect to the normal to the surface of the semiconductor substrate I. As ions 17 for forming a node electrode are
After injecting 2.0xlO"cm-' of 80Kev into the sidewalls of the second groove 8 to form the n0 layer 19 which will become the node electrode (Fig. 1(f)), the n0 layer on both sides of the second groove 8 is The second groove 8 is etched by about 300 nm to separate the N1 layer 19, and the 11 layer layer 19 at the bottom of the second groove 8 is removed. B ions 18 are heated at 50 KeV at an angle of approximately 7° to the normal to the surface of the semiconductor substrate 1 in order to prevent electrical lifting of the layer/element region from the semiconductor substrate 1.
93 layer 20 is formed in a region deeper than the n'' layer 19 (FIG. 1(g)).Groove 8
Here, it is necessary to form an impurity layer around the As ion 17. B ions 18 are implanted using four step ion implantations.
A thin thermal oxide film of m is formed to form a cell plate electrode material 10.
A polysilicon film is then formed into the first groove 5 using a CVD method or the like.
Then, the film is deposited to a thickness of about 190 nm, for example, to sufficiently fill the second groove 8 (FIG. 1(h)). Next, using the mask insulating film 4 as an etching stopper and mask for the element region 26, the cell plate electrode material 10 is etched to about the bottom of the first groove 5. Next, the mask insulating film 4 is removed (see FIG. )
). Next, an oxide film is deposited as the filling material 14 for the first groove 5 by CVD method or the like, and after planarized by a well-known method, the drain 2 is deposited by a normal MOS FET manufacturing process.
1. Source 22. A MO8) transistor having a gate 23 is formed (FIG. 1(j)).
以上のように本実施例では 溝5より十分大きく開口し
たイオン注入マスク39を用いるたへ 溝のアスペクト
比が増しても所望するレジストパターンが形成できフォ
トグラフィのプロセスマージンが大きくなん また 一
方向からのイオン注入により溝5の一方にのみ従来技術
に比べ確実に不純物層27を形成でき溝側壁でソースと
ノード電極01層が確実に接続できも このことはDR
AMの製造において必要不可欠であり、DRAMそのも
のの歩留まりに影響を与えも
表
16MDRAMにおいて従来の方法と本発明の方法との
マスク形成、不純物層の形成及び素子のソースとノード
電極接続の歩留まりを比較した結果を表に示も 本発明
の方法は従来の方法に比ベマスク形成が確実に行なわれ
るたべ 一方向からのイオン注入により溝の側壁の一方
にのみ不純物層が形成でき、そのためソースとノード電
極が確実に接続でき素子のソースとノード電極接続の歩
留まりが30%から80%に向上できた この歩留まり
が100%にならないのはバーチクルの要因である。As described above, in this embodiment, since the ion implantation mask 39 with an opening sufficiently larger than the groove 5 is used, the desired resist pattern can be formed even if the aspect ratio of the groove increases, and the process margin for photography is large. By ion implantation, the impurity layer 27 can be formed only in one side of the groove 5 more reliably than in the conventional technique, and the source and the node electrode 01 layer can be reliably connected on the side wall of the groove.
Table 16 Comparison of the yields of mask formation, impurity layer formation, and device source and node electrode connections between the conventional method and the method of the present invention in MDRAM, which is essential in the manufacture of AM and affects the yield of the DRAM itself. The results are shown in the table. Compared to the conventional method, the method of the present invention allows for more reliable mask formation.Ion implantation from one direction allows the impurity layer to be formed only on one sidewall of the trench, and therefore the source and node electrodes could be connected reliably, and the yield of connecting the source and node electrodes of the element could be improved from 30% to 80%.The reason why this yield was not 100% was due to the verticle.
な耘 本実施例ではDRAMセルの製造方法について説
明した爪 溝の所望する側壁部にイオン注入する半導体
装置全般に利用できることは言うまでもなLl
発明の効果
以上の説明から明らかなように 本発明によれば 一方
向からのイオン注入により、イオンの直進性を用いて、
溝より十分大きく開口したイオン注入マスクをマスクと
して溝の側壁の一方にのみ不純物をドーピングし 確実
に所望の不純物層を形成できも 従って、本発明は微細
構造の高密度集積化回路の歩留まり良い高精度な製造に
大きく寄与するものであもIn this embodiment, the method for manufacturing a DRAM cell is explained.It goes without saying that the present invention can be used for general semiconductor devices in which ions are implanted into a desired side wall of a groove. By ion implantation from one direction, using the linearity of ions,
A desired impurity layer can be reliably formed by doping only one sidewall of the trench with impurities using an ion implantation mask with an opening sufficiently larger than the trench. It greatly contributes to precision manufacturing.
第1図は本発明の一実施例における半導体装置の製造方
法を示す工程断面は 第2図は従来の半導体装置の製造
方法を示す工程断面は 第3図は従来のレジストマスク
形成時の問題点を説明するための断面図であもFIG. 1 is a process cross-section showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a process cross-section showing a conventional method for manufacturing a semiconductor device. FIG. 3 is a problem when forming a conventional resist mask. Even if it is a cross-sectional diagram to explain
Claims (4)
大きな開口を有するイオン注入マスクを形成する工程と
、前記イオン注入マスクを用いて前記半導体基板表面の
法線に対して斜めの一方向より前記開口した溝の側壁の
一部にイオン注入を行う工程とを備えた半導体装置の製
造方法。(1) A step of forming a groove in a semiconductor substrate, a step of forming an ion implantation mask having an opening larger than the groove, and a step of forming a groove obliquely to the normal to the surface of the semiconductor substrate using the ion implantation mask. A method of manufacturing a semiconductor device, comprising the step of implanting ions into a part of the side wall of the opened trench from the direction.
を特徴とする特許請求の範囲第1項記載の半導体装置の
製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation mask is formed outside the groove.
特徴とする特許請求の範囲第1項記載の半導体装置の製
造方法。(3) The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation mask is a photoresist.
1の溝よりも大きな開口を有するイオン注入マスクを形
成する工程と、前記イオン注入マスクを用いて前記半導
体基板表面の法線に対して斜めの一方向より前記開口し
た第1の溝の側壁の一部にイオン注入を行う工程と、前
記半導体基板上に膜を堆積し異方性の強いエッチングに
より前記堆積膜をエッチングして前記第1の溝の側壁だ
けに前記堆積膜を残す工程と、前記第1の溝中の半導体
基板が露出した部分をさらに深くエッチングして第2の
溝を形成する工程と、前記第2の溝の側壁に前記第1の
溝の側壁に注入したイオンと同種のイオンをドーピング
して前記第1の溝の側壁と前記第2の溝の側壁の不純物
層を連続に形成する工程とを備えた半導体装置の製造方
法。(4) forming a first groove in the semiconductor substrate; forming an ion implantation mask having an opening larger than the first groove; and using the ion implantation mask to a step of implanting ions into a part of the side wall of the first trench opened from one direction obliquely to the semiconductor substrate, and depositing a film on the semiconductor substrate and etching the deposited film by highly anisotropic etching. leaving the deposited film only on the side walls of the first trench; etching the exposed portion of the semiconductor substrate in the first trench deeper to form a second trench; doping the sidewalls of the trenches with ions of the same type as the ions implanted into the sidewalls of the first trenches to continuously form impurity layers on the sidewalls of the first trenches and the sidewalls of the second trenches; A method for manufacturing a semiconductor device comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1221987A JPH0384924A (en) | 1989-08-29 | 1989-08-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1221987A JPH0384924A (en) | 1989-08-29 | 1989-08-29 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0384924A true JPH0384924A (en) | 1991-04-10 |
Family
ID=16775304
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1221987A Pending JPH0384924A (en) | 1989-08-29 | 1989-08-29 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0384924A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0533475A2 (en) * | 1991-09-17 | 1993-03-24 | Fujitsu Limited | Optical semiconductor device, method of producing the optical semiconductor device, and laser device using optical semiconductor devices |
US5328854A (en) * | 1993-03-31 | 1994-07-12 | At&T Bell Laboratories | Fabrication of electronic devices with an internal window |
US5874346A (en) * | 1996-05-23 | 1999-02-23 | Advanced Micro Devices, Inc. | Subtrench conductor formation with large tilt angle implant |
WO2000072377A1 (en) * | 1999-05-20 | 2000-11-30 | Infineon Technologies Ag | Method for creating a trench contact for a memory location arrangement |
WO2002001607A3 (en) * | 2000-06-23 | 2002-05-23 | Infineon Technologies Corp | Method of producing trench capacitor buried strap |
-
1989
- 1989-08-29 JP JP1221987A patent/JPH0384924A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0533475A2 (en) * | 1991-09-17 | 1993-03-24 | Fujitsu Limited | Optical semiconductor device, method of producing the optical semiconductor device, and laser device using optical semiconductor devices |
US5347533A (en) * | 1991-09-17 | 1994-09-13 | Fujitsu Limited | Optical semiconductor device, method of producing the optical semiconductor device, and laser device using optical semiconductor devices |
US5328854A (en) * | 1993-03-31 | 1994-07-12 | At&T Bell Laboratories | Fabrication of electronic devices with an internal window |
US5874346A (en) * | 1996-05-23 | 1999-02-23 | Advanced Micro Devices, Inc. | Subtrench conductor formation with large tilt angle implant |
US6066885A (en) * | 1996-05-23 | 2000-05-23 | Advanced Micro Devices, Inc. | Subtrench conductor formed with large tilt angle implant |
WO2000072377A1 (en) * | 1999-05-20 | 2000-11-30 | Infineon Technologies Ag | Method for creating a trench contact for a memory location arrangement |
WO2002001607A3 (en) * | 2000-06-23 | 2002-05-23 | Infineon Technologies Corp | Method of producing trench capacitor buried strap |
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