JPH0384924A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To surely form a desired impurity layer by a method wherein an ion implantation mask having an opening larger than a groove is formed and, by using this mask, ions are implanted into one part of a sidewall of the opened groove from one oblique direction with reference to a normal line on the surface of a semiconductor substrate. CONSTITUTION:A thermal oxide film as a first protective film 2 and CVD polysilicon as a second protective film 3 are formed on a semiconductor substrate 1; a phosphate glass film is deposited as an insulating film 4 for mask use. Then, a first groove 5 is formed in an element isolation region of the semiconductor substrate 1 by making use of the insulating film 4 for mask use as a mask. A resist 39 is patterned in such a way that an opening part 100 sufficiently larger than the first groove 5 is formed and that one part of the first groove 5 and an element region 26 are exposed simultaneously. As ions as first n<+> layer formation ions 30 are implanted from one direction at an angle of about 7 deg. with reference to a normal line on the surface of the semiconductor substrate 1 by making use of the resist 39 and the insulating film 4 for mask use as a mask; a connecting n<+> layer 27 is formed. Since the ions 30 are implanted from one direction, the connecting n<+> layer 27 can be formed even when the opening part 100 is larger than a desired region, into which the ions are to be implanted, of the groove 5.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device.
A DRAM having an r Ce1l (hereinafter referred to as SCC) structure is being developed (Japanese Patent Application Laid-open No. 198076/1983). FIG. 2 is a process cross-sectional view showing a method of manufacturing a cell part of a DRAM using a conventional SCC structure.
A thermal oxide film of approximately 50 nm as a second protective film 3, a polysilicon film of approximately 220 nm as a second protective film 3, and an insulating film 4 for a mask.
Then, using the mask insulating film 4 as a mask, a first groove 5 is formed in the element isolation region on the semiconductor substrate l (see FIG. 2(a)). The first groove 5 and the device region 2 are formed using known lithography techniques.
The resist 29 is patterned so that 6 is exposed at the same time (FIG. 2(b)). Using the resist 29 and the mask insulating film 4 as a mask, the distance is approximately 7 mm relative to the normal to the surface of the semiconductor substrate 1.
n, which will become the node electrode formed in a later process from the angle of °.
Connection n connecting the third layer 19 and the source 22 of the transistor
During this time, As ions are implanted as n0 layer forming ions 30 to form the ``'' layer 27.
The side wall opposite to the side wall on which the 9th layer 27 is formed is masked by the resist 29, so ions are not implanted (Fig. 2 (C)). A part of the cross section along is shown in Figure 2 (C).
CV of about 180 nm as the insulating film 6 for forming groove side wall material.
In order to deposit the D oxide film (FIG. 2(d)), the insulating film 6 for forming the first trench sidewall material is left only on the side surfaces of the first trench 5 using an etching method with vertical anisotropy. 1 (FIG. 2(e)). The exposed portion of the semiconductor substrate 1 surface in the first trench 5 is further etched to form a second trench 8, and the semiconductor substrate 1 surface is etched using the mask insulating film 4 and the first trench sidewall material 7 as a mask. As ions 17 for forming a node electrode are implanted at an angle of about 7° to the normal line to form an n0 layer 19 that will become a node electrode only on the side wall of the second groove 8 (FIG. 2(f)). Next, the second groove 8 is cut approximately 300 times in order to separate the n layer 19 on both sides of the second groove 8.
nm digging (de, then at an angle of approximately 7° to the normal to the surface of the semiconductor substrate 1 to form a 90 layer 20 to ensure electrical isolation between the semiconductor substrate 1 and the n° layer 19). From B
Ions 18 are implanted (FIG. 2(g)). Next, a thin thermal oxide film of about 10 nm is formed as a capacitive oxide film 9, and a polysilicon film is deposited as a cell plate electrode material 10 using a CVD method (see Fig. 2 (h)). 10, the insulating film 4 for the eraser mask is removed to about the bottom of the first groove 5 (FIG. 2(i)).

Next, the first groove 5 is flattened using a filling material 14 by a well-known method, and then the drain 21. Source 22. MOS with gate 23)
A transistor is formed (FIG. 2(j)).

Problems to be Solved by the Invention In the conventional manufacturing method, an ion implantation mask was formed in all areas except the area where ions were to be implanted. 50 becomes narrower, and the desired opening 50 of the mask 29 cannot be formed in the photo process.
However, if the dimensions of the groove 5 become extremely small, close to the limits of the photolithography process, this may become impossible. As shown, resist remains on the bottom and sidewalls of the opening where ions should be implanted, and this serves as a mask, so that a sufficient connection n0 layer 27 is not formed on the sidewalls of the trench 5, and the node electrode n0 layer 19 and source 22 Furthermore, this problem becomes more and more pronounced as the aspect ratio of the trench increases.Also, this problem is not limited to the manufacturing of DRAMs, but is common to the manufacturing of semiconductor devices in general, where ions are implanted into the desired sidewalls of the trench. Even if the resolution of photolithography increases, the conductor device becomes finer and the aspect ratio of the groove increases.
This is one of the problems that cannot be avoided in the manufacturing of VLSIs, and the present invention was made in view of the above-mentioned problems. It is an object of the present invention to provide a method for manufacturing a semiconductor device that allows ion implantation and provides a semiconductor device with good device performance. forming an ion implantation mask having an opening larger than the groove; and using the ion implantation mask to open the opened groove from one direction oblique to the normal to the surface of the semiconductor substrate. The present invention is also applicable to a method of manufacturing a semiconductor device, which includes a step of implanting ions into a part of the sidewall. Using an ion implantation mask with a large opening as a mask, the impurity is doped only on one sidewall of the trench to ensure the formation of the desired impurity layer. Hereinafter, an example will be explained using FIG. 1. As a semiconductor substrate l, P
A thermal oxide film of approximately 50 nm as a first protective film 2 and a CVD polysilicon of 220 nm as a second protective film 3 are formed on a mold silicon substrate, and a CVD polysilicon film of approximately 190 nm is formed as a mask insulating film 4.
A phosphorus glass film of m is deposited by the CVD method, but then mask insulation jl! 4 as a mask, a first trench 5 having a constant depth of 11QOnm and a minimum trench width of 600 nm is formed in the element isolation region of the semiconductor substrate 1 (FIG. 1(a)).
. Next, using known lithography techniques, an opening 1 is formed that is sufficiently larger than the partial groove 5 of the first groove in which the connection 02 layer is to be formed.
00, and the resist 39 is patterned so that a part of the first groove 5 and the element region 26 are exposed at the same time (FIG. 1(b)). Using the resist 39 and the mask insulating film 4 as a mask, the first n0 layered ions 30 are irradiated with As ions from one direction at an angle of about 7° to the normal to the surface of the semiconductor substrate l.
2.0xlO"cr" implanted at 50KeV to connect n0 layer 2
7 (Fig. 1(C)). A part of the cross section along the line xx' shown in Fig. 1(b) is shown in Fig. 1(C).
These connection n0 layers 27c are for connecting the node electrode n0 layer 19 to be formed in a later step and the source 22 of the transistor. The connection n0 layer 27 can be formed even if the area is larger than the desired region to be implanted.In this embodiment, As ions were used as the n0 layer forming ions 30, but this is because using As ions provides better controllability during implantation. , during the heat treatment in the post-process (1, t,
For this reason, the resist 29 is then removed, and a CVD oxide film of about 180 nm is deposited thereon as the insulating film 6 for forming the first trench sidewall material (FIG. 1(d)). Then, the insulating film 6 for forming the first trench sidewall material is left only on the side surfaces of the first trench 5 using a cathode coupling parallel plate dry etching device (hereinafter referred to as RIE method) using CHh gas. 1 (FIG. 1(e)). In FIG. 1(e), the exposed portion of the semiconductor substrate 1 surface in the first trench 5 is again subjected to RIE using 5iC14 and CH2F2 gas. The second trench 8 is formed by further etching to a depth of about 1.5 m by using the mask insulating film 4 and the first trench sidewall material 7 as a mask, with respect to the normal to the surface of the semiconductor substrate I. As ions 17 for forming a node electrode are
After injecting 2.0xlO"cm-' of 80Kev into the sidewalls of the second groove 8 to form the n0 layer 19 which will become the node electrode (Fig. 1(f)), the n0 layer on both sides of the second groove 8 is The second groove 8 is etched by about 300 nm to separate the N1 layer 19, and the 11 layer layer 19 at the bottom of the second groove 8 is removed. B ions 18 are heated at 50 KeV at an angle of approximately 7° to the normal to the surface of the semiconductor substrate 1 in order to prevent electrical lifting of the layer/element region from the semiconductor substrate 1.
93 layer 20 is formed in a region deeper than the n'' layer 19 (FIG. 1(g)).Groove 8
Here, it is necessary to form an impurity layer around the As ion 17. B ions 18 are implanted using four step ion implantations.
A thin thermal oxide film of m is formed to form a cell plate electrode material 10.
A polysilicon film is then formed into the first groove 5 using a CVD method or the like.
Then, the film is deposited to a thickness of about 190 nm, for example, to sufficiently fill the second groove 8 (FIG. 1(h)). Next, using the mask insulating film 4 as an etching stopper and mask for the element region 26, the cell plate electrode material 10 is etched to about the bottom of the first groove 5. Next, the mask insulating film 4 is removed (see FIG. )
). Next, an oxide film is deposited as the filling material 14 for the first groove 5 by CVD method or the like, and after planarized by a well-known method, the drain 2 is deposited by a normal MOS FET manufacturing process.
1. Source 22. A MO8) transistor having a gate 23 is formed (FIG. 1(j)).

As described above, in this embodiment, since the ion implantation mask 39 with an opening sufficiently larger than the groove 5 is used, the desired resist pattern can be formed even if the aspect ratio of the groove increases, and the process margin for photography is large. By ion implantation, the impurity layer 27 can be formed only in one side of the groove 5 more reliably than in the conventional technique, and the source and the node electrode 01 layer can be reliably connected on the side wall of the groove.
Table 16 Comparison of the yields of mask formation, impurity layer formation, and device source and node electrode connections between the conventional method and the method of the present invention in MDRAM, which is essential in the manufacture of AM and affects the yield of the DRAM itself. The results are shown in the table. Compared to the conventional method, the method of the present invention allows for more reliable mask formation.Ion implantation from one direction allows the impurity layer to be formed only on one sidewall of the trench, and therefore the source and node electrodes could be connected reliably, and the yield of connecting the source and node electrodes of the element could be improved from 30% to 80%.The reason why this yield was not 100% was due to the verticle.

In this embodiment, the method for manufacturing a DRAM cell is explained.It goes without saying that the present invention can be used for general semiconductor devices in which ions are implanted into a desired side wall of a groove. By ion implantation from one direction, using the linearity of ions,
A desired impurity layer can be reliably formed by doping only one sidewall of the trench with impurities using an ion implantation mask with an opening sufficiently larger than the trench. It greatly contributes to precision manufacturing.

[Brief explanation of drawings]

FIG. 1 is a process cross-section showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a process cross-section showing a conventional method for manufacturing a semiconductor device. FIG. 3 is a problem when forming a conventional resist mask. Even if it is a cross-sectional diagram to explain

Claims (4)

[Claims] (1) A step of forming a groove in a semiconductor substrate, a step of forming an ion implantation mask having an opening larger than the groove, and a step of forming a groove obliquely to the normal to the surface of the semiconductor substrate using the ion implantation mask. A method of manufacturing a semiconductor device, comprising the step of implanting ions into a part of the side wall of the opened trench from the direction. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation mask is formed outside the groove. (3) The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation mask is a photoresist. (4) forming a first groove in the semiconductor substrate; forming an ion implantation mask having an opening larger than the first groove; and using the ion implantation mask to a step of implanting ions into a part of the side wall of the first trench opened from one direction obliquely to the semiconductor substrate, and depositing a film on the semiconductor substrate and etching the deposited film by highly anisotropic etching. leaving the deposited film only on the side walls of the first trench; etching the exposed portion of the semiconductor substrate in the first trench deeper to form a second trench; doping the sidewalls of the trenches with ions of the same type as the ions implanted into the sidewalls of the first trenches to continuously form impurity layers on the sidewalls of the first trenches and the sidewalls of the second trenches; A method for manufacturing a semiconductor device comprising: