TW448508B - Self-aligned cobalt silicide process for preventing the bridge connection between the gate and doped region of substrate - Google Patents

Abstract

A kind of self-aligned cobalt silicide process for preventing the bridge connection between the gate and doped substrate region is suitable for use on a substrate that has a gate and doped substrate region on both sides of the gate. At first, the double-layer insulation spacer with a surface composed of nitride is formed on the sidewall of gate. Then, a layer of cobalt metal is accommodated to form. The first thermally annealing process is performed onto the layer of cobalt metal in order to form cobalt silicide layer on the surfaces of gate and doped region, in which the non-reacted cobalt metal layer is remained on the surface of the double-layer spacer. After that, hot phosphoric acid solution is used to etch and remove the nitride layer of double-layer spacer and the non-reacted cobalt metal layer. The second thermally annealing process is then conducted. Since hot phosphoric acid solution can etch and remove the nitride of double-layer spacer, the non-reacted cobalt metal layer, and some residuals such that the bridge connection phenomenon occurred between the gate and doped substrate region can be prevented when performing the second thermally annealing process.

Description

448508 Amended J ^ 89101931 V. Description of the Invention (1) The present invention relates to a self-aligned silicide process, and particularly relates to a self-aligned lithography process that prevents the gate from bridging with the substrate doped region. With the increasing complexity of electronic devices, such as integrated circuits such as metal oxides (MOS), the size of crystals is also shrinking. Therefore, as for the channel area of the transistor, the source / drain resistance is also reduced. Relatively improved. In view of this, in order to reduce the resistance value and maintain the shallow junction between the metal layer and the mos transistor, the conventional technology discloses a self-aligned metal silicide process, as shown in FIG. 1. First, according to the first step, a basic MOS structure is formed on a semiconductor substrate 10 '. For example, an active region (not shown) is first isolated by a field oxide layer, and then according to the traditional integrated circuit manufacturing process such as deposition, lithography, and etching steps A gate oxide layer 12, a polycrystalline silicon gate 14, an oxide spacer 20 and a source / drain region 16 are formed in the active region. Then after the pre-metal dip step, a metal titanium layer is deposited 'for example' using a direct current (DC) magnetron sputtering process to comprehensively deposit a metal titanium layer with good oxygen absorption capabilities. At the proper temperature, 'it can react with silicon to form titanium silicide, and form a low-resistance compound by cross-diffusion'. Therefore, a good ohmic contact can be formed between the silicon and titanium interfaces. Second, the first thermal process, such as the rapid thermal annealing process (RTP), is performed at a temperature between 600 ° C and 800 ° C. As a result of this thermal annealing step ', the titanium silicide compound 31 is formed on the surface of the titanium and the polycrystalline silicon gate electrode 14 and the source / drain electrode 16. Among them, on the surface of the oxide spacer 20, a remaining titanium metal layer that does not react with silicon remains.

0503-4982T1V Repair l.ptc Page 4 4485 0 b Case No. 89Ϊ01931 Amendment V. Description of the Invention (2) Next, selective etching is used to remove the remaining titanium metal layer on the surface of the oxide barrier wall 2 〇 which has not reacted with silicon, for example, to An etchant containing a sulfuric acid solution is used to dissolve the remaining unreacted metal layer. Secondly, a second thermal process, such as a rapid thermal annealing process (RTP), is performed at a temperature of about 800 ° to 900 °. . After this thermal annealing step, the resistance of the compound 31 on the surface of the polycrystalline silicon gate 14 and the source / drain 16 can be reduced. However, in the traditional metal silicide process, when metal titanium is fully deposited by sputtering, and the first thermal annealing is performed, as the temperature increases, excess silicon will diffuse through the oxide gap. The wall 20 is further reacted with titanium on the surface of the oxide barrier wall 20 to form some residues 34. Because the subsequent selective wet etching process cannot remove the residue 34 on the surface of the oxide barrier wall 20, This results in a bridge between the gate and source / drain regions and causes the transistor to short-circuit. In addition, when the CMOS process technology is developed to reduce the gate length to below 018um and the shallow junctions required, it is difficult for the traditional titanium silicide process to continue to maintain low sheet resistance. In view of this, the purpose of the present invention is to solve the above-mentioned problem, and to use a better metal cobalt as an alternative material, which can 'maintain a low sheet resistance value' when the gate length is reduced to less than 0, in order to avoid cobalt silicide The process faces the same bridging problem, and a self-aligned cobalt silicide process is proposed to prevent the gate and source / drain bridges. It is suitable for a substrate that has a closed electrode and substrate doped regions on both sides of the gate. The process steps are as follows. Firstly, a double-layer insulating barrier wall made of nitride is formed on the side wall of the gate, and then it is conformably formed.

44350c _Case No. 89101931__ Year Month 5. Description of Invention (3)

Annealing process' to form a cobalt silicide layer on the surface of the gate electrode and the doped region, and leave an unreacted metal cobalt layer on the surface of the double-layered spacer wall. Next, the nitride and Unreacted metal layer and a second thermal annealing process. Since the hot phosphoric acid solution can etch away the disordered material of the double-layered spacer, the unreacted metal drill layer and some residues, so it can prevent the bridging phenomenon between the gate and the substrate doping region during the second thermal annealing process. occur. B Below, a self-aligned cobalt silicide manufacturing process for preventing gate-source / non-bridge bridging according to the present invention is illustrated in a diagrammatic manner. Brief description of the drawings: Figure 1 is a cross-sectional view showing the process of the traditional metal Shihua Huaqin process. Figures 2A to 2E are cross-sectional views of a self-aligned cobalt silicide process for preventing the closed electrode from bridging the substrate doped region in one embodiment of the present invention. [Symbol description] Semiconductor substrate ~ 10; gate oxide layer ~ 12; polycrystalline silicon gate ~ 14; oxide spacer ~ 20; source / drain region ~ 16; titanium silicide layer ~ 31; residue ~ 34; semiconductor substrate ~ 100; substrate doped region ~ 116; source / drain ~ 118; gate oxide ~ 112; polycrystalline dream gate ~ 114; double-layered spacer ~ 124; metal layer ~ 130; stone Xihua drilling layer ~ 131; residue ~ 134. Embodiment 凊 Refer to FIGS. 2A to 2E ′, which shows an embodiment of the present invention, a self-aligned cobalt silicide process that prevents the gate from bridging with the substrate doped region. Firstly, according to FIG. 2A, this embodiment is applicable to a semiconductor substrate 100. The method of forming the semiconductor substrate 100 is as follows:

0503-4982ΤΪ 修 l.ptc Page 6 4 485 v ___Case No. 89101931_Year_Month_Revision_ V. Description of the invention (4) Epi-crystalline (expi taxial) or silicon on the insulation layer (si 1 i con 〇 ni nsu 1 at or), etc., for convenience of explanation, a p-type silicon substrate is taken as an example here. Then define the active area where the transistor is located. For example, a thermal oxidation process, such as LOCOS, is used to form a field insulator, and the field insulating layer is used to isolate the active area (actiVe area) ( Not shown). Secondly, a gate 110 is formed on the active region and a substrate doped region located on both sides of the gate, such as a source / inverted region or a lightly doped region previously formed in this embodiment. For example, it may be based on Traditional integrated circuit processes such as deposition, lithographic etching, and ion doping steps form a gate oxide layer 11 2, a polycrystalline silicon gate 114 and a lightly doped region 116 in the active region. Next, referring to the circles 2B to 2C, a double-layered insulating barrier wall 12 made of nitride is formed on the side wall of the gate electrode 1 10. First, according to FIG. 2B, an insulating layer is conformally formed on the surface of the gate electrode 110, the lightly doped region 116, and the semiconductor substrate 100. The insulating layer material may be an oxide layer formed by a thermal oxidation method, or a chemical vapor phase The PETE0S oxide layer or plasma oxide layer (PEOXM20) formed by the deposition process. Then, a silicon nitride layer 122 can be formed on the surface of the emulsified layer 120 in compliance with the heating furnace tube at 650 ° C. Then, as shown in Figure 2C 'The silicon oxide layer 122 and the oxide layer 120 are etched back to form a double-layered spacer wall 1 2 4 with nitride on the sidewalls of the gate 1 14, and then an ion doping step may be performed in the lightly doped region 116 to form a A source / drain region 118 having an LDD structure. Next, a premetal removal step is performed, and then a metal is conformed to form a metal.

0503-4982TWffl.pt Page 7 44850b Revised SS 89101931 in the first month of the year V. Description of the invention (5) Cobalt layer, for example, a comprehensive deposition of a metallic cobalt with good oxygen absorption capacity by direct current (DC) magnetron sputtering process The layer 13 is characterized in that at a suitable temperature, thallium reacts with silicon to form cobalt silicide, and forms a low-resistance compound through cross-diffusion. Therefore, a good ohmic contact can be formed between the silicon and cobalt interfaces, where When the CMOS process technology is developed to reduce the gate length to less than 0.8 μm and the shallow junctions that need to be faced, because the traditional titanium silicide process is difficult to continue to maintain low sheet resistance, it is better to use a better metal Cobalt is an alternative material, which can continue to maintain a low sheet resistance when the gate length is reduced to less than 0.1. Secondly, referring to FIG. 2D, a first thermal process, such as a rapid thermal annealing process (RTP), is performed on the metallic cobalt layer 30, and the temperature is about 600.匚 to C. After this thermal annealing step, cobalt and compound silicon gate electrodes 14 and source / drain electrodes 11 8 are formed with cobalt silicide compounds 31. Among them, on the surface of the nitride 12 of the double-layered partition wall, a remaining metallic cobalt layer 34 that does not react with silicon and some residues (not shown) remain. Next, please refer to FIG. 2E for a selective etching step, such as using a hot acid solution to remove the nitride portion of the double-layer spacer 134, the remaining metal layer that has not reacted with "Shi Xi", and some residues. It can avoid the bridging phenomenon in the traditional 'process because the etchant containing sulfuric acid solution cannot dissolve the residue'. 'Second' implements the second thermal process, such as the rapid thermal annealing process (RTP). The temperature is about 800. 0 to 90 (TC). Through this thermal annealing step, the resistance value on the surface of the polycrystalline stone gate 1 1 4 and the source 1; and the pole 11 8 can be reduced. According to the above, Since the hot phosphoric acid solution can etch away the double-layered spacers

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^ 4 8 5 0 b

_ Plug No. 89101931 V. Description of the invention (6), so it is possible to carry out the bridging phenomenon in the second interval, gasification, unreacted metal drilling layer and some residues in the second thermal annealing process, to prevent gate and substrate doping. Although the present invention has been disclosed as above with a preferred embodiment to limit the present invention, anyone skilled in the art can make changes and retouching without departing from the spirit and scope. Therefore, the present invention The invention park shall be subject to the protection scope as defined in the attached patent application scope.

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Claims (1)

• 4485 0 b --MM, 89101931_year b amendment ___ 6. Application for patent scope 1. A self-aligned cobalt silicide process to prevent gate and source / drain bridge bridging 'suitable for a substrate' which has a gate Electrode and substrate doped regions located on both sides of the gate, including the following steps: (a) forming a double-layered insulating barrier wall made of nitride on the sidewall of the gate; (b) conformable formation-a metallic cobalt layer (C) performing a first thermal annealing process on the metallic cobalt layer to form a cobalt silicide layer on the surface of the gate and the substrate doped region, and leaving an unreacted metallic cobalt layer on the surface of the double-layered spacer wall; (d) Selective etching removes the nitride and unreacted metal cobalt layer of the double-layered spacer; and (e) performs a second thermal annealing process. 2. The process as described in item 1 of the scope of patent application, wherein the step (a) is to form a double-layered insulating barrier made of nitride and oxide on the side wall of the gate. 3. The process according to item 1 of the scope of patent application, wherein the step (d) is to selectively remove the nitride and unreacted metal cobalt layer of the double-layered spacer with a hot phosphoric acid solution. 4. A self-aligned cobalt silicide process for preventing gate and source / drain bridging is applicable to a semiconductor substrate, and the method includes the following steps: (a) forming a gate on the surface of the semiconductor substrate and two gates located on the gate; Side lightly doped region; (b) conformally forming an insulating layer on the gate, the lightly doped region and the surface of the semiconductor substrate; 0503-4982TW Repair l.ptc Page 10 4 4 8l- 5. The process described in item 4 of the patent scope (b) is to conform to the formation of a gas layer to identify the outer surface of the substrate or step. The layer is on the gate, the lightly doped region and the semiconductor. O5O3-49S2I ^ 01-Ptc