JP2007201294A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a semiconductor device having elements both in a silicide region and a nonsilicide region without increasing junction leak, even if a spacing is small between adjacent gate electrodes in a silicide forming region. <P>SOLUTION: A method of manufacturing the semiconductor device comprises a diffusion layer forming step (a) of forming a plurality of gate electrodes 103 in the silicide region Rsili and non silicide region Rnon, and a plurality of diffusion layers 104 on a semiconductor substrate 101 which is exposed from the gate electrodes 103; a first dielectric forming step (b) of forming a first dielectric 107 on the semiconductor substrate 101; a second dielectric forming step (c) of adding an impurity to the first dielectric 107 in the silicide region to form a second dielectric 107b having a slower etching rate than the first dielectric 107; and a step of removing the first dielectric 107a remaining on the silicide region Rsili by wet etching after retreating step (d) of the first dielectric 107 by anisotropic etching. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device having a metal silicide layer, and more particularly to a salicide technique.

  2. Description of the Related Art In recent semiconductor device manufacturing methods, a salicide process is used in which a metal silicide layer is formed in an impurity diffusion layer in a gate electrode or a source / drain region to reduce resistance in order to increase the speed of circuit elements. .

  On the other hand, when a semiconductor element is used as a resistance element, it is suitable not to silicide the impurity diffusion layer in the gate electrode or the source / drain region. Therefore, a manufacturing method of a semiconductor device in which both a silicide element and a non-silicide element are formed on the same semiconductor substrate is used (for example, see Patent Document 1).

  6 (a) to 6 (d) and FIG. 7 (a) are cross-sectional views showing respective steps of a conventional semiconductor device manufacturing method using a salicide process.

  6A to 6D and FIG. 7A, the left side shows a silicide formation region RSili for forming a silicide element, and the right side shows a non-silicide formation region Rnon for forming a non-silicide element.

  Here, a case where two adjacent FETs are formed in the silicide formation region Sili on the semiconductor substrate 1 and one FET is formed in the non-silicide formation region Rnon will be described.

  First, as shown in FIG. 6A, an element isolation oxide film 2 is formed on a semiconductor substrate 1 so as to surround a region to be activated by a LOCOS isolation method or an STI isolation method. Next, a gate oxide film (not shown) is grown on each active region surrounded by the element isolation oxide film 2 by a thermal oxidation method. Next, a polysilicon film is grown on the gate oxide film by a CVD method, and the polysilicon film is patterned by a photolithography method and a dry etching method to form the gate electrode 3. Here, two gate electrodes 3 are formed in the silicide formation region RSili, and one gate electrode 3 is formed in the non-silicide formation region Rnon.

  Next, an oxide film sidewall 5 made of a silicon oxide film is formed on the side surfaces of each gate electrode 3 and the gate oxide film by using a CVD method and an etching technique. Next, a nitride film sidewall 6 made of a silicon nitride film is formed on the side surface of the oxide film sidewall 5 using a CVD method and an etching technique. Next, a high-concentration shallow impurity diffusion layer 4 is formed by photolithography and ion implantation at positions on both sides of each gate electrode 3 where the surface of the semiconductor substrate 1 is exposed.

  Next, as shown in FIG. 6B, a CVD oxide film 7 is formed as a silicide protection film for suppressing the silicide reaction by the CVD method.

  Next, as shown in FIG. 6C, a resist 8 is formed on the surface of the CVD oxide film 7 by photolithography in the non-silicide formation region Rnon. Thereafter, the CVD oxide film 7 in the silicide formation region Rsili is removed by anisotropic etching using the resist 8 as an etching mask. At this time, a double side wall 7 a is further formed outside the nitride film side wall 6 in the silicide formation region Rsili. Thereafter, the surface of the semiconductor substrate 1 is cleaned.

  Double side wall 7 a formed outside nitride film side wall 6 covers part of the region on impurity diffusion layer 4. In particular, when the interval between the adjacent gate electrodes 3 is narrow, the impurity diffusion layer sandwiched between the nitride film sidewalls 6 as between the two gate electrodes 3 in the silicide formation region Rsili in FIG. 4 is covered with this double side wall 7a.

  Next, after removing the resist 8, as shown in FIG. 6D, a refractory metal film 9 made of Ni, Co, Ti or the like is deposited on the entire surface of the semiconductor substrate 1 by sputtering or the like.

  Next, as shown in FIG. 7A, by applying an appropriate heat treatment, the silicide in the portion where the refractory metal film 9 is in contact with the gate electrode 3 and the impurity diffusion layer 4 in the silicide formation region Rsili. Then, a metal silicide layer 10 a is formed on the gate electrode 3 and a metal silicide layer 10 b is formed on the impurity diffusion layer 4. Thereafter, the unreacted refractory metal film 9 is removed by selective etching using sulfuric acid / hydrogen peroxide.

Through the manufacturing process as described above, a silicide element is formed in the silicide formation region Rsili and a non-silicide element is formed in the non-silicide formation region Rnon on the same semiconductor substrate 1.
JP 2004-146616 A

  However, in the conventional method of manufacturing a semiconductor device by the salicide process, when the interval between adjacent gate electrodes formed in the silicide formation region is narrow, the silicidation reaction is not performed normally or the junction leakage increases. There was a problem.

  Hereinafter, problems in the semiconductor device manufacturing method using the conventional salicide process will be described.

  FIG. 8A shows a cross-sectional view of the semiconductor device when the CVD oxide film 7 is formed in the step of FIG. In addition, the same code | symbol is used for the same component as FIG.6 (b).

  In the conventional method of manufacturing a semiconductor device by the salicide process, when the distance between adjacent gate electrodes 3 becomes narrower than a certain distance in the step of forming the CVD oxide film 7 shown in FIG. The film thickness of the CVD oxide film 7 in the region sandwiched between 3 is increased.

  In particular, as shown in FIG. 8A, in the region where the distance L1 between the nitride film sidewalls 6 of the adjacent gate electrodes 3 is narrower than twice the CVD oxide film thickness T1, both sides The CVD oxide film 7 grown from the above adheres, and the thickness of the CVD oxide film T2 between the narrow gate electrodes 3 becomes significant. When the film thickness ratio of T2 / T1 is larger than the overetching ratio of anisotropic etching in the process shown in FIG. 6C, the CVD oxide film 7 on the impurity diffusion layer 4 between the narrow gate electrodes 3 is It cannot be removed by anisotropic etching. Thereby, in the step of depositing the refractory metal film 9 shown in FIG. 6D, the double side wall 7a existing on the impurity diffusion layer 4 between the narrow gate electrodes 3 functions as a silicide protection film, and FIG. In the step shown in a), the silicidation reaction is not performed, and the resistance of the impurity diffusion layer and the contact resistance are increased.

  On the other hand, in the step of removing the CVD oxide film 7 by anisotropic etching shown in FIG. 6C, the amount of overetching of anisotropic etching that can remove the CVD oxide film 7 between the narrow gate electrodes 3 in the silicide formation region Rsili. Is set, the impurity diffusion layer 4 in a region where the interval between the adjacent gate electrodes 3 is wide is excessively etched.

  FIG. 8B shows a case where anisotropic etching is performed with an overetching amount that can remove the CVD oxide film 7 between the narrow gate electrodes 3 in the silicide formation region Rsili being set in the step of FIG. FIG. 8 shows a cross-sectional view of the semiconductor device after the step of performing the silicidation reaction of FIG. In addition, the same code | symbol is used for the same component as Fig.7 (a).

  In the step of FIG. 6C, when the impurity diffusion layer 4 is excessively etched, a damage layer is formed on the impurity diffusion layer 4 where the interval between the adjacent gate electrodes 3 is wide. When the silicidation reaction is performed after the damaged layer is formed, the abnormally grown metal silicide layer 10c is generated as shown in FIG. 8B, and junction leakage increases.

  Further, in order to secure the metal silicide layer 10b when the resist 8 is removed after the step shown in FIG. 6C, before the step of depositing the refractory metal film 9 shown in FIG. When the CVD oxide film 7a remaining between the gate electrodes 3 is removed by wet etching, the thickness of the CVD oxide film 7 in the non-silicide formation region Rnon is reduced.

  That is, since the etching rate of the CVD oxide film 7 in the non-silicide formation region Rnon is the same as the etching rate of the CVD oxide film 7a remaining between the narrow gate electrodes 3, only the amount necessary for removing the CVD oxide film 7a is obtained. The film thickness of the CVD oxide film 7 in the non-silicide formation region Rnon is reduced. As a result, in this case, it becomes impossible to secure the film thickness of the CVD oxide film 7 as the silicide protection film in the non-silicide formation region Rnon.

  The present invention solves the above-described conventional problems, and even when the gap between adjacent gate electrodes in a silicide formation region is narrow, the silicide element is formed on the same semiconductor substrate without increasing junction leakage of the impurity diffusion layer. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming both non-silicide elements and non-silicide elements.

  In order to solve the above-described problems, a first aspect of the present invention provides a method for manufacturing a semiconductor device, wherein a silicide region having a silicide element and a non-silicide region having a non-silicide element are formed on a semiconductor substrate. A gate electrode forming step of forming a plurality of gate electrodes on the substrate; a diffusion layer forming step of forming an impurity diffusion layer on the semiconductor substrate exposed from the gate electrode; and a semiconductor substrate including the gate electrode on the semiconductor substrate. A first insulating film forming step for forming one insulating film; a second insulating film forming step for forming a second insulating film by adding an impurity to the first insulating film formed on the non-silicide region; A first insulating film removing step of removing the first insulating film on the silicide region; a metal film depositing step of depositing a metal film on the semiconductor substrate; and A method of manufacturing a semiconductor device, characterized by comprising a silicide layer forming step of forming a metal silicide layer on the surface of the surface and the impurity diffusion layer of the gate electrode.

  The second aspect of the present invention is the method for manufacturing a semiconductor device according to the first aspect of the present invention, wherein the second insulating film has a slower etching rate than the first insulating film.

  According to a third aspect of the present invention, after the second insulating film forming step and before the first insulating film removing step, the surface of the second insulating film is masked to form the first insulating layer on the silicide region. The method for manufacturing a semiconductor device according to the first aspect of the present invention further includes a first insulating film etching step of retracting the insulating film.

According to a fourth aspect of the present invention, the impurity is at least one of boron, BF _{2, and} carbon, and the second insulating film forming step uses an ion implantation method. It is a manufacturing method of a semiconductor device of the present invention.

  The fifth aspect of the present invention is characterized in that the impurities are diffused in the second insulating film by performing a heat treatment after the second insulating film forming step and before the first insulating film removing step. A method for manufacturing a semiconductor device according to a fourth aspect of the present invention.

  According to a sixth aspect of the present invention, there is provided the method for manufacturing a semiconductor device according to the first aspect, wherein the first insulating film removing step uses wet etching.

  According to a seventh aspect of the present invention, in the method for manufacturing a semiconductor device, a silicide region having a silicide element and a non-silicide region having a non-silicide element are formed on a semiconductor substrate. Forming a gate electrode, forming a diffusion layer on the semiconductor substrate exposed from the gate electrode, and forming a first insulating film on the semiconductor substrate including the gate electrode. A first insulating film forming step; a second insulating film forming step of forming a second insulating film by adding an impurity to the first insulating film formed on the silicide region; and a second insulating film on the silicide region. A second insulating film removing step of removing metal, a metal film depositing step of depositing a metal film on the semiconductor substrate, a surface of the gate electrode on the silicide region, and a front surface A silicide layer forming step of forming a metal silicide layer on the surface of the impurity diffusion layer, a method of manufacturing a semiconductor device, characterized in that it comprises a.

  An eighth aspect of the present invention is the method for manufacturing a semiconductor device according to the seventh aspect of the present invention, wherein the second insulating film has a higher etching rate than the first insulating film.

  In the ninth aspect of the present invention, after the second insulating film forming step and before the second insulating film removing step, the surface of the first insulating film is masked to form the second insulating film on the silicide region. The method of manufacturing a semiconductor device according to the seventh aspect of the present invention, further comprising a second insulating film etching step of retracting the insulating film.

  The tenth aspect of the present invention is the method of manufacturing a semiconductor device according to the seventh aspect of the present invention, wherein the impurity is phosphorus, and the second electrode forming step uses an ion implantation method.

  The eleventh aspect of the present invention is characterized in that the impurity is diffused into the second insulating film by performing a heat treatment after the second insulating film forming step and before the second insulating film removing step. A method for manufacturing a semiconductor device according to a tenth aspect of the present invention.

  The twelfth aspect of the present invention is the method for manufacturing a semiconductor device according to the seventh aspect of the present invention, wherein the second insulating film removing step uses wet etching.

  According to the present invention, a semiconductor capable of forming both a silicide element and a non-silicide element on the same semiconductor substrate without increasing junction leakage of the impurity diffusion layer even when the interval between adjacent gate electrodes in the silicide formation region is narrow A device manufacturing method can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIGS. 1A to 1D and FIGS. 2A to 2C are cross-sectional views showing respective steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

  In FIGS. 1A to 1D and FIGS. 2A to 2C, the left side shows a silicide formation region Rsili for forming a silicide element, and the right side shows a non-silicide formation region Rnon for forming a non-silicide element. ing.

  Here, a case where two adjacent FETs are formed in the silicide formation region Sili on the semiconductor substrate 101 and one FET is formed in the non-silicide formation region Rnon will be described.

  FIG. 3 is a schematic diagram showing an enlarged cross section of a portion between two gate electrodes 3 formed in the silicide formation region Rsili in the step of FIG.

  A method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS.

  First, as shown in FIG. 1A, an element isolation oxide film 102 is formed on a semiconductor substrate 101 so as to surround a region to be activated by a LOCOS isolation method or an STI isolation method. Next, a gate oxide film (not shown) is grown on each active region surrounded by the element isolation oxide film 102 by thermal oxidation. Next, a polysilicon film is grown on the gate oxide film by a CVD method, and the polysilicon film is patterned by a photolithography method and a dry etching method to form a gate electrode 103. Here, two gate electrodes 103 are formed in the silicide formation region RSili, and one gate electrode 103 is formed in the non-silicide formation region Rnon.

  Next, an oxide film sidewall 105 made of a silicon oxide film is formed on the side surfaces of each gate electrode 103 and the gate oxide film by using a CVD method and an etching technique. Next, a nitride film sidewall 106 made of a silicon nitride film is formed on the side surface of the oxide film sidewall 105 by using a CVD method and an etching technique. Next, a high-concentration shallow impurity diffusion layer 104 is formed by photolithography and ion implantation at positions on both sides of each gate electrode 103 where the semiconductor substrate 101 is exposed.

  Next, as shown in FIG. 1B, a CVD oxide film 107 is deposited by a CVD method at 500 ° C. or lower. The CVD oxide film 107 is an example of the first insulating film of the present invention, and the step of depositing the CVD oxide film 107 corresponds to an example of the first insulating film forming process of the present invention.

  At this time, when the distance between the nitride film sidewalls 106 of the two adjacent gate electrodes 103 is smaller than twice the film thickness of the CVD oxide film 107, the CVD oxide film 107 grown from both sides adheres. The CVD oxide film 107 on the impurity diffusion layer 104 between the two gate electrodes 103 becomes thick.

  As shown in FIG. 3, the CVD oxide film thickness on the gate electrode 103 is T11, the distance between the nitride film sidewalls 106 of the two gate electrodes 103 is L11, the taper angle of the nitride film sidewall 106 is θ, and the CVD oxide film When the side wall coating ratio (coverage) of 107 is C11, the CVD oxide film thickness T12 on the impurity diffusion layer 104 between the two gate electrodes 103 can be approximated by the equation (1).

T12 = (T11 × C11−L11 / 2) × tan θ (1)
Here, assuming that the CVD oxide film thickness T11 is 50 nm, the distance L11 between the nitride film side walls 106 is 70 nm, the taper angle θ of the nitride film side wall 106 is 80 degrees, and the coverage C11 of the CVD oxide film 107 is 100%. The CVD oxide film thickness T12 on the impurity diffusion layer 104 between the two gate electrodes 103 is 85 nm.

  Next, as shown in FIG. 1C, a resist 108a is formed on the surface of the CVD oxide film 107 by photolithography in the silicide formation region Rsili. Thereafter, boron is implanted into the CVD oxide film 107 deposited in the non-silicide formation region Rnon by the ion implantation method using the resist 108a as an implantation mask, and the CVD oxide film 107b is altered.

  The step of transforming the CVD oxide film 107 into the CVD oxide film 107b corresponds to an example of the second insulating film forming step of the present invention, and the CVD oxide film 107b corresponds to an example of the second insulating film of the present invention.

  Next, after removing the resist 108a, heat treatment is performed to diffuse impurities into the CVD oxide film 107b in the non-silicide formation region Rnon. Thereafter, as shown in FIG. 1D, a resist 108b is formed on the surface of the CVD oxide film 107b by photolithography in the non-silicide formation region Rnon. Thereafter, the CVD oxide film 107 in the silicide formation region Rsili is removed by anisotropic etching using the resist 108b as an etching mask. In the anisotropic etching, just etching is performed on the film thickness of the CVD oxide film 107 so as not to damage the impurity diffusion layer 104. At this time, in the region where the distance L11 between the nitride film sidewalls 106 in the silicide formation region Rsili is 70 nm, the CVD oxide film 107 is not completely removed, and the 35 nm CVD oxide film 107a remains.

  Note that the step of retracting the CVD oxide film 107 in the silicide formation region Rsili by the anisotropic etching corresponds to an example of the first insulating film etching step of the present invention.

  Next, as shown in FIG. 2A, after the resist 108b is removed, the CVD oxide film 107a remaining in the silicide formation region Rsili is removed by wet etching. At this time, since the wet etching rate of the CVD oxide film 107b in the non-silicide formation region Rnon is slower than the CVD oxide film 107a in the silicide formation region Rsili, the CVD oxidation remaining between the two adjacent gate electrodes 103 in the silicide formation region Rsili. Even if sufficient overetching is performed on the film 107a, the CVD oxide film 107b in the non-silicide formation region Rnon remains. Taking the case where the distance between the nitride film side walls 106 is 70 nm as an example, even if the remaining 35 nm of the CVD oxide film 107a is overetched by about 50%, the non-silicide formation region Rnon is formed. The CVD oxide film 107b remains.

  The step of removing the CVD oxide film 107a remaining in the silicide formation region Rsili by this wet etching corresponds to an example of the first insulating film removal step of the present invention.

  Next, as shown in FIG. 2B, a refractory metal film 109 made of Ni, Co, Ti or the like is deposited on the entire surface of the semiconductor substrate 101 by sputtering.

  Next, as shown in FIG. 2C, by performing an appropriate heat treatment, the silicide in the portion where the refractory metal film 109 and the gate electrode 103 and the impurity diffusion layer 104 are in contact with each other in the silicide formation region Rsili. The metal silicide layer 110 a is formed on the gate electrode 103 and the metal silicide layer 110 b is formed on the impurity diffusion layer 104. At this time, since the CVD oxide film 107b functions as a silicide protection film in the non-silicide formation region Rnon, silicidation can be prevented. Thereafter, the unreacted refractory metal film 109 is removed by selective etching such as sulfuric acid / hydrogen peroxide.

  In this manner, a silicide element is formed in the silicide formation region Rsili on the same semiconductor substrate 101, and a non-silicide element is formed in the non-silicide formation region Rnon.

  According to the method for manufacturing the semiconductor device of the first embodiment, the CVD oxide film 107b having a slower etching rate than the CVD oxide film 107 is etched when the CVD oxide film 107a remaining between the adjacent gate electrodes 103 is removed. Since it functions as a stopper and a mask at the time of silicidation reaction, it is possible to achieve both securing of a metal silicide layer between narrow gate electrodes in the silicide region and prevention of silicidation reaction in the non-silicide region.

  Further, in the manufacturing method of the semiconductor device of the first embodiment, the impurity diffusion layer 104 is not damaged in the step of removing the CVD oxide film 107 in the silicide formation region Rsili in FIG. As described above, just etching is performed on the film thickness of the CVD oxide film 107, so that an increase in junction leakage of the impurity diffusion layer 104 does not occur.

In the step shown in FIG. 1C, boron is used as an impurity as a dopant to the CVD oxide film 107 in the non-silicide formation region Rnon, but the same effect can be obtained by using BF ₂ or carbon.

  In the first embodiment, the first insulating film etching step of just etching the CVD oxide film 107 by anisotropic etching is performed before the first insulating film removing step of removing the CVD oxide film 107a by wet etching. However, the first insulating film removal step is performed without performing the first insulating film etching step after the second insulating film forming step in which the CVD oxide film 107 is transformed into the CVD oxide film 107b. Also good. Even in this case, the CVD oxide film 107b has a slower etching rate than the CVD oxide film 107, and the same effect can be obtained.

(Embodiment 2)
4 (a) to 4 (d) and FIGS. 5 (a) to 5 (c) are cross-sectional views showing respective steps of the method of manufacturing a semiconductor device according to the second embodiment of the present invention. In addition, the same code | symbol is used for the same component as FIG. 1 and FIG.

  4A to 4D and FIGS. 5A to 5C, the left side shows a silicide formation region Rsili for forming a silicide element, and the right side shows a non-silicide formation region Rnon for forming a non-silicide element. ing. As in the first embodiment, here, a case where two adjacent FETs are formed in the silicide formation region Sili on the semiconductor substrate 1 and one FET is formed in the non-silicide formation region Rnon will be described.

  A method for manufacturing the semiconductor device according to the second embodiment will be described with reference to FIGS.

  First, as shown in FIG. 4A, an element isolation oxide film 102 is formed on a semiconductor substrate 101 so as to surround a region to be activated by a LOCOS isolation method or an STI isolation method. Next, a gate oxide film (not shown) is grown on each active region surrounded by the element isolation oxide film 102 by thermal oxidation. Next, a polysilicon film is grown on the gate oxide film by a CVD method, and the polysilicon film is patterned by a photolithography method and a dry etching method to form a gate electrode 103. Here, two gate electrodes 103 are formed in the silicide formation region RSili, and one gate electrode 103 is formed in the non-silicide formation region Rnon.

  Next, an oxide film sidewall 105 made of a silicon oxide film is formed on the side surfaces of each gate electrode 103 and the gate oxide film by using a CVD method and an etching technique. Next, a nitride film sidewall 106 made of a silicon nitride film is formed on the side surface of the oxide film sidewall 105 by using a CVD method and an etching technique. Next, a high-concentration shallow impurity diffusion layer 104 is formed by photolithography and ion implantation at positions on both sides of each gate electrode 103 where the semiconductor substrate 101 is exposed.

  Next, as shown in FIG. 4B, a CVD oxide film 201 is deposited by a CVD method at 500 ° C. or lower. At this time, when the distance between the nitride film sidewalls 106 of the two adjacent gate electrodes 103 is smaller than twice the film thickness of the CVD oxide film 201, the CVD oxide film 201 grown from both sides adheres. The CVD oxide film 201 on the impurity diffusion layer 104 between the two gate electrodes 103 becomes thick.

  Next, as shown in FIG. 4C, a resist 108 is formed on the surface of the CVD oxide film 201 by photolithography in the non-silicide formation region Rnon. Thereafter, using the resist 108 as an implantation mask, phosphorus is implanted into the CVD oxide film 201 deposited in the silicide formation region Rsili by ion implantation, and the CVD oxide film 201b is altered.

  The step of transforming the CVD oxide film 201 into the CVD oxide film 201b corresponds to an example of the second insulating film forming step of the present invention, and the CVD oxide film 201b corresponds to an example of the second insulating film of the present invention.

  Next, after removing the resist 108, heat treatment is performed to diffuse impurities into the CVD oxide film 201 b in the silicide formation region Rsili. Thereafter, in the non-silicide formation region Rnon, a resist is formed again on the surface of the CVD oxide film 201 by photolithography, and then the CVD oxide film 201b in the silicide formation region Rsili is anisotropically etched using the resist as an etching mask. Remove. In the anisotropic etching, just etching is performed on the thickness of the CVD oxide film 201b so as not to damage the impurity diffusion layer 104. At this time, as shown in FIG. 4D, the CVD oxide film 201b is not completely removed between the two adjacent gate electrodes 103 in the silicide formation region Rsili, and the CVD oxide film 201c remains. Then, the resist is removed.

  Note that the step of retreating the CVD oxide film 201b in the silicide formation region Rsili by the anisotropic etching is an example of the second insulating film etching step of the present invention.

  Next, as shown in FIG. 5A, the CVD oxide film 201c in the silicide formation region Rsili is removed by wet etching. At this time, since the wet etching rate of the CVD oxide film 201 in the non-silicide formation region Rnon is slower than the CVD oxide film 201c in the silicide formation region Rsili, the CVD oxidation remaining between the two adjacent gate electrodes 103 in the silicide formation region Rsili Even if the film 201c is sufficiently over-etched, it remains as the CVD oxide film 201a in the non-silicide formation region Rnon.

  The step of removing the CVD oxide film 201c remaining in the silicide formation region Rsili by this wet etching corresponds to an example of the second insulating film removal step of the present invention.

  Next, as shown in FIG. 5B, a refractory metal film 109 made of Ni, Co, Ti or the like is deposited on the entire surface of the semiconductor substrate 101 by sputtering.

  Next, as shown in FIG. 5C, by applying an appropriate heat treatment, the silicide in the portion where the refractory metal film 109 and the gate electrode 103 and the impurity diffusion layer 104 are in contact with each other in the silicide formation region Rsili. The metal silicide layer 110 a is formed on the gate electrode 103 and the metal silicide layer 110 b is formed on the impurity diffusion layer 104. At this time, since the CVD oxide film 201a functions as a silicide protection film in the non-silicide formation region Rnon, silicidation can be prevented. Thereafter, the unreacted refractory metal film 109 is removed by selective etching such as sulfuric acid / hydrogen peroxide.

  In this manner, a silicide element is formed in the silicide formation region Rsili on the same semiconductor substrate 101, and a non-silicide element is formed in the non-silicide formation region Rnon.

  According to the manufacturing method of the semiconductor device of the second embodiment, the etching rate of the CVD oxide film 201b in the silicide formation region Rsili is made faster than the etching rate of the CVD oxide film 201 in the non-silicide formation region, thereby forming the CVD oxide film 201c. Since the CVD oxide film 201 having a relatively slower etching rate functions as an etching stopper at the time of removing the CVD oxide film 201c remaining between the adjacent gate electrodes 103 and a mask at the silicidation reaction, it remains in the silicide region. It is possible to achieve both the removal of the CVD oxide film 201c and the securing of the CVD oxide film 201a in the non-silicide region, and the securing of the metal silicide layer between the narrow gate electrodes in the silicide region and the prevention of the silicidation reaction in the non-silicide region. it can.

  Further, in the method of manufacturing the semiconductor device of the second embodiment, the impurity diffusion layer 104 is not damaged in the step of removing the CVD oxide film 201b in the silicide formation region Rsili in FIG. 4D by anisotropic etching. Thus, since just etching is performed on the film thickness of the CVD oxide film 201b, an increase in junction leakage of the impurity diffusion layer 104 does not occur.

  In the second embodiment, the second insulating film etching step of just etching the CVD oxide film 201b by anisotropic etching is performed before the second insulating film removing step of removing the CVD oxide film 201c by wet etching. The second insulating film removing step is performed without performing the second insulating film etching step after the second insulating film forming step in which the CVD oxide film 201 is transformed into the CVD oxide film 201b. Also good. Even in this case, the CVD oxide film 201b has a higher etching rate than the CVD oxide film 201, so that the same effect can be obtained.

  In each of the embodiments, two FETs in the vicinity of the silicide formation region and one FET in the non-silicide region are formed on the same semiconductor substrate. However, the present invention is not limited to the FET and is close to the silicide region. The method for manufacturing a semiconductor device of the present invention can also be applied to the formation of silicide elements other than FETs.

  Further, there may be a plurality of silicide formation regions and non-silicide formation regions on the same semiconductor substrate, and if there are at least silicide elements in the same silicide formation region, the method for manufacturing a semiconductor device of the present invention can be applied. .

  The method of manufacturing a semiconductor device according to the present invention allows a silicide element and a non-silicide element to be formed on the same semiconductor substrate without increasing junction leakage of the impurity diffusion layer even when the gap between adjacent gate electrodes in the silicide formation region is narrow. Both of them can be formed, and are useful for a method of manufacturing a semiconductor device provided with a metal silicide layer.

Sectional drawing which shows the process of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. Sectional drawing which shows the process of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. The schematic diagram which shows the expanded cross section of the part between two gate electrodes formed in the silicide formation area | region in the process of FIG.1 (b) of the semiconductor device which concerns on Embodiment 1 of this invention. Sectional drawing which shows the process of the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. Sectional drawing which shows the process of the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. Sectional drawing which shows the process of the manufacturing method of the conventional semiconductor device Sectional drawing which shows the process of the manufacturing method of the conventional semiconductor device Sectional drawing which shows the subject of the conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Semiconductor substrate 102 Element isolation oxide film 103 Gate electrode 104 Impurity diffused layer 105 Oxide film side wall 107, 107a, 107b CVD oxide film 108, 108a, 108b Resist 109 Refractory metal film 110a, 110b Metal silicide layer 201, 201a, 201b , 201c CVD oxide film L11 Distance between nitride film sidewalls θ Nitride film sidewall taper angle T11 CVD oxide film thickness T12 CVD oxide film thickness

Claims (12)

In a method for manufacturing a semiconductor device, a silicide region having a silicide element and a non-silicide region having a non-silicide element are formed on a semiconductor substrate.
A gate electrode forming step of forming a plurality of gate electrodes on the semiconductor substrate;
A diffusion layer forming step of forming an impurity diffusion layer in the semiconductor substrate exposed from the gate electrode;
A first insulating film forming step of forming a first insulating film on the semiconductor substrate including the gate electrode;
A second insulating film forming step of forming a second insulating film by adding an impurity to the first insulating film formed on the non-silicide region;
A first insulating film removing step of removing the first insulating film on the silicide region;
A metal film deposition step of depositing a metal film on the semiconductor substrate;
And a silicide layer forming step of forming a metal silicide layer on the surface of the gate electrode and the surface of the impurity diffusion layer on the silicide region.   The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film has an etching rate slower than that of the first insulating film.   After the second insulating film forming step and before the first insulating film removing step, the first insulating film on the surface of the second insulating film is masked to recede the first insulating film on the silicide region. The method for manufacturing a semiconductor device according to claim 1, further comprising an etching step. The impurity is at least one of boron, BF ₂ or carbon,
The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film forming step uses an ion implantation method.   5. The semiconductor according to claim 4, wherein the impurity is diffused into the second insulating film by performing a heat treatment after the second insulating film forming step and before the first insulating film removing step. Device manufacturing method.   The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film removing step uses wet etching. In a method for manufacturing a semiconductor device, a silicide region having a silicide element and a non-silicide region having a non-silicide element are formed on a semiconductor substrate.
A gate electrode forming step of forming a plurality of gate electrodes on the semiconductor substrate;
A diffusion layer forming step of forming an impurity diffusion layer in the semiconductor substrate exposed from the gate electrode;
A first insulating film forming step of forming a first insulating film on the semiconductor substrate including the gate electrode;
A second insulating film forming step of forming a second insulating film by adding an impurity to the first insulating film formed on the silicide region;
A second insulating film removing step of removing the second insulating film on the silicide region;
A metal film deposition step of depositing a metal film on the semiconductor substrate;
And a silicide layer forming step of forming a metal silicide layer on the surface of the gate electrode and the surface of the impurity diffusion layer on the silicide region.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the second insulating film has an etching rate faster than that of the first insulating film.   After the second insulating film forming step and before the second insulating film removing step, the second insulating film is formed by retreating the second insulating film on the silicide region by masking the surface of the first insulating film. The method of manufacturing a semiconductor device according to claim 7, further comprising an etching step. The impurity is phosphorus;
The method of manufacturing a semiconductor device according to claim 7, wherein the second electrode forming step uses an ion implantation method.   11. The semiconductor according to claim 10, wherein the impurity is diffused into the second insulating film by performing a heat treatment after the second insulating film forming step and before the second insulating film removing step. Device manufacturing method. The method of manufacturing a semiconductor device according to claim 7, wherein the second insulating film removing step uses wet etching.