KR20040051697A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to prevent a damage to an LDD(lightly doped drain) ion implantation process or a source/drain ion implantation process by depositing a nitride thin film after a thermal oxide process for recovering gate etch damage is performed. CONSTITUTION: A semiconductor substrate(21) including an isolation layer and a well is prepared. A gate electrode is formed on the substrate. A thermal oxide process is performed on the resultant structure to grow a thermal oxide layer(25) of a thin film on the gate electrode and the substrate. A nitride layer is deposited on the thermal oxide layer. An LDD process and a halo ion implantation process are sequentially performed by using the nitride layer as a buffer layer so as to form an LDD region(28) and a halo region(29) on the substrate at both sides of the gate electrode. A spacer is formed on both sidewalls of the gate electrode. A source/drain ion implantation process using the nitride layer as a buffer layer again is performed to form a source/drain region(32) on the substrate at both sides of the gate electrode including the spacer. An insulation layer is deposited on the resultant structure. The insulation layer and the nitride layer under the insulation layer are etched to form a silicide blocking pattern(33) exposing the surface of the gate electrode and the surface of the source/drain region. A silicide layer(34) is formed on the exposed gate electrode and the source/drain region.

Description

Method of manufacturing semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for preventing ion implantation damage when forming a shallow junction.

Various technologies have been proposed to secure device characteristics according to high integration of semiconductor devices. For example, in order to improve the short channel effect due to the reduction of the gate line width, LDD (Lightly Doped Drain) and Shallow Junction forming techniques have been proposed, and the operation speed of the device through the reduction of the contact resistance has been proposed. A technique of selectively silicide film formation on the junction region and the gate electrode surface has been proposed to improve the efficiency.

Hereinafter, a method of fabricating a semiconductor device according to the related art to which the LDD and the shallow junction and the silicide film forming technology are applied will be described with reference to FIGS. 1A to 1E.

Referring to FIG. 1A, a device isolation film 2 is formed in the field region of the semiconductor substrate 1 to isolate the devices. Then, a well-ion implantation process is performed with the well mask 3 formed on the substrate 1 to form NMOS and PMOS devices.

Referring to FIG. 1B, after the gate oxide film 4a and the gate conductive film 4b are sequentially formed on the entire region of the substrate 1 in a state where the well-mask is removed, the gate electrode 4 is formed by etching them. do. Then, a thermal oxidation process is performed on the substrate resultant to recover etch damage. Here, reference numeral 5 denotes a thermal oxide film of a thin film grown by an oxidation process.

Referring to FIG. 1C, after the first ion implantation mask 6 is formed on the substrate 1, LDD ion implantation and halo ion implantation are performed, whereby both sides of the gate electrode 4 are formed. LDD regions 7 and halo regions 8 are formed in the substrate surface.

Referring to FIG. 1D, in a state where the first ion implantation mask is removed, the oxide film 9a and the nitride film 9b are sequentially formed on the substrate resultant, followed by blanket etching to form spacers on both sidewalls of the gate electrode 4. 9) form. Then, after the second ion implantation mask 10 is formed in place on the substrate 1, source / drain ion implantation is performed, and then, the substrate is annealed to activate the implanted impurities. The source / drain regions 11 are formed on the substrate surface on both sides of the gate electrode 4 including the < RTI ID = 0.0 >

Here, the second ion implantation mask 10 is preferably removed after source / drain ion implantation.

Referring to FIG. 1E, although not shown, the silicide blocking pattern (not shown) defining a region in which the silicide layer is to be formed is patterned by depositing an oxide film or a nitride film while the oxide film or the nitride film is deposited. Then, after depositing the transition metal film, the first heat treatment, the selective etching, and the second heat treatment are sequentially performed to form the silicide film 12 on the surface of the source / drain region 11 and the surface of the gate electrode 4. do.

Thereafter, in a state where the silicide blocking pattern is removed, a series of subsequent processes including a wiring process are performed to manufacture a semiconductor device.

However, according to the conventional method for manufacturing a semiconductor device described above, when performing LDD ion implantation, although the gate oxide film remains on the substrate surface at a predetermined thickness, this thickness is the ion implantation buffer in the fabrication of devices having a class of 0.25 μm or less. The thickness that cannot be applied as a buffer layer is thick, and in particular, because it is not uniform, it is caused by ion implantation in devices having 0.25 μm or less in which heavy atomic ions must be injected to form a shallow junction. Damage can not be avoided, and thus there is a problem in that device characteristics and reliability are deteriorated.

In addition, in the source / drain ion implantation, a buffer layer must be formed in order to minimize damage caused by ion implantation. In this case, the short channel effect is intensified due to the unnecessary thermal process.

In addition, since some excessive etching must be performed when the spacer is formed, there is a problem in that the substrate and the device isolation film are lost.

Accordingly, the present invention has been made to solve the above problems, to provide a method of manufacturing a semiconductor device that can prevent the loss of the substrate and the device isolation film when forming a spacer while preventing damage caused by ion implantation. There is a purpose.

1A to 1E are cross-sectional views of processes for explaining a method of manufacturing a semiconductor device according to the prior art.

2A through 2F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

21 semiconductor substrate 22 device isolation film

23: well mask 24a: gate oxide film

24b: gate conductive film 24: gate electrode

25: thermal oxide film 26: first nitride film

27: first ion implantation mask 28: LDD region

29 halo region 30a oxide film

30b: second nitride film 30: spacer

31: second ion implantation mask 32: source / drain region

33: silicide blocking pattern 34: silicide film

In order to achieve the above object, the present invention provides a semiconductor substrate having a device isolation film and a well; Forming a gate electrode on the substrate; Thermally oxidizing the substrate product to grow a thin thermal oxide film on the gate electrode and the substrate surface; Depositing a nitride film on the thermal oxide film; LDD and halo ion implantation are sequentially performed using the nitride film as a buffer film to form LDD regions and halo regions on the substrate surfaces on both sides of the gate electrode; Forming spacers on both sidewalls of the gate electrode; Source / drain ion implantation using the nitride film again as a buffer film to form source / drain regions on the substrate surfaces on both sides of the gate electrode including the spacers; Depositing an insulating film on the substrate resultant up to this step; Etching the insulating film and the nitride film thereunder to form a silicide blocking pattern exposing the gate electrode surface and the source / drain region surface; And forming a silicide film on the exposed gate electrode surface and the source / drain region surface.

Here, the nitride film is deposited to a thickness of 50 to 200 kPa by reacting any one Si-based gas selected from the group consisting of SiH 4, SiH 2 Cl 2, and Si 2 H 6 with NH 3 gas at a temperature of 600 to 800 ° C.

The forming of the spacer may include depositing an oxide film and a nitride film sequentially on the substrate resultant with a thickness of 50 to 200 kPa and 400 to 1000 kPa, dry etching the nitride film, and the oxide film as an HF-based solution. It consists of a step of excessive wet etching using.

The silicide blocking pattern insulating film is an oxide film or a nitride film. When the silicide blocking pattern insulating film is an oxide film, the oxide film is dry-etched with a high selectivity with the nitride film thereunder, and the nitride film is etched by phosphoric acid treatment. When the insulating film for the silicide blocking pattern is a nitride film, the nitride film and the nitride film functioning as an ion implantation buffer film are etched together.

According to the present invention, by forming the ion implantation buffer film of a nitride film only once before the ion implantation process, it is possible to prevent the occurrence of damage due to all subsequent ion implantation processes, and at the time of forming the spacer due to the presence of the ion implantation buffer film. It is possible to prevent substrate loss due to excessive etching.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to an embodiment of the present invention.

Referring to FIG. 2A, a trench type device isolation film 22 is formed in the field region of the semiconductor substrate 21 to isolate the devices according to a known process. Then, a well-ion implantation process is performed while the well mask 23 is formed on the substrate 21 to form NMOS and PMOS devices.

Referring to FIG. 2B, the gate oxide film 24a and the gate conductive film 24b are sequentially formed on the entire region of the substrate 21 in a state where the well-mask is removed, and then, they are etched by the device isolation film 2. The gate electrode 24 is formed on the active region of the limited substrate 21. Then, a thermal oxidation process is performed on the substrate product to recover the etch damage when the gate electrode 24 is formed. As a result of the thermal oxidation process, the thermal oxide film 25 is grown on the substrate surface including the gate electrode 24 in a thin film.

Next, the first nitride film 26 is deposited on the thermal oxide film 25 to a thickness of 200 kPa or less, preferably 50 to 200 kPa. Here, the first nitride layer 26 is deposited to function as an ion implantation buffer layer in a subsequent LDD ion implantation process, and Si-based gas such as SiH 4, SiH 2 Cl 2, or Si 2 H 6 and NH 3 at a temperature of 600 to 800 ° C. Deposition through the reaction of gas.

Referring to FIG. 2C, LDD ion implantation and halo ion implantation are performed using the first nitride layer 26 as an ion implantation buffer layer in a state where the first ion implantation mask 27 is formed in place on the first nitride layer 26. In turn, the LDD region 28 and the halo region 29 are formed in the substrate surface on both sides of the gate electrode 24.

Here, since the LDD ion implantation and the halo ion implantation are performed using the first nitride film 26 as an ion implantation buffer film, the generation of ion implantation damage is suppressed, and therefore, deterioration of device characteristics does not occur.

Referring to FIG. 2D, the oxide film 30a and the second nitride film 30b are sequentially deposited on the substrate resultant in the state where the first ion implantation mask is removed, with a thickness of 50 to 200 GPa and 400 to 1000 GPa, respectively.

Referring to FIG. 2E, after the second nitride film 30b is dry-etched, the oxide film 30a is subsequently wet-etched to form spacers 30 on both sidewalls of the gate electrode 2. Here, the wet etching of the oxide film 30a is performed by using a HF-based solution. At this time, the first nitride layer 26 that is not etched in the HF-based solution is present in the lower portion of the oxide film 30a. Sufficient etching can be achieved. Therefore, due to the presence of the first nitride layer 26, the loss of the substrate 21 and the device isolation layer 22 due to the excessive etching during the formation of the spacer 30 does not occur.

The spacer 30 may be formed of only one material of an oxide film or a nitride film, not a stacked structure of an oxide film and a nitride film.

Subsequently, the source / drain ion implantation is performed while the second ion implantation mask 31 is formed in place on the exposed first nitride film 26, and then the substrate is annealed to include the spacer 30. The source / drain regions 32 are formed on the substrate surfaces on both sides of the gate electrode 24.

Here, since the first nitride film 26 functions as an ion implantation buffer film at the time of source / drain ion implantation, the occurrence of ion implantation damage can be suppressed. In addition, since an additional oxidation step for forming an ion implantation buffer film is not necessary, deterioration of device characteristics due to a short channel effect does not occur.

On the other hand, the second ion implantation mask 31 is preferably removed after source / drain ion implantation.

Referring to FIG. 2F, that defines a region where a silicide film will be subsequently formed on the first nitride film 26. A silicide blocking pattern 33 is formed to expose the substrate surface and the gate electrode surface. Here, the silicide blocking pattern 33 is formed by sequentially performing a mask process and an etching process after depositing an oxide film or a nitride film.

In this case, when the deposited film is an oxide film, the etching is performed by dry etching with a high selectivity with the nitride film, followed by phosphoric acid treatment for an appropriate time to etch the first nitride film 26 functioning as an ion implantation buffer film. . On the other hand, when the deposited film is a nitride film, the first nitride film 26 is etched together during the etching.

Next, a transition metal film is deposited on the substrate product up to the above step, and then the first and second heat treatments, the selective etching, and the second heat treatment are sequentially performed on the substrate product, so that the surface of the source / drain region 32 and the gate electrode ( The silicide film 34 is formed on the surface of the substrate 24.

Thereafter, a series of subsequent processes including a wiring process are performed in a state where the silicide blocking pattern is removed to manufacture a semiconductor device.

Meanwhile, in the above-described embodiment of the present invention, when the thickness of the nitride film deposited as the initial buffer film is thickened within the above range, the nitride film may be left until the silicide metal film is deposited, in which case, a separate silicide The etching process may be performed without deposition of the insulating film for blocking pattern.

As described above, the present invention deposits a nitride film of a thin film after a thermal oxidation process for recovering gate etching damage, thereby preventing the occurrence of ion implantation damage during LDD ion implantation and source / drain ion implantation due to the presence of the nitride film. In addition, it is possible to prevent the loss of the substrate and the device isolation film during the excessive etching for the formation of the spacer, and also to remove the unnecessary thermal process of about 600 ~ 750 ℃ causing the short channel effect after ion implantation By doing so, the short channel effect can be prevented from appearing.

Therefore, the present invention can improve the leakage current characteristics of the device, thereby improving the device characteristics and reliability.

In addition, since the nitride film of the thin film can be used as an insulating film for the silicide blocking pattern, further film deposition can be reduced.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (8)

Providing a semiconductor substrate having an isolation layer and a well; Forming a gate electrode on the substrate; Thermally oxidizing the substrate product to grow a thin thermal oxide film on the gate electrode and the substrate surface; Depositing a nitride film on the thermal oxide film; LDD and halo ion implantation are sequentially performed using the nitride film as a buffer film to form LDD regions and halo regions on the substrate surfaces on both sides of the gate electrode; Forming spacers on both sidewalls of the gate electrode; Source / drain ion implantation using the nitride film again as a buffer film to form source / drain regions on the substrate surfaces on both sides of the gate electrode including the spacers; Depositing an insulating film on the substrate resultant up to this step; Etching the insulating film and the nitride film thereunder to form a silicide blocking pattern exposing the gate electrode surface and the source / drain region surface; And Forming a silicide film on the exposed gate electrode surface and the source / drain region surface. The method of manufacturing a semiconductor device according to claim 1, wherein the nitride film is deposited to a thickness of 50 to 200 GPa. The semiconductor device of claim 1, wherein the nitride film is deposited by reacting any one of Si-based gas selected from the group consisting of SiH 4, SiH 2 Cl 2, and Si 2 H 6 with NH 3 gas at a temperature of 600 to 800 ° C. 6. Way. The method of claim 1, wherein forming the spacer Sequentially depositing an oxide film and a nitride film on the substrate resultant; Dry etching the nitride film; And A method of manufacturing a semiconductor device, characterized in that the oxide film comprises a step of excessive wet etching using a solution of the HF series. The method of manufacturing a semiconductor device according to claim 4, wherein the oxide film and the nitride film are deposited to have a thickness of 50 to 200 mW and 400 to 1000 mW, respectively. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film for the silicide blocking pattern is an oxide film or a nitride film. The method of claim 6, wherein when the insulating film for the silicide blocking pattern is an oxide film, And dry etching the oxide film with a high selectivity with the nitride film thereunder, and then etching the nitride film by phosphoric acid treatment. The insulating film for silicide blocking pattern is a nitride film, And etching the nitride film functioning as the nitride film and the ion implantation buffer film together.