‘1255553 九、發明說明： 【發明所屬之技術領域】 本么月係關於-種碎覆部分絕緣場效電晶體及其製作方 【先前技術】 集合關、歐洲、台灣、日本和韓國之半導體技術協會 (SIA)之專家所共同制訂之國際半導體技術藍圖，訂出未來 # 冑作奈米金屬氧化半導體元件技術之方向，也點出了一些 瓶頸：對於傳統C刪製程來講，最嚴重的問題㈣刪) 可能是漏電流問題，太多的寄生州接面電容與嚴重的超短 通道效應、。參考圖，習知之金屬氧化半導體裝置10 包括：一基板11、一本體12、_源極13、一汲極14、一閘 極氧化層15及-閘極16。該本體12與該基板n為一體或形 成於該基板11上。該源㈣及該沒極14形成於該基板 - 且設置於該本體12之側邊。若該基板11與該本體12為1>型， • 該源極13及該汲極14為N+型，故PN接面之區域過大，而造 成漏電流太大之問題與太多的寄生pN接面電容。另外，在 忒白知孟屬氧化半導體裝置丨〇之該源極丨3及該汲極14間之 通道1 7具有嚴重的超短通道效應。 苓考圖2所不，其顯示習知具有矽覆絕緣s〇I基板之金屬 氧化半導體裝置20。該習知之金屬氧化半導體裝置2〇包 括· 一基板21、一本體22、一源極23、一汲極24、一閘極 氧化層25及一閘極26。該基板21具有一基底211及一埋入氧 化層212。利用埋入氧化層212減少pN接面，以減少漏電流 100435.doc 1255553 寄生PN接面電谷。習知的石夕覆絕緣金屬氧化半導體裝置 料舒緩超短通道效應，但為了進一步解決漏電流、寄 生電容與超短通道問題，卻完全仰賴超薄厚度的石夕薄層。 、然因為S01具有-完全隔離石夕薄層之埋入氧化層（Buned _ 〇xld中散熱不易而造成通道層之帶電載子嚴重地被自我 加熱兀件和系統之性能也因此大幅降低。同時也產生了 金屬氧化半導體裝置的Η檻啟動電壓（Thi*esh〇ld VGltage)對 鲁超薄矽薄層厚度不均勻性之嚴重敏感問題。 〃目刖解決上述問題的方法並不多見，而同時能夠解決漏 電机、寄生電容與超短通道效應、自我加熱效應、浮體 (Floating body effect)與屈膝效應（Kink Effect)及單拴走火 效應（Single iatch up)六大問題之方法亦屬稀有。如前所 述，若針對PN接面做有效的阻隔降同時也能讓本體與基板 相連接，如此一來上述問題方可徹底解決。最近在會議期 ' 刊上有被提出使用淺溝渠濕式蝕刻製作源極、汲極部分埋 參 入氧化層之假半導覆絕緣（SOI)場效電晶體來實行，側面的 漏電流與寄生接面電容仍無解決。此外為解決厚度均勻性 的超薄石夕薄膜問題有專利被提出，也有利用比較好之主動 區旁側絕緣材質來減低隔離島之漏電流（如美國專利第 5,〇34,789號第5,053,353號及第6,825,529號）。解決自我加熱 效應問題之專利，幾乎沒有。解決浮體與屈膝效應問題之 專利（如美國專利第6,746,937號，第6,794,716號），大都是 利用具有浪費面積的本體缚點端（Body tie)的元件架構。另 外，美國專利第6,770,540號雖改善浪費面積的缺點，但其 100435.doc * 1255553 閘極與源極、汲極間人 ^ 勒效;》n Bp 、, D 谷太大會造成頻率操作時有米 勒效應問通。吳國專利號第6,218,249號 示雖然能製得純能較佳之大，，3155虎揭 傳#夕八Μ斤 不未凡件，然而因為都是利用 … 减半導體架構和傳統之SCH架構配合超淺接 面深度’但也都未能同時減輕或解決上述提出的問題。 、^專f之部分空切覆絕緣金氧半裝置（PD_會有漏電 &及接面電容大’主要來自於太多之底部與旁側pN接面； 且會有自我加熱效應和浮體效應’主要S沒有通道連接可 散熱和可騎積聚碰撞游離載子之本體至基底。故本發明 以發明之雙邊襯技術同時製作源/汲極底部與側面之内部 阻絕部來杜絕PN接面而僅留極淺之表面部分當通道層 (Channel layer)供裝置電流流通，同時預留適當寬度之垂直 本體通道用於散熱和排除浮體效應而無須製作極淺接面深 度之源/汲極’且可鬆弛對均勾超薄石夕薄膜厚度之嚴格需 求0 因此’有必要提供-種創新且具進步性的⑦覆部分絕緣 場效電晶體，以解決上述問題。 【發明内容】 本發明之一目的在於提供一種矽覆部分絕緣場效電晶 體，其包括：一基板、一本體通道、一内部阻絕部、一閘 極氧化部、一閘極部、一源極部及一汲極部。該本體通道 形成於該基板之上。該内部阻絕部係呈L形，形成於該基板 上且设置於该本體通道之側邊。該閘極氧化部形成於該本 體通道上。該閘極部形成於該閘極氧化部上。該源極部及 100435.doc 1255553 S亥及極部係形成於該内部阻 ,,0I丨、'邑°卩上，並於部分該本體通道 之側邊。 本發明之另一目的在於提供一 ^ . ^ 種夕覆邻分絕緣場效電晶 體之製作方法，包括以下步驟：（ ()扣（、一基板；（b)依序形 成閘極氣化層、一閘極層及一氧化η Θ 乳化犧牲層於該基板上； (C)形成一邊襯光罩於該氧化犧 ^ 、 俄狂層上，（d)利用該邊襯光 罩，/刀別於該氧化犧牲層、閘極声 片 閘位層及该閘極氧化層形成一 :犧牲部、一間極氧化部及一間極部；⑷形成一閉極保 以於該閘極部之側邊；（f刚自動對齊，於該基板形成 本體通道；（g)形成—内部阻絕部於該基板上且於該本體 通道之側邊；及⑻形成-源極部及1極部，於該内部阻 絕部上，並於部分該本體通道之側邊。 本發明之石夕覆部分絕緣場效電晶體係利用該内部阻絕部 介入該本體通道與該源極部、該汲極部之間，以取代原來 之廣大的底部與旁側PN接面，可降低金屬氧化半導體裝置 中PN接面的面積而大幅降低漏電流與⑼接面電容。並且， 經由適當選擇材質，也同時能夠解決或終止習知金屬氧化 半導體裝置之PN接面之電場及麼制其造成之元件空乏區向 本體延展’進而可以同㈣制超短通道效應。因為本發明 之石夕覆部分絕緣場效電晶體具有本體通道，故沒有浮體效 應及自我加熱效應。在製作方法上’由於開極部、内部阻 絕部及源極部與汲極部係以自我對齊之方式形成，可確實 達到裝置微小化之目的。 、 【實施方式】 100435.doc -1255553 。月芩閱圖3，其顯示本發明矽覆部分絕緣場效電晶體之示 思圖。本發明矽覆部份絕緣場效電晶體30包括：包括：一 基板31、一本體通道311、一内部阻絕部％、一閘極氧化部 - 32、、一閘極部33、一源極部37及一汲極部38。該基板”可 - 為為矽、鍺或in—v族晶圓基板。該本體通道311形成於該 基板3 1之上。 該内部阻絕部36係呈L形，形成於該基板3丨上且設置於該 % 本體通道3 11之側邊。該内部阻絕部36之材質係選自由二氧 化矽、氮化矽、氧氮氧（0N0)、空氣腔（Air Gap)、具有不 同払雜雜質濃度之金屬石夕化物、或金屬所組成之群。 ”亥閘極氧化部32形成於該本體通道3 11上。該閘極部33形 成於該閘極氧化部32上。該閘極部33可為一多晶矽層，亦 可具有一金屬矽化物層及一多晶矽層，該金屬矽化物層係 於該多晶矽層上，該閘極部33係形成相對於該本體通道3 i i • 上。該閘極部33也可具有至少一中能隙（Mid_Gap)金屬層， • 亦即該閘極部33可為一中能隙金屬層或多層中能隙金屬層 之組合。 本發明矽覆部分絕緣場效電晶體3〇另包括一金屬矽化物 部34 ’形成於該閘極部33上。本發明矽覆部份絕緣場效電 晶體30另包括一閘極保護部35，該閘極保護部35為氮化矽 層或低K材質之組合層，該閘極保護部35用以覆蓋保護該閘 極部33之側邊，該閘極保護部35之厚度為5nm至50 nm。 該源極部37及該汲極部38係形成於該内部阻絕部36上， 並於部分該本體通道3 11之側邊。該本體通道3 11之側邊具 100435.doc •1255553 有一淺層通道口 3 12，該源極部37及該汲極部38係形成於該 該本體通道311之淺層通道口 312之側邊。該淺層通道口 312 之厚度為0.5 nm至30 nm之間。本發明矽覆部分絕緣場效電 ~ 晶體3〇另包括一源極接觸層371及一汲極接觸層38ι，分別 形成於該源極部3 7及該汲極部3 8上。該金屬；δ夕化物部3 4、 該源極接觸層371及該汲極接觸層38 1，可由金屬石夕化製程 同時形成，係為金屬石夕化層。 φ 本發明之矽覆部份絕緣場效電晶體係利用該内部阻絕部 36介入該本體通道311與該源極部37、該汲極部％之間，以 取代原來之廣大的底部與旁側PN接面，可降低金屬氧化半 導體裝置中PN接面的面積而大幅降低漏電流與pN接面電 容。並且，經由適當選擇材質，也同時能夠解決或終止習 知金屬氧化半導體裝置之PN接面之電場及壓制其造成之元 件空乏區向本體延展，進而可以同時壓制超短通道效應。 j 另外，因為本發明之矽覆部分絕緣場效電晶體具有本體通 • 道311，故沒有浮體效應及自我加熱效應。 參考圖4A至4E，其顯示本發明矽覆部份絕緣場效電晶體 之製作方法示意圖。首先參考圖4A，提供一基板4ι，在完 •«準清洗步驟與完成Z⑽光罩製程後，以任何隔離技術 (例如：利用局部氧化隔離技術L0C0S或淺溝槽隔離技術 STI)配合主動區光罩定義形成裝置之主動區。 再以熱氧化法成長以形成—閘極氧化層42於該基板41 上。該閘極氧化層之厚度為〇.5nm至2nm之間，該閉極氧化 層42係為二氧化矽層或高K值介電材料層。 100435.doc -10- •1255553 然後，以電漿輔助化學氣相沉積（PECVD)、低溫低壓之 本氣相/儿積（LPC VD)或濺鑛方法形成一閘極層43於該閘 極氧化層42上。該閘極層43可為一多晶矽層，亦可為單層 =多層金屬，亦可包括一多晶矽層及一金屬矽化物層，該 ' ^屬碎化物層係形成於該多晶石夕層上。再以低溫低壓之化 予氣相沉積方法形成一氧化犧牲層44於該閘極層U上。 、再以電漿輔助化學氣相沉積方法形成一多晶矽層45於部 _ 刀之忒氧化犧牲層44上，再以低溫低壓之化學氣相沉積方 法地毯式形成一氮化矽層於該多晶矽層及該犧牲氧化層 上，以活性離子颠刻技術姓刻該氮化石夕層，以形成該邊概 光罩46。 利用等方向性濕式韻刻或活性離子钱刻技術剝除該多晶 矽層=5。再以活性離子蝕刻技術蝕刻該氧化犧牲層料以形 成一氧化犧牲部47。剝除氮化矽邊襯光罩46，並以該氧化 — 犧牲部47為硬光罩⑽rdMask)，以活性料_技_刻 • _極層43及該閘極氧化層42，以形成-閘極部53及一問 極氧化^ 52。再地毯式成長一氮化石夕層，然後再利用邊概 ㈣以活性離子㈣方法㈣該氮切層以形成—閑極保 濩邛55。再以該剩餘氧化犧牲部47及該閘極保護部兄為遮 罩，利用活性離子蝕刻方法蝕刻該基板4丨至一設定深度， 以形成一本體通道511，如圖4B所示。 參考圖4C，地毯式成長一内部阻絕層48，再地毯式成長 一第一多晶矽層49於該内部阻絕層48上。參考圖41)，以^ 性離子姓刻方法姓刻該第-多晶石夕層49，使該内部阻絕層 100435.doc -11- .1255553 4 8曝硌其ι度，再以活性離子蝕刻方法蝕刻該内部阻絕層 48至該本體通道511之側邊，以形成一内部阻絕部％，並暴 鉻部分该本體通道511之側邊，為一淺層通道口 512。 _ 參考圖4E，係以電漿辅助化學氣相沉積（PECVD)、低溫 低壓之化學氣相沉積（LPCVD)或濺鍍方法地毯式成長一第 二多晶矽層，再以活性離子蝕刻方法蝕刻該第二多晶矽 層，以形成一源極部57及一汲極部58於該淺層通道口 512 _ 側邊另外，可以逑擇性蟲晶成長技術形成該源極部5 7及 該汲極部58於該淺層通道口 512側邊。之後，可以利用一活 性離子蝕刻步驟，蝕刻該源極部57及該汲極部58，使該源 極部57及该汲極部58之最高高度大於或等於該本體通道 511之隶南而度。 之後，先長一薄層二氧化矽散射層，再利用一離子佈值 技術配和一熱修復步驟，形成一源極接面及一汲極接面， - 分別於該源極部57與該淺層通道口 512之間，及該汲極部58 # 與該淺層通道口 512之間。在形成該源極部57及該汲極部58 之步驟中，係利用該閘極部5 3為一遮罩，配合離子佈值用 之該二氧化矽散射層，自我對準形成該源極部57及該汲極 •部 58 〇 接著，進行金屬矽化技術，首先以活性離子蝕刻技術或 以濕姓刻技術剝除閘極部53上面之氧化犧牲部47之硬光罩 (Hard mask)和離子佈植用之二氧化矽散射層，使閘極多晶 石夕和加厚之源/汲極同時暴露出。然後地毯式蒸鑛金屬鎳， 亦可為生成金屬矽化物之其他金屬。然後進行以適當溫度 100435.doc -12- 1255553 之驅入，使在源極部57及該汲極部58上分別形成—源極接 觸層571及一汲極接觸層58卜該源極接觸層571及該汲極接 觸層58 1係為金屬石夕化層（Silicide)，同時在閘極部53上形成 一金屬石夕化物部54(Polyside)，且無須光罩。 再地毯式成長TEOS ’或其他如含磷硼之矽氧化物玻螭 (BPSG)，或其他低K值材料作為保護層，之後再利用習知 的接觸窗和金屬連線的製程技術來完成製作本發明矽覆部 份絕緣場效電晶體50。 本發明之金屬氧化半導體裝置50可應用於低成本之傳統 石夕晶圓基板上，以大幅降低製作高性能電路與單晶片系統 之成本。依據上述實施例之製作方法可知本發明僅利用單 -光罩形成該氮化矽邊襯光罩46,其他都是以自我對齊完 成整個製程。因此，本發明之金屬氧化半導體裝置5〇可節 省成本又可解決漏電流問題、寄生接面電容太大問題、浮 體效應問題、自我加熱效應問題、寄生串接電阻太大問題、 超短通道效應問題與單检效應等問題。 惟上述實_僅為說明本發明之原理及其功效，而非用 以限制本發明。因此，習於此技術之人士可在不違背本發 明之精神對上述實施例進行修改及變化。本發明之權利範 圍應如後述之申請專利範圍所列。 【圖式簡單說明】 圖1為習知金屬氧化半導體裝置之示意圖； 圖2為習知具有埋入氧化層之金屬氧化半導體裝置之示 100435.doc -1255553 圖3為本發明矽覆部份絕緣場效電晶體之示意圖； 圖4 A至4E為本發明矽覆部份絕緣場效電晶體之製作方 法示意圖。 【主要元件符號說明】 10 習知之金屬氧化半導體裝置 11 基板 12 13 14 15 16 17 20 21 22 23 24 25 26 30 31 32 33 34'1255553 IX. Description of the invention: [Technical field of invention] This month is about a kind of fragmented partially insulated field effect transistor and its maker [Prior Art] Semiconductor technology of Huiguan, Europe, Taiwan, Japan and Korea The international semiconductor technology blueprint jointly developed by the experts of the Association (SIA) sets out the future direction of the technology of nano-metal oxide semiconductor devices, and also points out some bottlenecks: the most serious problem for the traditional C-cut process (4) Delete) It may be a leakage current problem, too many parasitic state junction capacitances and severe ultra-short channel effects. Referring to the drawings, a conventional metal oxide semiconductor device 10 includes a substrate 11, a body 12, a source 13, a drain 14, a gate oxide layer 15, and a gate 16. The body 12 is integral with or formed on the substrate 11. The source (4) and the gate 14 are formed on the substrate - and are disposed on the side of the body 12. If the substrate 11 and the body 12 are of the type 1>, the source 13 and the drain 14 are of the N+ type, so that the area of the PN junction is too large, and the leakage current is too large to be connected with too many parasitic pNs. Surface capacitance. In addition, the source 丨3 between the source 丨3 and the drain 14 of the 氧化 知 属 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Referring to Fig. 2, there is shown a metal oxide semiconductor device 20 having a conventionally insulated silicon substrate. The conventional metal oxide semiconductor device 2 includes a substrate 21, a body 22, a source 23, a drain 24, a gate oxide layer 25, and a gate 26. The substrate 21 has a substrate 211 and a buried oxide layer 212. The buried oxide layer 212 is used to reduce the pN junction to reduce leakage current. 100435.doc 1255553 Parasitic PN junction electric valley. The well-known Shixi-covered insulating metal oxide semiconductor device is used to soothe the ultra-short channel effect, but in order to further solve the problems of leakage current, parasitic capacitance and ultra-short channel, it relies entirely on the thin thickness of the Shi Xi thin layer. However, because S01 has a fully isolated oxide layer embedded in the thin layer (the Buned _ 〇xld heat dissipation is not easy, the charged carrier of the channel layer is seriously self-heated, and the performance of the system is greatly reduced. The Η槛 startup voltage of the metal oxide semiconductor device (Thi*esh〇ld VGltage) is also seriously sensitive to the thickness unevenness of the ultra-thin thin layer. It is rare to see the above problems. At the same time, it is also rare to solve the six problems of leakage motor, parasitic capacitance and ultra-short channel effect, self-heating effect, floating body effect and Kink effect and single iatch up. As mentioned above, if the effective barrier drop is made for the PN junction, the body can be connected to the substrate, so that the above problems can be completely solved. Recently, during the conference period, it was proposed to use shallow trenches and wet. The etched source is fabricated by a dummy semi-conductive insulating (SOI) field effect transistor in which the source and drain portions are buried in the oxide layer. The leakage current on the side and the parasitic junction capacitance remain unresolved. In addition, a patent has been proposed to solve the problem of ultra-thin stone film thickness uniformity, and a relatively good active area side insulation material is also used to reduce the leakage current of the isolation island (for example, U.S. Patent No. 5, No. 5, 053, No. 5,053,353 and No. 6,825,529. There is almost no patent for solving the problem of self-heating effect. The patents for solving the problem of floating body and knee flexion (such as U.S. Patent No. 6,746,937, No. 6,794,716) mostly utilize the body end point with waste area ( The component structure of the body tie. In addition, U.S. Patent No. 6,770,540 improves the waste area, but its 100435.doc * 1255553 gate and source, bungee ^ ^ effect; "n Bp,, D Gu Tai At the time of the frequency operation, there is a Miller effect. Wu Guobiao No. 6,218,249 shows that although it can produce pure and better, the 3155 Tiger reveals that #夕八Μ斤 is not the case, but because it is used ... reduce the semiconductor architecture and the traditional SCH architecture with the ultra-shallow junction depth' but also fail to alleviate or solve the above-mentioned problems at the same time. The device (PD_ has leakage & and the junction capacitance is large) mainly comes from too many bottom and side pN junctions; and there will be self-heating effect and floating body effect 'main S no channel connection can dissipate heat and ride Accumulating the body of the collision free carrier to the substrate. Therefore, the invention uses the double lining technique of the invention to simultaneously fabricate the internal barrier portion of the source/drain bottom and the side to eliminate the PN junction and leave only the extremely shallow surface portion as the channel layer (Channel Layer) for the device current to circulate, while preserving the vertical body channel of appropriate width for heat dissipation and elimination of the floating body effect without the need to make a source of very shallow junction depth / bungee' and can relax the ultra-thin thin film thickness Strict demand 0 Therefore, it is necessary to provide an innovative and progressive 7-layer partially insulated field effect transistor to solve the above problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a covered partially insulated field effect transistor, comprising: a substrate, a body channel, an internal blocking portion, a gate oxide portion, a gate portion, and a source Ministry and a pole. The body channel is formed over the substrate. The internal blocking portion is L-shaped and formed on the substrate and disposed on a side of the body passage. The gate oxidized portion is formed on the body passage. The gate portion is formed on the gate oxide portion. The source portion and the 100435.doc 1255553 S and the pole portions are formed on the internal resistance, 0I 丨, '邑°卩, and on the side of the portion of the body passage. Another object of the present invention is to provide a method for fabricating a luminescent sub-isolated field-effect transistor, comprising the steps of: () deducting (a substrate; (b) sequentially forming a gate gasification layer a gate layer and an oxidized η 乳化 emulsified sacrificial layer on the substrate; (C) forming a side lining on the oxidized sacrificial layer, the Russian mad layer, (d) using the edge lining, / knife Forming a sacrificial portion, a pole oxidizing portion and a pole portion in the oxidized sacrificial layer, the gate acoustic film gate layer and the gate oxide layer; (4) forming a closed end to protect the side of the gate portion (f is just automatically aligned to form a body channel on the substrate; (g) forming an internal blocking portion on the substrate and on a side of the body channel; and (8) forming a source portion and a pole portion, The internal blocking portion is located on a side of the body channel. The portion of the insulative field effect electric crystal system of the present invention is interposed between the body channel and the source portion and the drain portion by the internal blocking portion. In order to replace the original bottom and side PN junctions, the PN connection in the metal oxide semiconductor device can be reduced. The area is greatly reduced by the leakage current and (9) junction capacitance. Moreover, by appropriately selecting the material, the electric field of the PN junction of the conventional metal oxide semiconductor device can be solved or terminated, and the component depletion region is extended to the body. 'Then can be the same as (4) ultra-short channel effect. Because the stone-covered partially-insulated field effect transistor of the invention has a body channel, there is no floating body effect and self-heating effect. In the manufacturing method, 'because of the open part and the internal resistance The part, the source part and the bungee part are formed in a self-aligning manner, and the device can be surely miniaturized. [Embodiment] 100435.doc -1255553. See Figure 3 for a review of the present invention. The insulating field effect transistor 30 includes: a substrate 31, a body channel 311, an internal barrier portion, a gate oxide portion - 32, A gate portion 33, a source portion 37 and a drain portion 38. The substrate "may be" a germanium, germanium or in-v family wafer substrate. The body channel 311 is formed on the substrate 31. The The partial blocking portion 36 is L-shaped and formed on the substrate 3A and disposed on the side of the % body passage 31. The material of the internal blocking portion 36 is selected from the group consisting of cerium oxide, cerium nitride, oxygen oxynitride. (0N0), an air chamber (Air Gap), a group of metal cerium compounds having different concentrations of impurity impurities, or a group of metals. "The sluice gate oxidation portion 32 is formed on the body passage 3 11. The gate portion 33 is formed on the gate oxidization portion 32. The gate portion 33 may be a polysilicon layer, or may have a metal telluride layer and a polysilicon layer, the metal halide layer is on the polysilicon layer, the gate The portion 33 is formed with respect to the body passage 3 ii. The gate portion 33 may also have at least one medium gap (Mid_Gap) metal layer, that is, the gate portion 33 may be a medium gap metal layer or A combination of multi-layer gap metal layers. The covered partially insulated field effect transistor 3 of the present invention further includes a metal germanide portion 34' formed on the gate portion 33. The partial insulating field effect transistor 30 of the present invention further includes a gate protection portion 35 which is a combination layer of a tantalum nitride layer or a low K material, and the gate protection portion 35 is used for covering protection. The side of the gate portion 33 has a thickness of 5 nm to 50 nm. The source portion 37 and the drain portion 38 are formed on the internal blocking portion 36 and on a side of the portion of the body passage 31. The side of the body channel 3 11 has a shallow channel opening 3 12 , and the source portion 37 and the drain portion 38 are formed on the side of the shallow channel opening 312 of the body channel 311 . . The shallow channel opening 312 has a thickness between 0.5 nm and 30 nm. In the present invention, a portion of the insulating field effect transistor 301 further includes a source contact layer 371 and a drain contact layer 38 ι formed on the source portion 37 and the drain portion 38, respectively. The metal; the delta layer portion 34, the source contact layer 371, and the gate contact layer 38 1 may be simultaneously formed by a metal-stone process, and is a metal-stone layer. φ The partially insulated field effect electric crystal system of the present invention is interposed between the main body channel 311 and the source portion 37 and the drain portion by the internal blocking portion 36 to replace the original bottom and side The PN junction reduces the area of the PN junction in the metal oxide semiconductor device and significantly reduces leakage current and pN junction capacitance. Moreover, by appropriately selecting the material, the electric field of the PN junction of the conventional metal oxide semiconductor device can be solved or terminated, and the element depletion region caused by the suppression can be extended to the body, thereby suppressing the ultrashort channel effect at the same time. Further, since the partially insulated field effect transistor of the present invention has the body passage 311, there is no floating body effect and self-heating effect. Referring to Figures 4A through 4E, there are shown schematic views of a method of fabricating a partially insulated field effect transistor of the present invention. Referring first to FIG. 4A, a substrate 4i is provided, and after the "pre-cleaning step" and the completion of the Z(10) mask process, the active area light is combined with any isolation technique (for example, using local oxidation isolation technology L0C0S or shallow trench isolation technology STI). The hood defines the active area of the forming device. Further, it is grown by thermal oxidation to form a gate oxide layer 42 on the substrate 41. The thickness of the gate oxide layer is between 55 nm and 2 nm, and the gate oxide layer 42 is a layer of germanium dioxide or a layer of high-k dielectric material. 100435.doc -10- •1255553 Then, a gate layer 43 is formed by plasma-assisted chemical vapor deposition (PECVD), low-temperature low-pressure gas phase/integration (LPC VD) or sputtering method. On layer 42. The gate layer 43 may be a polysilicon layer, or may be a single layer=multilayer metal, or may include a polysilicon layer and a metal germanide layer formed on the polycrystalline layer. . An oxidized sacrificial layer 44 is formed on the gate layer U by a vapor deposition method by a low temperature and a low pressure. Then, a polysilicon layer 45 is formed by a plasma-assisted chemical vapor deposition method on the yttrium-oxidized sacrificial layer 44, and a tantalum nitride layer is formed on the polycrystalline germanium layer by a low-temperature low-pressure chemical vapor deposition method. And on the sacrificial oxide layer, the nitride layer is engraved by a reactive ion etch technique to form the edge mask 46. The polycrystalline germanium layer is stripped using an isotropic wet rhyme or reactive ion engraving technique. The oxidized sacrificial layer is then etched by a reactive ion etching technique to form an oxidized sacrificial portion 47. Stripping the tantalum nitride edge reticle 46, and using the oxidation-sacrificial portion 47 as a hard mask (10) rdMask, to form a gate with the active material layer _ electrode layer 43 and the gate oxide layer 42 The pole portion 53 and a pole electrode oxide 52. Then, the carpet is grown into a layer of nitriding stone, and then the edge is used (4) to form the nitrogen layer by the active ion (4) method (4). Then, the remaining oxide sacrificial portion 47 and the gate protection portion are shielded, and the substrate 4 is etched to a set depth by a reactive ion etching method to form a body via 511 as shown in FIG. 4B. Referring to Fig. 4C, a carpet-type inner barrier layer 48 is grown, and a first polysilicon layer 49 is grown on the inner barrier layer 48. Referring to FIG. 41), the first-polycrystalline layer 49 is engraved by the method of the surname of the ion, so that the internal barrier layer 100435.doc -11-.1255553 4 8 is exposed to the degree of i. The method etches the inner barrier layer 48 to the side of the body channel 511 to form an internal barrier portion %, and the chrome portion of the side of the body channel 511 is a shallow channel opening 512. Referring to FIG. 4E, a second polysilicon layer is grown by plasma-assisted chemical vapor deposition (PECVD), low-temperature low-pressure chemical vapor deposition (LPCVD) or sputtering, and then etched by reactive ion etching. The second polysilicon layer is formed to form a source portion 57 and a drain portion 58 on the side of the shallow channel opening 512 _, and the source portion 57 can be formed by a selective crystal growth technique. The drain portion 58 is on the side of the shallow channel opening 512. Thereafter, the source portion 57 and the drain portion 58 may be etched by a reactive ion etching step such that the highest height of the source portion 57 and the drain portion 58 is greater than or equal to the south of the body channel 511. . Thereafter, a thin layer of ruthenium dioxide scattering layer is first grown, and then an ion cloth value technique is used to match a heat repair step to form a source junction and a drain junction, respectively - the source portion 57 and the source Between the shallow channel openings 512 and between the drain portion 58 # and the shallow channel port 512. In the step of forming the source portion 57 and the drain portion 58, the gate portion 53 is a mask, and the erbium dioxide scattering layer for the ion cloth value is used to self-align the source. The portion 57 and the gate portion 58 are then subjected to a metal deuteration technique by first stripping the hard mask of the oxidized sacrificial portion 47 on the gate portion 53 by a reactive ion etching technique or a wet etching technique. The cerium oxide scattering layer for ion implantation exposes both the gate polycrystal and the thickened source/dip. The carpet-type nickel metal is then used to form other metals that form metal halides. Then, driving at a suitable temperature of 100435.doc -12-1255553 is performed to form a source contact layer 571 and a drain contact layer 58 on the source portion 57 and the drain portion 58, respectively. The 571 and the gate contact layer 58 1 are made of a metallization layer, and a metal side portion 54 (Polyside) is formed on the gate portion 53 without a photomask. Re-carpet-grown TEOS' or other phosphorous-boron-containing bismuth oxide glass (BPSG), or other low-k materials as a protective layer, and then using conventional contact window and metal wiring process technology to complete the production The present invention covers a portion of the insulating field effect transistor 50. The metal oxide semiconductor device 50 of the present invention can be applied to a low-cost conventional Shihwa wafer substrate to substantially reduce the cost of fabricating high performance circuits and single wafer systems. According to the manufacturing method of the above embodiment, it is understood that the present invention forms the tantalum nitride edge reticle 46 using only a single-mask, and the others are self-aligned to complete the entire process. Therefore, the metal oxide semiconductor device 5 of the present invention can save cost and solve the problem of leakage current, too large parasitic junction capacitance, floating body effect problem, self-heating effect problem, too large parasitic series resistance problem, ultra short channel Problems such as effect problems and single-check effects. However, the foregoing is merely illustrative of the principles and effects of the invention and is not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a conventional metal oxide semiconductor device; FIG. 2 is a schematic diagram of a conventional metal oxide semiconductor device having a buried oxide layer 100435.doc -1255553 FIG. 3 is a partial insulation of the present invention Schematic diagram of the field effect transistor; FIG. 4A to FIG. 4E are schematic diagrams showing the manufacturing method of the partial insulation field effect transistor of the present invention. [Description of main component symbols] 10 Conventional metal oxide semiconductor device 11 Substrate 12 13 14 15 16 17 20 21 22 23 24 25 26 30 31 32 33 34
本體 源極 汲極 閘極氧化層 閘極 通道 習知之矽覆絕緣（SOI)金屬氧化半導體裝置 基板 本體 源極 及極 閘極氧化層 閘極 本發明矽覆部分絕緣場效電晶體 基板 閘極氧化部 閘極部 金屬化合物部 100435.doc -14- .1255553 35 閘極保護部 36 内部阻絕部 37 源極部 38 汲極部 41 基板 42 閘極氧化層 43 閘極層 44 氧化犧牲層 45 多晶矽層 46 氮化ί夕邊概光罩 47 氧化犧牲部 48 内部阻絕層 49 第一多晶矽層 50 本發明碎覆部分絕緣場效電晶體 51 基板 52 閘極氧化部 53 閘極部 54 金屬矽化物部 55 閘極保護部 56 内部阻絕部 57 源極部 58 汲極部 211 基底 212 埋入氧化層 100435.doc -15 - •1255553 311 本體通道 312 淺層通道口 371 源極接觸層 381 汲極接觸層 511 本體通道 512 淺層通道口 571 源極接觸層 581 汲極接觸層 100435.doc -16Bulk source gate drain oxide gate gate known as SOI metal oxide semiconductor device substrate body source and gate gate oxide gate electrode gate oxide partial oxidation field effect transistor substrate gate oxidation Gate gate metal compound part 100435.doc -14- .1255553 35 Gate protection part 36 Internal blocking part 37 Source part 38 Deuterium part 41 Substrate 42 Gate oxide layer 43 Gate layer 44 Oxide sacrificial layer 45 Polycrystalline layer 46 nitriding illuminating mask 47 oxidizing sacrificial portion 48 internal barrier layer 49 first polysilicon layer 50 shattering partially insulating field effect transistor 51 substrate 52 gate oxide portion 53 gate portion 54 metal telluride Portion 55 gate protection portion 56 internal barrier portion 57 source portion 58 drain portion 211 substrate 212 buried oxide layer 100435.doc -15 - •1255553 311 body channel 312 shallow channel port 371 source contact layer 381 gate contact Layer 511 body channel 512 shallow channel port 571 source contact layer 581 gate contact layer 100435.doc -16