TW471048B - Method of preventing extrusion of a gate - Google Patents

Abstract

A method of preventing extrusion of a gate is provided. A dielectric layer, a conductive layer, a silicide layer, a capping layer and a photoresist layer are formed, respectively, on the surface of a semiconductor wafer. Thereafter, a photo and etching process (PEP) is performed to form a plurality of gates on the surface of the semiconductor wafer. After the photoresist layer is removed, a cleaning process is performed on the surface of the semiconductor wafer to slightly etch the exposed sidewall of the silicide layer of each gate. Finally, a rapid thermal nitridation process (RTN) is performed to nitridize the exposed surface of the silicide layer of each gate so as to prevent the occurrence of extrusion.

Description

471048 V. Description of the invention (1) Field of the invention The present invention provides a method for fabricating a gate electrode, especially a method for avoiding the phenomenon of e x trusi ο η of the gate metal silicide (S i 1icide) layer. Methods. Background Description Metal-oxide semiconductor (MOS) transistors are very important components in semiconductor integrated circuits, and the electrical performance of their gates is an important key to the quality of MOS transistors. The conventional gate usually includes a doped polycrystalline silicon layer (PoSi icon) or an amorphous silicon layer as a main conductive layer, and is then formed on the polycrystalline silicon layer. A metal silicide layer, so that the subsequently formed metal layer and the polycrystalline silicon interface can form a good ohmic contact, thereby reducing the sheet resistance of the gate and increasing the operating speed of the MOS transistor. Please refer to FIGS. 1 to 4, which are schematic diagrams of a conventional method for fabricating a gate electrode 20 on a semiconductor wafer 10. As shown in FIG. 1, the conventional method firstly forms a gate oxide layer (not shown), a doped polycrystalline silicon layer 1 2, a metal silicide layer 14, and a top protective layer in order on the surface of the semiconductor wafer 10. 1 6. Then, a photoresist layer 18 is formed on the surface of the top protective layer 16, and a yellow photolithography process is performed to define the photoresist layer 18.

471048 V. Description of the invention (2) The pattern of a plurality of gates is shown in Figure 2. Next, the pattern of the photoresist layer 18 is used as a hard mask to perform an anisotropic (anisotropic) In the dry etching process, the top protective layer 16, the metal silicide layer 14, and the polycrystalline silicon layer 12 are removed to the surface of the gate oxide layer to form a plurality of gate electrodes 20. After removing the photoresist layer 18, the gate electrode 20 and the surface of the semiconductor wafer 10 are uniformly covered with a liner oxide layer 22. However, in the process of forming the lining oxide layer 22, the lining oxide layer 22 will react with the silicidation ball constituting the metal oxide layer 14, and a metal silicon oxide compound is formed on the surface of the metal silicide layer 14 The conductive layer 24 is formed to cause a convex phenomenon of the gate electrode 20 profile.

Then, as shown in FIG. 3, a sidewall 26 made of silicon nitride (Si × γ) is formed on both sides of the gate electrode 20. Since the vertical side wall of the gate 20 has an uneven profile, the side wall 26 will generate a undulating surface along the contour of the gate 20. Subsequently, a chemical vapor deposition (CVD) process is performed to form a dielectric layer 28 on the surface of the semiconductor wafer 10, and the deposition thickness of the dielectric layer 28 should be greater than the height of the gate electrode 20 to make the dielectric Layer 28 completely covers the surface of gate 20. Then, a yellow light process is used to define a p 1 ug hole pattern, and an etch back process is performed to remove a part of the dielectric layer 28 to form between the two gates 20 A plug hole 30 that penetrates the dielectric layer 28 and reaches the surface of the semiconductor wafer 10.

Page 6 471048 5. Description of the invention (3) As shown in Figure 4, finally a doped polycrystalline silicon layer (not shown) is fully deposited on the surface of the semiconductor wafer 10 to completely fill the plug hole 30, and then removed A doped polycrystalline silicon layer deposited on the outside of the plug hole 30 forms a conductive plug 32. Since the metal silicide layer 14 and the conductive plug 32 rely on the sidewall 26 only as a barrier, the conductive layer 24 protruding outwards causes the metal silicide layer 14 to be convex, which forces the sidewall. The element 2 6 generates an uneven profile, so that the side wall 2 6 formed on the outer side of the junction between the top protective layer 16 and the metal silicide layer 14 is liable to cause a serious insufficient thickness, which makes it impossible to effectively isolate the two conductive layers. Cause a short circuit. In addition, because the profile of the side wall 26 is uneven, it will reduce the filling capacity of the conductive material of the conductive plug 32, which will cause a phenomenon of voids in the conductive plug 32, which will affect its electrical appearance. . SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for avoiding a short circuit caused by a bump phenomenon of a metal silicide layer of a gate electrode. In the preferred embodiment of the present invention, a semiconductor wafer is first provided, and a dielectric layer, a conductive layer, a metal oxide layer, a top protective layer, and a photoresist layer are sequentially formed on the semiconductor wafer. Next, a yellow light process is performed to define a plurality of gate patterns in the photoresist layer. Photoresist

471048 5. Description of the invention (4) The pattern of the layer (4) is used as a hard mask to etch the top protective layer, the metal silicide layer, and the conductive layer to form each gate on the surface of the semiconductor wafer. After the photoresist layer is removed, a cleaning process is performed on the surface of the semiconductor wafer, and a part of the metal silicide layer exposed on each gate sidewall is etched. Finally, a rapid high temperature nitridation process (RTN) is performed to nitride the surface of the metal silicide layer exposed by each gate to avoid the phenomenon of bumping of each gate, and complete the gate fabrication of the present invention. k Since the present invention uses a rapid high-temperature nitridation process to surface-treat the exposed metal \ silicide layer sidewalls to form a protective layer, it can effectively prevent the metal stone oxide layer from bulging, which in turn causes the gate electrode to produce a Roughly flat outline to improve its electrical performance. Detailed description of the invention Please refer to FIG. 5 to FIG. 9. FIG. 5 to FIG. 9 are schematic diagrams of a method for manufacturing a gate 56 according to the present invention. As shown in FIG. 5, a semiconductor wafer 40 is first provided, and a silicon dioxide (silicon di i ο X i d e, S i 0 2) layer is formed on the surface of the semiconductor wafer 40 as a gate oxide layer (not shown). Then, a chemical vapor deposition method is used to sequentially form a doped polycrystalline stone layer 42, a metal layer 44, a metal stone layer 46, a metal layer 48, and an antibody on the surface of the semiconductor wafer 40 in order. A reflective layer 50 and a top protective layer 52. Among them, the titanium metal layers 4 4 and 4 8 are used to reduce the sheet resistance values between the polycrystalline silicon layer 42 and the metal silicide layer 46 and the surface of the metal oxide layer 46, respectively.

Page 8 471048 V. Description of the invention (5) '----- f 46 is composed of tungsten tungsten oxide (WSix), and the anti-reflection layer 50 is composed of silicon oxynitride ^ silicon-0Xynitride (SiON) Structure, the top protective layer 52 is composed of a compound. Next, a photoresist 2 &4; is formed on the surface of the top protective layer 5 2 and a yellow light process is performed to define a plurality of gates in the photoresist layer 5 4 as shown in FIG. 6. Isotropic dry etching of the reflective layer 50, titanium metal layer 48, metal and polycrystalline silicon layer 4 2 to the gate oxide layer 5 6 ° The pattern of the photoresist layer 54 is used as a hard cover process, and the top protective layer 5 is removed 2. Anti-Shi Xi The compound layer 46 and the titanium metal layer 4 4 are formed on the surface to form a plurality of gate electrodes. After the layer 5 4 is shown in FIG. 7, the semiconductor wafer 4 is formed. Surface ί ί ί ί / f, use RCA standard cleaning solution-1 (sc_ ”to clean ^ = Zuri film _ 40 surface, and at the same time select the vertical wall exposed by the metal silicide layer 46 Ground etching to generate a groove 5 8 structure on both sides of the gate 5 6. Then, as shown in FIG. 8, a rapid high temperature nitridation process (RTN) is performed: pass-through_ nitrogen-containing gas The nitrogen-containing gas is thermally decomposed to generate nitrogen atoms' to expose the surface of the metal silicide layer 4 6 in the groove 5 8 structure to produce a tungsten nitride dielectric layer 6 0 and the gate jp 5 6 It has an approximately flat sidewall structure, wherein the nitrogen-containing gas may be nitrous oxide (N20), nitric oxide,

471048 V. Description of the invention (6) D or ammonia (ammonia, Hi 3), etc. (NO), nitrogen (ni trogen), as shown in Figure 9, and then a low pressure chemical vapor deposition (LPCVD) process is performed. Ethoxylate (tetra-ethyl-ortho-si 1 icate, Si (0C2H5) 4, TE0S) is used as a reaction gas to form a lining oxide layer 62 on the gate 56 and the surface of the semiconductor wafer 40. Subsequently, A nitrogen-silicon compound layer (not shown) is deposited over the liner oxide layer 62 and a part of the nitrogen-stone compound layer is removed by etching to form a sidewall 6 4 ′ on both sides of the gate electrode 5 6 to complete the present invention. The gate electrode 5 6 is produced. Because the present invention first uses a cleaning process to remove part of the metal silicide layer 46 to form a groove 5 8 around the vertical sidewall of the gate electrode 5 6, and then a rapid high temperature is used. The nitriding process is used to perform a surface treatment on the metal silicide layer 46 exposed in the grooves 58, so that the gate electrode 58 can have a slightly flat profile. In addition, the rapid high-temperature nitriding process used in the present invention (RTN) A dielectric layer 60 is formed on the surface of the metal oxide layer 4 6 as A protective layer to isolate the metal silicide layer 46 and the lining oxide layer 62, so not only can effectively prevent the metal tungsten silicide from oxidizing to form a conductive layer, thereby suppressing the convexity of the gate 5 6 structure, but also avoiding metal A short circuit occurs between the silicide layer 46 and the conductive plug that is subsequently filled between the two gates 56. Compared to the conventional method of making the gate, the present invention uses a multi-layer structure, such as metal A titanium gold layer is added above and below each layer to reduce the sheet resistance of the gate and improve its electrical performance. In addition, the invention

Page 10 471048 5. Description of the invention (7) A fast high temperature nitridation process is used to surface-treat the metal tungsten silicide layer of the gate electrode to effectively prevent the metal tungsten silicide from reacting with the liner oxide layer. Therefore, the method of the present invention can not only prevent the phenomenon of the convexity of the gate electrode and maintain the integrity of the gate structure, but also can use a dielectric layer generated on the surface of the metallized chemical crane layer after nitriding to increase the conductive plug Isolation from the metal tungsten oxide layer to effectively avoid short circuit problems. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

Page 11 471048 Brief description of the diagrams Brief description of the diagrams Figures 1 to 4 are schematic diagrams of the conventional method for making a gate. 5 to 9 are schematic diagrams of a method for fabricating a gate electrode according to the present invention. Symbol description

Page 12 10 Semiconductor wafers 12 Polycrystalline silicon layer 14 Metal oxide layer 16 Top protective layer 18 Photoresist layer 20 Gate 22 Almost oxide layer 24 Conductive layer 26 Side wall 28 Dielectric layer 30 Plug hole 32 Conductive plug 40 Semiconductor wafer 42 Polycrystalline silicon layer 44, 48 Titanium metal layer 46 Metal oxide layer 50 Anti-reflection layer 52 Top protective layer 54 Photoresist layer 56 Gate 58 Recess 60 Dielectric layer 62 Lining oxide layer 64 Side wall

Claims (1)

471048 6. Scope of patent application 1. A method for avoiding the phenomenon of gate extrusion on a semiconductor wafer, the method includes the following steps: sequentially forming a dielectric layer and a conductive layer on the surface of the semiconductor wafer A silicide layer, a protective layer and a photoresist layer; perform a lithography process, and define a plurality of gate patterns (P a 11 er η) in the photoresist layer ); Using the pattern of the photoresist layer as a hard mask to etch the top protective layer, the metal oxide layer and the conductive layer to form the gates on the surface of the semiconductor wafer; The photoresist layer; performing a cleaning process on the surface of the semiconductor wafer, and etching the metal silicide layer exposed on each side wall of the gate; and performing a rapid high temperature nitridation process (RTN) to nitride each The surface of the metal sanding layer exposed by the gate. 2. The method of claim 1 in which the dielectric layer is composed of silicon dioxide (Si 02). 3. The method according to item 1 of the patent application, wherein the conductive layer is composed of a doped polycrystalline stone (d 0 p e d ρ ο 1 y s i 1 i c ο η) layer. 4. The method of claim 3, wherein the top surface of the conductive layer further includes a titanium (Ti) layer to reduce the sheet resistance between the conductive layer and the metal oxide layer. ). Page 13 471048 6. Scope of patent application 5. The method according to item 1 of the scope of patent application, wherein the metal silicide layer is composed of a metal tungsten silicide (WSi x) layer. 6. The method of claim 1, wherein the top surface of the metal silicide layer further comprises a titanium (T) layer, which is used to reduce the sheet resistance on the surface of the metal silicide layer. 7. The method according to item 1 of the patent application, wherein the bottom of the top protective layer further comprises an anti-reflection coating (ARC). 8. The method according to item 1 of the patent application scope, wherein the cleaning solution of the cleaning process comprises RCA standard cleaning solution-1 (SC-1). 9. The method according to item 1 of the scope of patent application, wherein the rapid high-temperature nitriding process is performed on a nitrogen (N 2), nitrous oxide (N20), nitric oxide (NO) or Ammonia (NH3) environment. 10. The method according to item 1 of the scope of patent application, wherein the rapid high-temperature nitridation process forms a protective layer on the surface of the metal silicide layer exposed by each gate to suppress the metal silicide of each gate. The layer has a convex phenomenon. Page 14 471048 6. The scope of the patent application is a plurality of gates and polycrystalline silicon guides: 11. One-line square-to-layer and one-to-one pattern; Use the metal to form the opposite poles and layers: to enter each of the A method for forming a semiconductor wafer, the method includes the following steps: forming a dielectric layer, a polycrystalline silicon metal oxide layer, a protective layer, and a photoresist layer in sequence on the surface of the semiconductor wafer; performing a yellow light process; A pattern of a plurality of gate resist layers is defined in the photoresist layer as the layer and the polycrystalline silicon and each of the polycrystalline silicon resist layers; the photolithium oxide used on the side of the crystalline silicon wire on the surface of the bulk wafer is used to eliminate the light The semiconductors each etch the top protective layer and layer on the hard mask exposed by the polycrystalline silicon wire in a rapid high temperature nitridation process to etch the top surface of the semiconductor wafer; a cleaning process and etch each of the gates to expose A part of the metal silicide (RTN) is used to nitride the surface of the metal oxide layer of each gate. 1 2. The method according to item 11 of the scope of patent application, wherein the dielectric layer is composed of SiO 2 (S i 0 2). 13. The method according to item 11 of the scope of patent application, wherein the polycrystalline silicon layer is a doped polycrystalline silicon layer, and the top surface of the doped polycrystalline silicon layer further includes a titanium (T i) layer to reduce the doping. Sheet resistance between the polycrystalline silicon layer and the metal silicide layer. Page 15 471048 6. Scope of patent application 1 4. The method according to item 11 of the scope of patent application, wherein the metal silicide layer is composed of a metal tungsten silicide (WS ix) layer, and the top surface of the metal silicide layer A titanium (T i) layer is further included to reduce the sheet resistance of the surface of the metal oxide layer. 15. The method according to item 11 of the patent application, wherein the bottom of the top protective layer further comprises an anti-reflection layer (ARC). 16. The method according to item 11 of the scope of patent application, wherein the cleaning solution in the cleaning process includes R C A standard cleaning solution-1 (S C-1). 17. The method according to item 11 of the scope of patent application, wherein the rapid high-temperature nitriding process is performed on a nitrogen (N 2), nitrous oxide (N 20), nitric oxide (NO), or ammonia gas ( NH3). Page 16