TWI694571B - Word line structure and method of manufacturing the same - Google Patents

Abstract

Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.

Description

Character line structure and manufacturing method thereof

The invention relates to a memory element and a manufacturing method thereof, and particularly relates to a word line structure and a manufacturing method thereof.

The metal silicide layer has the advantages of high melting point, stability and low resistance value, and has been widely used in integrated circuits. In the gradually miniaturized integrated circuit technology, the line width, contact area and junction depth are gradually reduced. In order to effectively improve the working quality of the device, reduce the resistance and reduce the signal transmission delay caused by the resistance and capacitance, so it is often The metal silicide layer is used to effectively reduce the junction resistance.

However, with the advancement of memory technology, the critical size of memory (such as word line spacing) has also shrunk. Due to the narrowing of the word line spacing, the word line necking is likely to occur in the silidation process, which may cause the word line bending problem, which may cause leakage current, which may affect the performance of the memory.

The invention provides a word line structure and a manufacturing method thereof, which can avoid the word line bending problem caused by the necking of the word line, and improve the stability and durability of the impedance of the original word line, thereby improving the memory efficacy.

The invention provides a word line structure, including: a substrate, a stacked structure and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is arranged on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and the concentration of the first metal element and the concentration of the second metal element gradually decrease from the top surface of the metal silicide structure toward the substrate.

In an embodiment of the invention, the first metal element includes titanium, nickel or a combination thereof, and the second metal element includes cobalt.

In an embodiment of the invention, the concentration of the first metal element is less than the concentration of the second metal element, and the concentration of the second metal element is less than the concentration of silicon element.

In an embodiment of the present invention, the metal silicide structure includes a first part and a second part located on the first part, and the average concentration of the first metal element in the second part is about 5 to 7 times.

In an embodiment of the present invention, the ratio of the average concentration of the second metal element in the second part to the average concentration of the second metal element in the first part is 1 to 2.

In an embodiment of the invention, the first metal element has a first concentration gradient, the second metal element has a second concentration gradient, and the first concentration gradient is greater than the second concentration gradient.

In an embodiment of the invention, the above-mentioned stacked structure includes: a charge storage layer, a conductor layer and an inter-gate dielectric layer. The conductor layer is arranged on the charge storage layer. The inter-gate dielectric layer is disposed between the charge storage layer and the conductor layer.

In an embodiment of the invention, the above word line structure further includes a tunneling dielectric layer disposed between the substrate and the stacked structure.

The present invention provides a method for manufacturing the above word line structure in an embodiment of the present invention, and the steps are as follows. A stacked structure is formed on the substrate. A deposition process is performed to form a first metal layer and a second metal layer in order to cover the top of the stacked structure, where the first metal layer and the second metal layer have different metals. A heat treatment process is performed to transform the top of the stacked structure into a metal silicide structure.

In an embodiment of the invention, the above-mentioned first metal layer includes a titanium layer, a nickel layer or a combination thereof, and the second metal layer includes a cobalt layer.

In an embodiment of the invention, the thickness of the first metal layer is smaller than the thickness of the second metal layer.

In an embodiment of the invention, the above heat treatment process includes the following steps. The first heat treatment step is performed so that the first metal layer and the second metal layer react with the top of the stacked structure. A selective removal step is performed to remove the unreacted first metal layer and the unreacted second metal layer. The second heat treatment step is performed, and the temperature of the second heat treatment step is greater than the temperature of the first heat treatment step.

In an embodiment of the invention, the above-mentioned deposition process and the first heat treatment step are performed simultaneously.

In an embodiment of the invention, the above-mentioned first heat treatment step is performed after the deposition process.

In an embodiment of the invention, the above manufacturing method further includes forming a cap layer on the second metal layer, wherein the cap layer includes a metal nitride layer.

In an embodiment of the invention, the metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element. The concentration of the first metal element and the concentration of the second metal element gradually decrease from the top surface of the metal silicide structure toward the substrate.

In an embodiment of the invention, the concentration of the first metal element is less than the concentration of the second metal element, and the concentration of the second metal element is less than the concentration of silicon element.

In an embodiment of the present invention, the above metal silicide structure includes a first part and a second part located on the first part, and the average concentration of the first metal element in the second part is about 5 to 7 in the first part Times.

In an embodiment of the present invention, the ratio of the average concentration of the second metal element in the second part to the average concentration of the second metal element in the first part is 1 to 2.

In an embodiment of the invention, the first metal element has a first concentration gradient, the second metal element has a second concentration gradient, and the first concentration gradient is greater than the second concentration gradient.

Based on the above, in this embodiment, the first metal layer and the second metal layer are sequentially formed to cover the top of the stack structure, and a heat treatment process is performed to transform the top of the stack structure into a metal silicide structure. Since the first metal layer and the second metal layer have different materials, they can maintain the shape of the metal silicide structure and are not prone to necking or bending. In this case, this embodiment can reduce the word line impedance, thereby improving the performance of the memory.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

The invention is explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms, and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numerals indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

1A to 1E are schematic cross-sectional views of a manufacturing process of a word line structure according to an embodiment of the invention. The word line structure described in the following embodiments can be applied to memory elements (such as flash memory), but the invention is not limited thereto.

Referring to FIG. 1A, an embodiment of the present invention provides a method for manufacturing a word line structure 10 (as shown in FIG. 1D). The steps are as follows. First, the substrate 100 is provided. In some embodiments, the substrate 100 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator, SOI) on an insulating layer. The semiconductor is, for example, an atom of group IVA, such as silicon or germanium. The semiconductor compound is, for example, a semiconductor compound formed by group IVA atoms, for example, silicon carbide or germanium silicide, or a semiconductor compound formed by group IIIA atoms and group VA atoms, for example, gallium arsenide.

Next, a tunneling dielectric layer 102 is formed on the substrate 100. As shown in FIG. 1A, the tunneling dielectric layer 102 fully covers the surface of the substrate 100. In some embodiments, the tunneling dielectric layer 102 may be composed of a single material layer. The single material layer is, for example, a low dielectric constant material or a high dielectric constant material. The low dielectric constant material is a dielectric material having a dielectric constant lower than 4, such as silicon oxide or silicon oxynitride. The high dielectric constant material is a dielectric material having a dielectric constant higher than 4, for example, HfAlO, HfO ₂ , Al ₂ O ₃ or Si ₃ N ₄ . In an alternative embodiment, the tunneling dielectric layer 102 can also be a double-layer structure or a multi-layer structure.

Then, a plurality of stacked structures 104 are formed on the tunneling dielectric layer 102 so that the tunneling dielectric layer 102 is located between the substrate 100 and the stacking structure 104. Specifically, the stacked structure 104 includes a charge storage layer 106, an intergate dielectric layer 108, and a conductor layer 110 in this order from bottom to top. In some embodiments, the material of the charge storage layer 106 includes a conductive material, which may be, for example, doped polysilicon, undoped polysilicon, or a combination thereof. In this embodiment, the charge storage layer 106 may be a floating gate. The material of the inter-gate dielectric layer 108 includes a dielectric material, which may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The inter-gate dielectric layer 108 may be a single-layer structure or a multi-layer structure. In this embodiment, the inter-gate dielectric layer 108 may be, for example, a composite layer composed of oxide/nitride/oxide (Oxide/Nitride/Oxide, ONO). The material of the conductor layer 110 includes a conductor material, which may be, for example, doped polysilicon, undoped polysilicon, or a combination thereof. In this embodiment, the conductor layer 110 may be a control gate.

In some embodiments, the stacked structures 104 are spaced apart from each other in an equidistant manner, as shown in FIG. 1A. However, the present invention is not limited to this. In other embodiments, the stacked structures 104 may also be spaced from each other in a non-equidistant manner. In alternative embodiments, the width or bottom area of the stacked structure 104 may be the same as or different from each other.

After forming the stacked structure 104, a liner layer 112 is formed to conformally cover the stacked structure 104. In some embodiments, the material of the liner layer 112 includes a dielectric material, which may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Next, a dielectric layer 113 is formed to fill the trenches or spaces between the stacked structures 104. In some embodiments, the material of the dielectric layer 113 includes a dielectric material, which may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In alternative embodiments, the liner layer 112 and the dielectric layer 113 include different materials. For example, the liner layer 112 may be a silicon oxide layer, and the dielectric layer 113 may be a silicon nitride layer. On the other hand, after the dielectric layer 113 is formed, a planarization process may be selectively performed so that the top surface of the dielectric layer 113 and the top surface of the liner layer 112 are coplanar, as shown in FIG. 1A.

Referring to FIGS. 1A and 1B, part of the dielectric layer 113 and part of the liner layer 112 are sequentially removed, so that the top 111 of the stacked structure 104 is exposed to the dielectric layer 113a and the liner layer 112a. The ratio of the top 111 and the bottom 109 of the stacked structure 104 can be adjusted according to requirements, and the invention is not limited thereto. In some embodiments, the top surface of the liner layer 112a is at least higher than the top surface of the intergate dielectric layer 108.

1B and 1C, after the top 111 of the stack structure 104 is exposed, the dielectric layer 113a is completely removed. Next, a deposition process is performed to sequentially form the first metal layer 114, the second metal layer 116, and the cap layer 118. In this case, the first metal layer 114, the second metal layer 116 and the cap layer 118 conformally cover at least the top surface and the side wall of the top 111 of the stacked structure 104. In an alternative embodiment, as shown in FIG. 1C, the first metal layer 114, the second metal layer 116, and the cap layer 118 extend to cover the surface of the liner layer 112a. In some embodiments, the first metal layer 114 includes a titanium layer, a nickel layer, or a combination thereof, and the thickness thereof may be between 0.5 nm and 3 nm. The second metal layer 116 includes a cobalt layer, and its thickness may be between 5 nm and 8 nm. In this embodiment, the first metal layer 114 and the second metal layer 116 have different metals, and the thickness of the first metal layer 114 is smaller than the thickness of the second metal layer 116. The cap layer 118 includes a metal nitride layer, for example, titanium nitride (TiN), and its thickness may be between 5 nm and 10 nm.

1C and 1D, a heat treatment process (or silicidation process) is performed to transform the top 111 of the stack structure 104 into a metal silicide structure 121. Hereinafter, the bottom 109 of the stacked structure 104 is referred to as a stacked structure 104, and the metal silicide structure 121 is located on the stacked structure 104. Specifically, the above heat treatment process includes the following steps. The first heat treatment step is performed so that the first metal layer 114 and the second metal layer 116 react with the top 111 of the stack structure 104 to form the first metal silicide. In this case, the above-mentioned first metal silicide may be, for example, a metastable phase structure. In some embodiments, the first heat treatment step may be a Rapid Thermal Process (RTP), the temperature of which may range from 450°C to 500°C, and the processing time may range from 30 seconds to Between 180 seconds.

After forming the first metal silicide, a selective removal step is performed to remove the unreacted first metal layer 114, the unreacted second metal layer 116, and the cap layer 118. In some embodiments, the aforementioned selective removal step is, for example, an RCA cleaning process. The RCA cleaning process includes the use of a mixed solution of water (H ₂ O)/hydrogen peroxide (H ₂ O ₂ )/ammonia (NH ₄ OH) (that is, standard cleaning solution SC1), and the use of water (H ₂ O)/excess A mixed solution of hydrogen oxide (H ₂ O ₂ )/hydrochloric acid (HCl) (that is, standard cleaning solution SC2) or a combination of the above SC1 and SC2 is used.

After removing the unreacted first metal layer 114, the unreacted second metal layer 116, and the cap layer 118, a second heat treatment step is performed to convert the first metal silicide to a second metal with a lower resistance value The silicide, that is, the metal silicide structure 121 shown in FIG. 1D. In this case, the above-mentioned second metal silicide may be, for example, a stable phase structure. In other words, the phase structure of the second metal silicide is more stable than that of the first metal silicide. In some embodiments, the second heat treatment step may be another rapid heat treatment process, the temperature may be between 700°C and 900°C, and the treatment time may be between 10 seconds and 90 seconds. In an alternative embodiment, the temperature of the second heat treatment step is greater than the temperature of the first heat treatment step.

In addition, although the first heat treatment step is performed after the deposition process, the present invention is not limited thereto. In other embodiments, the deposition process and the first heat treatment step may also be performed simultaneously. That is, deposition and heating can be performed simultaneously in the same chamber. In other words, the deposition process and the first heat treatment step can be performed in-situ.

As shown in FIG. 1D, during the silicidation process, the top 111 reacts with the first metal layer 114 and the second metal layer 116 to consume part of the top 111. Therefore, the volume of the metal silicide structure 121 after the reaction may be smaller than the volume of the top 111 before the reaction. The shrinkage phenomenon of the metal silicide described above makes the side walls of the metal silicide structure 121 shrink more than the side walls of the stacked structure 104.

It is worth noting that in this embodiment, the first metal layer 114 and the second metal layer 116 made of different metal materials are subjected to a silicidation process with the top 111, which can solve the problem of necking or deformation of the metal silicide structure 121. In order to reduce the impedance of the word line, and thus improve the performance of the memory. In the following, the first metal layer 114 is a titanium layer and the second metal layer 116 is a cobalt layer as an example. In some embodiments, the movement rate of the titanium element in the titanium layer 114 is smaller than the movement rate of the cobalt element in the cobalt layer 116. In this case, most of the cobalt element diffuses into the top 111, while most of the titanium element stays on the surface of the top 111. Therefore, these titanium elements can maintain the shape of the metal silicide structure 121, and are not easy to neck and bend. Compared with the single cobalt layer for the silicidation process, in this embodiment, the titanium layer is inserted between the cobalt layer and the silicon layer for the silicidation process. The outline of the metal silicide structure 121 formed by it is straighter and less curved, and It can also improve the stability and durability of the word line impedance. In another embodiment, in the silicidation process, cobalt atoms consume more silicon atoms than titanium or nickel atoms. Therefore, compared with the single cobalt layer for the silicidation process, in this embodiment, the titanium layer or the nickel layer is inserted between the cobalt layer and the silicon layer to perform the silicidation process, and the formed metal silicide structure 121 is less likely to shrink. Therefore, , The shape of the metal silicide structure 121 can be maintained without being easily deformed.

1D and FIG. 2, the metal silicide structure 121 is disposed on the stack structure 104. The metal silicide structure 121 includes a first metal element 131, a second metal element 132, and a silicon element 133. In one embodiment, the first metal element 131 includes titanium, nickel, or a combination thereof, and the second metal element 132 includes cobalt. In another embodiment, the first metal element 131 and the second metal element 132 are different. As shown in FIG. 2, along the direction of the top surface 121t of the metal silicide structure 121 toward the substrate 100 (that is, line AA′), the concentration of the first metal element 131 and the concentration of the second metal element 132 gradually cut back. The concentration of the first metal element 131 is less than the concentration of the second metal element 132, and the concentration of the second metal element 132 is less than the concentration of the silicon element 133.

In other embodiments, the first metal element 131 has a first concentration gradient, and the second metal element 132 has a second concentration gradient. Here, the "concentration gradient" refers to the concentration difference, the slope of the concentration curve, or the ratio of the maximum concentration to the minimum concentration. As shown in FIG. 2, the first concentration gradient of the first metal element 131 is greater than the second concentration gradient of the second metal element 132. In other words, most of the first metal elements 131 (such as Ti) are located or concentrated on the top surface 121t of the metal silicide structure 121; and most of the second metal elements 132 (such as Co) are diffused or uniformly dispersed to In the metal silicide structure 121.

Specifically, the metal silicide structure 121 includes a first portion 121a and a second portion 121b located on the first portion 121a, as shown in FIG. 1D. In some embodiments, the middle width W1 of the first portion 121a may be less than or equal to the middle width W2 of the second portion 121b, but the invention is not limited thereto. As shown in FIG. 2, looking along the direction of the top surface 121t of the metal silicide structure 121 toward the substrate 100 (that is, line AA′), in one embodiment, the first metal element in the second portion 121b The ratio (R1) of the average concentration of 131 to the average concentration of the first metal element 131 in the first portion 121a is 5 to 7. That is to say, the average concentration of the first metal element 131 in the second portion 121b is about 5 to 7 times that of the first portion 121a. In another embodiment, the ratio (R2) of the average concentration of the second metal element 132 in the second portion 121b to the average concentration of the second metal element 132 in the first portion 121a is 1 to 2. In an alternative embodiment, the aforementioned ratio (R1) is greater than the ratio (R2). In other words, the first metal element 131 is more concentrated in the second portion 121b; and the second metal element 132 is evenly distributed in the first portion 121a and the second portion 121b.

1D and 1E, after the metal silicide structure 121 is formed, the word line structure 10 is completed. After forming the word line structure 10, a dielectric layer 120 may be formed to cover the metal silicide structure 121. In some embodiments, the material of the dielectric layer 120 includes silicon oxide, phosphorosilicate glass (PSG), borophosphosilicate glass (BPSG), or a combination thereof. Since the spacing between the metal silicide structures 121 is relatively small, an air gap 122 is formed when the dielectric layer 120 fills the space between the metal silicide structures 121. As shown in FIG. 1E, the air gap 122 is located between the stacked structures 104 and extends from the lower portion of the stacked structure 104 to the upper portion of the metal silicide structure 121. In some embodiments, since the dielectric constant of the air gap 122 approaches 1, the air gap 122 can reduce the capacitance between the metal silicide structures 121 and reduce the RC delay. As shown in FIG. 1E, the top surface 122t of the air gap 122 may be equal to or higher than the top surface 121t of the metal silicide structure 121. In another embodiment, the air gap 122 may or may not contact the top surface of the tunneling dielectric layer 102. In alternative embodiments, the air gap 122 includes a single air gap or more than two air gaps.

In summary, in this embodiment, the first metal layer and the second metal layer are formed in order to cover the top of the stack structure, and a heat treatment process is performed to transform the top of the stack structure into a metal silicide structure. Since the first metal layer and the second metal layer have different materials, they can maintain the shape of the metal silicide structure and are not prone to necking or bending. In this case, this embodiment can reduce the word line impedance, thereby improving the performance of the memory.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10: Character line structure 100: base 102: Tunneling dielectric layer 104: stacked structure 106: charge storage layer 108: Gate dielectric layer 109: bottom of the stack structure 110: conductor layer 111: the top of the stack structure 112: Lining 113, 120: dielectric layer 114: first metal layer 116: Second metal layer 118: top cover layer 121: Metal silicide structure 121a: Part One 121b: Part Two 121t: top surface of metal silicide structure 122: Air gap 122t: the top surface of the air gap 131: The first metal element 132: Second metal element 133: Silicon W1, W2: middle width

1A to 1E are schematic cross-sectional views of a manufacturing process of a word line structure according to an embodiment of the invention. Fig. 2 is a graph of the relationship between the numerical intensity (density) and the distance along the line A-A' of Fig. 1D.

10: Character line structure

100: base

102: Tunneling dielectric layer

104: stacked structure

106: charge storage layer

108: Gate dielectric layer

110: conductor layer

112a: Lining

120: dielectric layer

121: Metal silicide structure

121t: top surface of metal silicide structure

122: Air gap

122t: the top surface of the air gap

Claims (20)

A character line structure, including: Stacked structure, arranged on the substrate; and A metal silicide structure disposed on the stack structure, wherein the metal silicide structure includes a first metal element, a second metal element, and a silicon element, the first metal element is different from the second metal element, and The concentration of the first metal element and the concentration of the second metal element gradually decrease from the top surface of the metal silicide structure toward the substrate. The character line structure as described in item 1 of the patent application scope, wherein the first metal element includes titanium, nickel or a combination thereof, and the second metal element includes cobalt. The character line structure as described in item 2 of the patent application range, wherein the concentration of the first metal element is less than the concentration of the second metal element, and the concentration of the second metal element is less than The concentration of silicon element. The word line structure as described in item 2 of the patent application scope, wherein the metal silicide structure includes a first part and a second part located on the first part, and the first metal in the second part The ratio of the average concentration of the element to the average concentration of the first metal element in the first part is 5 to 7. The character line structure as described in item 4 of the patent application range, wherein the ratio of the average concentration of the second metal element in the second part to the average concentration of the second metal element in the first part For 1 to 2. The character line structure as described in item 2 of the patent application scope, wherein the first metal element has a first concentration gradient, the second metal element has a second concentration gradient, and the first concentration gradient is greater than the Second concentration gradient. The character line structure as described in item 1 of the patent application scope, wherein the stacked structure includes: Charge storage layer; A conductor layer disposed on the charge storage layer; and The inter-gate dielectric layer is disposed between the charge storage layer and the conductor layer. The word line structure as described in item 1 of the patent application further includes a tunneling dielectric layer disposed between the substrate and the stacked structure. A method for manufacturing a character line structure includes: Forming a stacked structure on the substrate; Performing a deposition process to sequentially form a first metal layer and a second metal layer to cover the top of the stacked structure, wherein the first metal layer and the second metal layer have different metals; and A heat treatment process is performed to transform the top of the stacked structure into a metal silicide structure. The method for manufacturing a word line structure as described in item 9 of the patent application range, wherein the first metal layer includes a titanium layer, a nickel layer, or a combination thereof, and the second metal layer includes a cobalt layer. The method for manufacturing a word line structure as described in item 9 of the patent application range, wherein the thickness of the first metal layer is smaller than the thickness of the second metal layer. The method for manufacturing a character line structure as described in item 9 of the patent application scope, wherein the process of performing the heat treatment includes: Performing a first heat treatment step so that the first metal layer and the second metal layer react with the top of the stacked structure; Performing a selective removal step to remove the unreacted first metal layer and the unreacted second metal layer; and A second heat treatment step is performed, wherein the temperature of the second heat treatment step is greater than the temperature of the first heat treatment step. The method for manufacturing a word line structure as described in item 12 of the patent application scope, wherein the deposition process and the first heat treatment step are performed simultaneously. The method for manufacturing a word line structure as described in item 12 of the patent application scope, wherein the first heat treatment step is performed after the deposition process. The method for manufacturing a word line structure as described in item 9 of the scope of the patent application further includes forming a cap layer on the second metal layer, wherein the cap layer includes a metal nitride layer. The method for manufacturing a word line structure as described in item 9 of the patent application scope, wherein the metal silicide structure includes a first metal element, a second metal element, and a silicon element, the first metal element and the second The metal elements are different, and the concentrations of the first metal element and the second metal element gradually decrease from the top surface of the metal silicide structure toward the substrate. The method for manufacturing a word line structure as described in item 16 of the patent application range, wherein the concentration of the first metal element is less than the concentration of the second metal element, and the position of the second metal element The concentration is less than the concentration of silicon element. The method for manufacturing a word line structure as described in item 16 of the patent application range, wherein the metal silicide structure includes a first part and a second part located on the first part, and the The ratio of the average concentration of the first metal element to the average concentration of the first metal element in the first part is 5 to 7. The method for manufacturing a character line structure as described in item 18 of the patent application range, wherein the average concentration of the second metal element in the second part and the average of the second metal element in the first part The ratio of the concentration is 1 to 2. The method for manufacturing a word line structure as described in item 16 of the patent application range, wherein the first metal element has a first concentration gradient, the second metal element has a second concentration gradient, and the first concentration gradient Greater than the second concentration gradient.

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