TWI553784B - Memory device and method for fabricating the same - Google Patents

Description

Memory element and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a memory device and a method of fabricating the same.

Memory can be divided into two types: volatile memory (Volatile memory) and non-volatile memory (Non-volatile memory). Volatile memory will disappear after the power supply is interrupted. The non-volatile memory will not disappear after the power supply is interrupted. After re-powering, it will be able to Read the data in the memory. Therefore, non-volatile memory can be widely used in electronic products, especially portable products.

As the accumulation of memory elements increases and the size shrinks, the leakage current of the memory elements also increases. When boron is doped in the well region of the memory element, boron in the boundary region is easily out-diffused, so that the doping concentration of boron in the boundary region of the well region is smaller than the doping concentration of boron in the intermediate region of the well region. In this way, when the memory element is operated, its threshold voltage (Vt) will vary with different doping concentrations in the well region. When the threshold voltage changes As you increase, the reliability of the memory component decreases.

Since the prior art performed an additional ion implantation process at the boundary region of the well region to compensate for the doping concentration of the boundary region of the well region after outward diffusion. However, this technical solution causes surface damage of the tunneling dielectric layer on the well region and reduces the stress of the tunneling dielectric layer, so that it has a voltage shift (Vt shift). In order to improve the phenomenon of threshold voltage displacement, it is necessary to increase the thickness of the tunneling dielectric layer. However, an increase in the thickness of the tunneling dielectric layer causes an increase in its operating voltage, and this result is not desirable for components with high integration. Therefore, how to reduce the leakage current of the memory element and improve the uniformity of the threshold voltage (Uniformity) becomes an extremely problem to be solved.

The present invention provides a memory element and a method of fabricating the same that can improve the uniformity of the threshold voltage of the memory element.

The present invention provides a memory device including a substrate, a well region, a tunneling dielectric layer, a first conductor layer, an isolation structure, and a barrier layer. The well zone is located in the substrate. The tunneling dielectric layer is located on the well region. The first conductor layer is on the tunneling dielectric layer. The isolation structure is located in the first conductor layer, the tunneling dielectric layer, the well region, and the substrate. The barrier layer is located between the isolation structure and the well region.

In an embodiment of the invention, the memory element further includes a gate dielectric layer on a top surface of the first conductor layer and a top surface of the isolation structure. The second conductor layer is on the inter-gate dielectric layer.

In an embodiment of the invention, the barrier layer further extends the isolation structure Between the first conductor layer and the above.

In an embodiment of the invention, the barrier layer comprises a nitrogen-containing material.

In an embodiment of the invention, the barrier layer comprises tantalum nitride or hafnium oxynitride.

The present invention provides a method of fabricating a memory element comprising providing a substrate. Next, a well region is formed in the substrate. A tunneling dielectric layer is formed on the well region. Forming a first conductor layer on the tunneling dielectric layer. A trench is then formed in the first conductor layer, the tunneling dielectric layer, the well region, and the substrate. Thereafter, a surface treatment process is performed to form a barrier layer on the side and bottom surfaces of the trench.

In an embodiment of the invention, the surface treatment process includes a nitriding treatment, a plasma treatment, or an oxynitridation treatment.

In an embodiment of the invention, the surface treatment process includes a nitridation process, and the nitridation process includes a heat treatment, a plasma treatment, or an oxynitride treatment.

In an embodiment of the invention, the barrier layer comprises a nitrogen-containing material.

In an embodiment of the invention, the barrier layer comprises tantalum nitride or hafnium oxynitride.

Based on the above, the present invention can utilize the above-mentioned barrier layer to prevent or reduce out-diffusion of the doping dopant doped in the well region and the first conductor layer, and reduce the doping concentration boundary region and the intermediate region of the well region and the first conductor layer. The difference in doping concentration. In this way, the boundary region between the well region and the first conductor layer is less likely to cause leakage current, thereby improving the uniformity of the threshold voltage and the uniformity of the tunneling current of the memory device of the present invention.

In order to make the above features and advantages of the present invention more apparent, the following is a special The embodiments are described in detail below in conjunction with the drawings.

10‧‧‧ Ditch

20‧‧‧Isolation structure

100‧‧‧Base

110‧‧‧ Well Area

120‧‧‧Tunnel dielectric layer

130‧‧‧First conductor layer

140‧‧‧ Cover layer

145‧‧‧ surface treatment process

150‧‧‧Barrier layer

160‧‧‧Interruptor dielectric layer

170‧‧‧Second conductor layer

1A-1G are schematic cross-sectional views showing a manufacturing process of a memory device according to an embodiment of the invention.

1A-1G are schematic cross-sectional views showing a manufacturing process of a memory device according to an embodiment of the invention.

Referring to FIG. 1A, a substrate 100 is provided. The substrate 100 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator (SOI)). The semiconductor is, for example, an atom of the IVA group, such as ruthenium or osmium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of Group IVA, such as tantalum carbide or germanium telluride, or a semiconductor compound formed of a group IIIA atom and a group VA atom, such as gallium arsenide.

Next, a well region 110 is formed in the substrate 100. The well region 110 can be formed by a patterned mask layer and an ion implantation process. In one embodiment, the substrate 100 has a first conductivity type; the well region 110 also has a first conductivity type, wherein the first conductivity type is, for example, a P type. In another embodiment, the substrate 100 has a first conductivity type; the well region 110 has a second conductivity type, wherein the first conductivity type is, for example, an N type; and the second conductivity type is, for example, a P type.

A tunneling dielectric layer 120 is formed over the well region 110. The tunneling dielectric layer 120 can be composed of a single material layer. The single material layer is, for example, a low dielectric constant material or a high dielectric constant material. The low dielectric constant material is a dielectric material having a dielectric constant of less than 4, such as ruthenium oxide or ruthenium oxynitride. The high dielectric constant material is a dielectric material having a dielectric constant higher than 4, such as HfAlO, HfO ₂ , Al ₂ O ₃ or Si ₃ N ₄ . The tunneling dielectric layer 120 can also select a two-layer stacked structure or a multilayer stacked structure that can increase the injection current according to the Band-gap Engineering Theory. The two-layer stacked structure is, for example, a two-layer stacked structure (represented by a low dielectric constant material/high dielectric constant material) composed of a low dielectric constant material and a high dielectric constant material, such as yttrium oxide/HfSiO, yttrium oxide/ HfO ₂ or yttrium oxide/tantalum nitride. The multilayer stacked structure is, for example, a multilayer stack structure composed of a low dielectric constant material, a high dielectric constant material, and a low dielectric constant material (represented by a low dielectric constant material/high dielectric constant material/low dielectric constant material), For example, yttrium oxide/tantalum nitride/yttria or yttrium oxide/Al ₂ O ₃ /yttrium oxide. The formation method of the tunnel dielectric layer 120 is formed, for example, by chemical vapor deposition, in situ steam generation (ISSG), low pressure radical oxidation (LPRO) or furnace tube oxidation.

Thereafter, a first conductor layer 130 is formed on the tunnel dielectric layer 120 (eg, as a floating gate). The material of the first conductor layer 130 is, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof can be formed by chemical vapor deposition. The dopant in the doped polysilicon is, for example, boron.

Referring to FIG. 1B, a patterned mask layer 140 is formed on the first conductor layer 130. The material of the mask layer 140 is, for example, a tantalum material, a metal material, an oxide or a back. The surface treatment process 145 is not reactive material or the like. The material of the mask layer 140 of the present invention is not limited thereto as long as there is a high etching selectivity between the material of the mask layer 140 and the material of the substrate 100, the tunnel dielectric layer 120, and the first conductor layer 130.

Referring to FIG. 1C, a trench 10 is formed in the first conductor layer 130, the tunnel dielectric layer 120, the well region 110, and the substrate 100. Specifically, the patterned mask layer 140 is used as an etching mask layer, and the first conductor layer 130 and the tunnel dielectric layer 120 are etched by a dry etching method (for example, a sputtering etching method, a reactive ion etching method, or the like). The well region 110 and the substrate 100 form a trench 10.

Referring to FIG. 1D, a barrier layer 150 is formed on sidewalls of the well region 110. In the present embodiment, the barrier layer 150 is formed on the top surface of the hard mask layer 140 and the side and bottom surfaces of the trench 10, but if the material of the side and bottom surfaces of the trench 10 is a silicon oxide compound or cannot be processed in the surface treatment process 145 The material and the like in which the reaction is generated, the barrier layer 150 is not formed on the side and the bottom surface of the trench 10, that is, the barrier layer 150 of the present invention may be a continuous or discontinuous surface. The material of the barrier layer 150 is different from the material of the subsequently formed isolation structure 20 (Fig. 1E). More specifically, in the selection of the material of the barrier layer 150, the diffusion rate of the dopant in the well region 110 in the barrier layer 150 can be selected to be much lower than in the subsequently formed isolation structure 20 (Fig. 1E). The material of the diffusion rate. In an embodiment, the material of the barrier layer 150 may include a nitrogen-containing material. The nitrogen-containing material is, for example, tantalum nitride (SiN), cerium oxynitride (SiON), or a combination thereof. In an embodiment, the barrier layer 150 may have a thickness of 5 angstroms to 500 angstroms. The method of forming the barrier layer 150 is, for example, performing a surface treatment process 145. The surface treatment process 145 is, for example, a nitriding treatment, a plasma treatment process, or an oxynitride treatment process. In an embodiment, the nitriding treatment comprises heat treatment, plasma treatment or nitrogen oxidation treatment. Specifically, the plasma treatment can be performed using Ar/N ₂ as a precursor gas (Precursor Gas) in a High-Vaccum Chamber at a temperature of 200 ° C to 1000 ° C. However, the invention is not limited thereto.

Next, referring to FIG. 1E, an isolation structure 20 is formed in the trench 10. The isolation structure 20 is formed by, for example, forming an insulating layer (not shown) on the mask layer 140, and the insulating layer fills the trench 10. The material of the insulating layer is, for example, an oxide. The oxide is, for example, spin-on glass (SOG) or high-density plasma oxide (HDP oxide), and the formation method thereof can be formed by chemical vapor deposition. Then, the first conductor layer 130 is used as a Stop Layer, and the insulating layer is removed by chemical mechanical polishing (CMP) to expose the top surface of the first conductor layer 130. Overpolish may be performed during the CMP process to ensure that the mask layer 140 and the barrier layer 150 on the first conductor layer 130 may be completely removed. Therefore, the top surface of the isolation structure 20 formed and the top surface of the first conductor layer 130 may have a slight height difference of about 100 angstroms to 1000 angstroms. However, the present invention is not limited thereto, and if the process conditions are properly controlled, the top surface of the isolation structure 20 may be coplanar with the top surface of the first conductor layer 130.

Referring to FIG. 1F, a gate dielectric layer 160 is formed on the first conductor layer 130 and the isolation structure 20. The inter-gate dielectric layer 160 is conformally formed along the first conductor layer 130 and the top surface of the isolation structure 20. The inter-gate dielectric layer 160 covers the top surface of the first conductor layer 130 and the isolation structure 20 and partially covers the barrier layer 150 between the first conductor layer 130 and the isolation structure 20. In one embodiment, 160 cases of the dielectric layer between the gates For example, the composite layer composed of an oxide layer/nitride layer/oxide layer (Oxide-Nitride-Oxide, ONO) may be three or more layers. The invention is not limited thereto, and the formation method may be Chemical vapor deposition, thermal oxidation, and the like.

Referring to FIG. 1G, a second conductor layer 170 is formed on the inter-gate dielectric layer 160 (for example, as a control gate). The method of forming the second conductor layer 170 is, for example, forming a layer of a conductor material. The material of the conductor material is, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof can be performed by chemical vapor deposition. The thickness of the second conductor layer 170 is, for example, 300 angstroms to 2000 angstroms. Thereafter, the conductor material layer is patterned using a lithography and etching process to form the second conductor layer 170.

1G, a memory device according to an embodiment of the invention includes a substrate 100, a well region 110, a tunneling dielectric layer 120, a first conductor layer 130, an isolation structure 20, a barrier layer 150, an inter-gate dielectric layer 160, and The second conductor layer 170. Well zone 110 is located in substrate 100. The tunneling dielectric layer 120 is located on the well region 110. The first conductor layer 130 is located on the tunneling dielectric layer 120, and the first conductor layer 130 can be used as a floating gate. The isolation structure 20 passes through the first conductor layer 130, the tunnel dielectric layer 120, the well region 110, and extends into the substrate 100. The inter-gate dielectric layer 160 is located on the top surface of the first conductor layer 130 and the top surface of the isolation structure 20. The second conductor layer 170 is located on the inter-gate dielectric layer 160, and the second conductor layer 170 can serve as a control gate. The barrier layer 150 is between the isolation structure 20 and the first conductor layer 130, between the isolation structure 20 and the tunnel dielectric layer 120, and between the isolation structure 20 and the well region 110.

In the present invention, the material of the barrier layer 150 formed on the sidewall of the well region 110 is different from the isolation structure, and the doping dopant doped in the well region 110 can be prevented from being outwardly diffused. For example, when boron is doped in well region 110, the diffusion rate of boron in the barrier layer (e.g., tantalum nitride, hafnium oxynitride) 150 is much lower than that of boron in the isolation structure (e.g., hafnium oxide) 20. The rate, therefore, barrier layer 150 can prevent outward diffusion of boron doped in well region 110. In addition, the barrier layer 150 can also prevent the dopant in the first conductor layer 130 from diffusing outward.

In summary, the present invention forms a barrier layer on the sidewall of the well region and the first conductor layer, which can prevent or reduce the outward diffusion of dopant doping in the well region and the first conductor layer to improve the memory of the present invention. The uniformity of the threshold voltage of the component and the uniformity of the tunneling current. In addition, the present invention can form a barrier layer by surface treatment, improve the uniformity of the threshold voltage of the memory element, and the tunneling current without requiring an additional ion implantation process or increasing the thickness of the tunneling dielectric layer. Uniformity.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

20‧‧‧Isolation structure

100‧‧‧Base

110‧‧‧ Well Area

120‧‧‧Tunnel dielectric layer

130‧‧‧First conductor layer

150‧‧‧Barrier layer

160‧‧‧Interruptor dielectric layer

170‧‧‧Second conductor layer

Claims (10)

A memory element comprising: a well region located in a substrate; a tunneling dielectric layer on the well region; a first conductor layer on the tunneling dielectric layer; and an isolation structure at the first a conductor layer, the tunneling dielectric layer, the well region and the substrate; and a barrier layer between the isolation structure and the well region. The memory device of claim 1, further comprising: a gate dielectric layer on a top surface of the first conductor layer and a top surface of the isolation structure; and a second conductor layer located at the On the dielectric layer of the gate. The memory device of claim 1, wherein the barrier layer extends further between the isolation structure and the first conductor layer. The memory element of claim 1, wherein the barrier layer comprises a nitrogen-containing material. The memory element of claim 4, wherein the nitrogen-containing material comprises tantalum nitride or hafnium oxynitride. A method of fabricating a memory device, comprising: providing a substrate; forming a well region in the substrate; forming a tunneling dielectric layer on the well region; Forming a first conductor layer on the tunneling dielectric layer; forming a trench in the first conductor layer, the tunneling dielectric layer, the well region, and the substrate; and performing a surface treatment process to make the trench A barrier layer is formed on the side and the bottom surface. The method of manufacturing a memory device according to the sixth aspect of the invention, wherein the surface treatment process comprises a nitriding treatment, an oxynitridation treatment or a plasma treatment. The method of manufacturing a memory device according to claim 6, wherein the surface treatment process comprises a nitridation treatment, and the nitridation treatment comprises a heat treatment, a plasma treatment, or an oxynitridation treatment. The method of manufacturing a memory device according to claim 6, wherein the barrier layer comprises a nitrogen-containing material. The method of manufacturing a memory device according to claim 6, wherein the nitrogen-containing material comprises tantalum nitride or hafnium oxynitride.