TWI612643B - Memory device and manufacturing method of the same - Google Patents

Abstract

A memory component and a method of manufacturing the same. The memory device includes a substrate, a floating gate, a gate insulating layer, an inter-gate dielectric layer, and a control gate. The control gate has a multilayer structure of three or more layers, and at least one layer of the multilayer structure is metal Telluride layer.

Description

Memory element and method of manufacturing same

The present invention relates to a semiconductor technology, and more particularly to a memory device and a method of fabricating the same.

Non-volatile memory has become widely used in personal computers and electronic devices because it has the advantages of multiple data storage, reading, erasing, etc., and the stored data does not disappear after power-off. A memory component.

The word line in a non-volatile memory is typically a metal telluride layer formed on a control gate. Wherein, in order to remove impurities in the metal telluride layer, the metal telluride layer is usually subjected to heat treatment after forming the metal telluride layer. However, the metal telluride in the metal telluride layer may diffuse into the control gate due to this heat treatment, and even the metal telluride contacts the inter-gate dielectric layer (IPD), and causes the dielectric layer capacitance failure between the gates, the gate The dielectric layer has disadvantages such as reduced breakdown voltage and reduced component reliability.

1 is a transmission electron microscope (TEM) photograph of a conventional memory device.

Referring to FIG. 1, the memory device includes a substrate 100, an isolation structure 102 in the substrate 100, a floating gate 104, a gate insulating layer 106, an inter-gate dielectric layer 108, and a control gate 110. The control gate 110 is generally of a two-layer structure, including a first layer 1101 filled between the floating gates 104 and a second layer 1102 thereon. The first layer 1101 is polycrystalline germanium, and the second layer 1102 is metal germanide. . In the memory device of FIG. 1, the metal telluride of the second layer 1102 is diffused into the first layer 1101 by heat treatment, and even at the looped portion, the metal telluride has directly contacted the inter-gate dielectric layer 108. This causes disadvantages such as capacitor failure of the gate dielectric layer 108, a breakdown voltage of the inter-gate dielectric layer 108, and a decrease in device reliability.

In view of the above, the present invention provides a memory device and a method of fabricating the same, which can prevent diffusion of a metal telluride in a metal telluride layer due to heat treatment to contact a dielectric layer between gates, and to provide semiconductor devices with good reliability.

The invention provides a memory device comprising a floating gate, a gate insulating layer, a gate dielectric layer and a control gate. The floating gate is located on the substrate. The gate insulating layer is between the floating gate and the substrate. The gate dielectric layer is on the floating gate. The control gate is located on the dielectric layer between the gates and has a multilayer structure of three or more layers, and at least one layer of the multilayer structure is a metal halide layer.

In an embodiment of the invention, the control gate includes a first layer, a second layer, and a third layer. The second layer is located between the first layer and the third layer.

In an embodiment of the invention, the thickness of the first layer and the second layer of the control gate is less than the thickness of the third layer.

In an embodiment of the invention, the grain size of the first layer of the control gate is smaller than the grain size of the second layer and the third layer.

In an embodiment of the invention, at least one layer of the control gate is a carbon doped polysilicon.

The invention further provides a method of fabricating a memory device, comprising sequentially forming a gate insulating layer and a floating gate on a substrate. The floating gate and the gate insulating layer are patterned, and a plurality of isolation structures are formed in the substrate, the surface of the isolation structure being lower than the surface of the floating gate. A dielectric layer between the gates is formed on the floating gate and the isolation structure. A control gate is formed on the dielectric layer of the gate, and the control gate has a multi-layer structure of three or more layers, at least one of which is a metal telluride layer.

In still another embodiment of the present invention, the method of forming the control gate includes sequentially forming a first layer, a second layer, and a third layer on the inter-gate dielectric layer.

In still another embodiment of the present invention, carbon may be doped during the formation of the first layer.

In still another embodiment of the present invention, carbon may be doped during the formation of the second layer.

In still another embodiment of the present invention, heat treatment may be performed after forming the metal halide layer.

Based on the above, the present invention can prevent the metal telluride layer from diffusing contact with the inter-gate dielectric layer by heat treatment by making the control gate of the memory element have a multilayer structure of three or more layers, and the semiconductor element has a good semiconductor element. Reliability.

The above described features and advantages of the invention will be apparent from the following description.

2A-2H are schematic cross-sectional views showing a manufacturing process of a memory device according to an embodiment of the invention.

Referring to FIG. 2A, a gate insulating layer 202 is formed on the substrate 200. In the present embodiment, the substrate 200 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a silicon on insulator (SOI). The semiconductor is, for example, an atom of the IVA group, such as ruthenium or osmium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of Group IVA, such as tantalum carbide or germanium telluride, or a semiconductor compound formed of a group IIIA atom and a group VA atom, such as gallium arsenide. The substrate 200 may have a doping, and the doping of the substrate 200 may be a P-type or an N-type. The P-type doping may be a Group IIIA ion, such as a boron ion. The N-type doping may be a Group VA ion such as arsenic or phosphorus.

In the present embodiment, the gate insulating layer 202 may be composed of a single material layer. The single material layer is, for example, a low dielectric constant material or a high dielectric constant material. The low dielectric constant material is a dielectric material having a dielectric constant of less than 4, such as ruthenium oxide or ruthenium oxynitride. The high dielectric constant material is a dielectric material having a dielectric constant higher than 4, such as HfAlO, HfO ₂ , Al ₂ O ₃ or Si ₃ N ₄ . The gate insulating layer 202 can also select a two-layer stacked structure or a multilayer stacked structure that can increase the injection current according to a band-gap engineering (BE) theory. The two-layer stacked structure is, for example, a two-layer stacked structure (represented by a low dielectric constant material/high dielectric constant material) composed of a low dielectric constant material and a high dielectric constant material, such as yttrium oxide/HfSiO, yttrium oxide/ HfO ₂ or yttrium oxide/tantalum nitride. The multilayer stacked structure is, for example, a multilayer stack structure composed of a low dielectric constant material, a high dielectric constant material, and a low dielectric constant material (represented by a low dielectric constant material/high dielectric constant material/low dielectric constant material), For example, yttrium oxide/tantalum nitride/yttria or yttrium oxide/Al ₂ O ₃ /yttrium oxide. The method of forming the gate insulating layer 202 is, for example, a thermal oxidation method or a chemical vapor deposition method.

Referring to FIG. 2A, a conductor layer 204 is further formed on the gate insulating layer 202. The material of the conductor layer 204 is, for example, a stacked layer of a polycrystalline germanium (including doped polysilicon), a polycrystalline germanium metal or a combination thereof, a metal layer or an applicable conductor, and the conductive layer 204 is formed by, for example, chemical vapor deposition or physics. Vapor deposition method. Next, a patterned mask layer 205 is formed on the conductor layer 204. The patterned mask layer 205 can be a single material layer or a two layer material layer. In an embodiment, the patterned mask layer 205 is, for example, a patterned photoresist layer.

Then, referring to FIG. 2B, an etching process is performed by patterning the mask layer 205 as a mask to pattern the conductor layer 204 and the gate insulating layer 202 to form a floating gate 204a and a gate insulating layer 202a. A plurality of trenches 206 are formed in the substrate 200a. The etching process is, for example, an anisotropic etching method such as a dry etching method.

Next, referring to FIG. 2C, the patterned mask layer 205 is removed, and then an insulating material layer 208 is formed on the substrate 200a, and the insulating material is filled into the trench 206 and covers the floating gate 204a. The above method of removing the patterned mask layer 205 is, for example, a dry removal method, a wet removal method, or a combination thereof. The material of the insulating material layer 208 is, for example, cerium oxide or borophosphonium glass, and the method of forming it is, for example, a chemical vapor deposition method.

Next, referring to FIG. 2D, the insulating material layer 208 on the floating gate 204a is removed and an insulating material layer 208a is formed in the trench 206. The method of removal can be carried out using a chemical mechanical polishing process, but is not limited thereto. In another embodiment, it can also be carried out using a wet etching method.

Then, referring to FIG. 2E, a portion of the insulating material layer 208a in the trench 206 is removed to form an isolation structure 208b. The surface 208s of the isolation structure 208b is lower than the surface 204s of the floating gate 204a. A method of removing a portion of the insulating material layer 208a is, for example, a wet etching method or a dry etching method.

Then, referring to FIG. 2F, a gate dielectric layer 210 is formed on the floating gate 204a and the isolation structure 208b. The inter-gate dielectric layer 210 may be a single layer or have multiple layers such as an ONO structure. In this embodiment, the inter-gate dielectric layer 210 is exemplified by a three-layer structure, wherein the inter-gate dielectric layer 210 includes a dielectric layer 2101, a dielectric layer 2102, and a dielectric layer 2103, and the dielectric layer 2103 is located. On the electrical layer 2102, a dielectric layer 2102 is located on the dielectric layer 2101. The material of the dielectric layer 2101 and the dielectric layer 2103, such as cerium oxide or other insulating material, is formed by, for example, chemical vapor deposition or thermal oxidation. The material of the dielectric layer 2102, such as tantalum nitride or other insulating material, is formed by, for example, chemical vapor deposition or thermal nitridation.

Next, referring to FIG. 2G, a stacked structure 212 is formed on the inter-gate dielectric layer 210, and the stacked structure 212 is a polycrystalline germanium structure of three or more layers. In this embodiment, the stack structure 212 is formed by sequentially forming a first layer 2121, a second material layer 2122, and a third material layer 2123 on the inter-gate dielectric layer 210, and the forming method is, for example, using chemical vapor deposition. The method is either physical vapor deposition; then, the three layers 2121, 2122, and 2123 are patterned to obtain a stacked structure 212.

In another embodiment of the present invention, carbon may be doped during the formation of the first layer 2121 to control the grain of the first layer 2121 at 10 nm to 20 nm, which helps to fill the floating gate 204a. The space between. In another embodiment of the invention, carbon may also be doped during the formation of the second material layer 2122. By using at least one of the first layer 2121 and the second material layer 2122 as a carbon-doped polysilicon, the grain size of the polycrystalline silicon in at least one of the first layer 2121 and the second material layer 2122 can be reduced. Strengthen the barrier to metal telluride.

In another embodiment of the invention, the layers in stack structure 212 have different grain sizes. By having the various layers in the stack structure 212 have different grain sizes, the barrier capability to metal telluride can be enhanced. In an embodiment of the invention, the grain size of the first layer 2121 is smaller than the grain size of the second material layer 2122 and the third material layer 2123.

In an embodiment of the present invention, the layers in the stacked structure 212 have different thicknesses, wherein the thickness of the first layer 2121 is, for example, 200 Å to 400 Å, and the thickness of the second material layer 2122 is, for example, 100 Å to 300 Å, and the third material layer. The thickness of 2123 is, for example, 400 Å to 600 Å. By controlling the thickness of each layer in the stacked structure 212 within the above range, it is possible to prevent the metal telluride from contacting the inter-gate dielectric layer while maintaining the thickness of the control gate so that the control gate is not excessively thick, thereby avoiding the control gate. Extreme thickness unevenness or uneven etching.

In another embodiment of the invention, the layers in stack structure 212 have different thicknesses. By having different thicknesses of the layers in the stacked structure 212, the grain size of each layer of polycrystalline germanium in the stacked structure 212 can be further controlled, so that the grain size of each layer of polycrystalline germanium in the stacked structure 212 is different, and the barrier property against the metal telluride is enhanced. In an embodiment of the invention, the thickness of the first layer 2121 and the second material layer 2122 is less than the thickness of the third material layer 2123.

The formation of the stacked structure 212 having three polysilicon layers is exemplified in the present invention, but the present invention is not limited thereto. The stacked structure may be formed to have four or more layers as long as it has a multilayer structure of three or more layers.

Thereafter, referring to FIG. 2H, a metal layer (not shown) capable of forming a metal halide, such as cobalt or nickel, is deposited on the stacked structure 212. The deposition method of the metal layer is, for example, a chemical vapor deposition method or a physical vapor deposition method. After depositing the metal layer, heat treatment is performed to react the metal layer with the second material layer 2122 and the third material layer 2123 to form the second layer 2122a and the third layer 2123a, thereby forming the control gate 212a. The material of the second layer 2122a and the third layer 2123a is, for example, cobalt ruthenium, nickel ruthenium or other applicable materials. In an embodiment of the invention, the second layer 2122a and the third layer 2123a are cobalt ruthenium. In an embodiment of the invention, the heat treatment is rapid temperature rise treatment (RTP). In the present embodiment, by forming the control gate 212a to have a multilayer structure of three or more layers, it is possible to effectively prevent the metal telluride in the second layer 2122a and the third layer 2123a from being diffused due to heat treatment in a subsequent process. The inter-gate dielectric layer 210 is contacted and the semiconductor element is provided with good reliability.

After the second layer 2122a and the third layer 2123a are formed, heat treatment may be further performed. The heat treatment is performed, for example, at a temperature of 800 ° C to 900 ° C for 60 seconds to 120 seconds to remove impurities or impurities in the inter-gate dielectric layer such as hafnium oxide or tantalum nitride.

Referring again to FIG. 2H, the memory device of the embodiment of the present invention includes a floating gate 204a, a gate insulating layer 202a, an isolation structure 208b, a dielectric layer 2101, a dielectric layer 2102, a dielectric layer 2103, and a control gate 212a. .

The material of the floating gate 204a is, for example, a stacked layer of polycrystalline germanium (including doped polysilicon), polycrystalline germanium metal or a combination thereof, a metal layer or an applicable conductor.

The gate insulating layer 202a may be composed of a single material layer. The single material layer is, for example, a low dielectric constant material or a high dielectric constant material. The gate insulating layer 202a is located between the floating gate 204a and the substrate 200. The gate insulating layer 202a can also select a two-layer stacked structure or a multilayer stacked structure that can increase the injection current according to the energy gap engineering theory.

The isolation structure 208b is used to isolate the adjacent two memory elements 20. The material of the isolation structure 208b may be an insulating material such as yttrium oxide or borophosphon glass. The isolation structure 208b is located in the substrate 200 between adjacent two floating gates 204a.

The inter-gate dielectric layer 210 can include a dielectric layer 2101, a dielectric layer 2102, and a dielectric layer 2103. The material of the dielectric layer 2101 and the dielectric layer 2103 includes cerium oxide or other insulating material, and the material of the dielectric layer 2102 includes tantalum nitride or other insulating material.

Control gate 212a covers floating gates 204a of a plurality of memory elements 20 and covers isolation structures 208b that isolate adjacent two memory elements 20. The control gate 212a includes a first layer 2121, a second layer 2122a and a third layer 2123a, and a second layer 2122a is located between the first layer 2121 and the third layer 2123a, wherein the first layer 2121 is polycrystalline germanium, and the second layer 2122a The third layer 2123a is a metal halide. In another embodiment, the first layer 2121 can be a carbon doped polysilicon. Additionally, in an embodiment, the layers in the control gate 212a can have different grain sizes. For example, the grain size of the first layer 2121 may be smaller than the grain size of the second layer 2122a and the third layer 2123a. In another embodiment, the layers in the control gate 212a can have different thicknesses. For example, the thickness of the first layer 2121 and the second layer 2122a may be less than the thickness of the third layer 2123a. The material of the second layer 2122a and the third layer 2123a is, for example, cobalt ruthenium, nickel ruthenium or other applicable materials. In an embodiment of the invention, the second layer 2122a and the third layer 2123a are cobalt ruthenium.

The above embodiment has exemplified the control gate 212a having a three-layer structure, but the present invention is not limited thereto. The control gate may have a multilayer structure of three or more layers, and may have four or more layers. By having the control gate 212a having a multilayer structure of three or more layers, it is possible to effectively prevent diffusion of the metal germanide in the second layer 2122a and the third layer 2123a due to heat treatment to contact the inter-gate dielectric layer 210, and to have the semiconductor element Good reliability.

An example is given below to confirm the efficacy of the present invention, but the scope of the present invention is not limited to the following.

<Example>

A memory element as shown in Fig. 2H was fabricated, and after 2 minutes of rapid thermal processing (RTP) at 850 ° C, its structure was observed and shown in Fig. 3. Wherein, in the control gate 312 on the inter-gate dielectric layer 310, the first layer 3121 has a thickness of 300 Å, the second layer 3122 has a thickness of 200 Å, and the third layer 3123 has a thickness of 500 Å, and the first layer 3121 has a thickness of 500 Å. The grain size is 15 nm to 20 nm, the grain size of the second layer 3122 is 10 nm to 20 nm, the grain size of the third layer 3123 is 30 nm to 40 nm, and the second layer 3122 and the third layer 2123 It is cobalt ruthenium (CoSi ₂ ).

Figure 3 is a transmission electron microscope (TEM) photograph of a memory element in the example.

Referring to FIG. 3 , in the present example, the metal germanide in the second layer 3122 and the third layer 3123 does not contact the inter-gate dielectric layer 310 due to the heat treatment, thereby avoiding the capacitor failure of the inter-gate dielectric layer 310 and the gate. The breakdown voltage of the dielectric layer 310 is lowered, and the reliability of the element is lowered.

As described above, the present invention uses a conductor layer of a multilayer structure of three or more layers as a gate structure, and can be applied to various semiconductor elements, for example, as a control gate of a memory element, thereby preventing metal deuteration. The fact that the layer diffuses into contact with the inter-gate dielectric layer due to heat treatment occurs, and the semiconductor element has good reliability. And the process of the present invention can be integrated with existing processes.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

20‧‧‧ memory components

100, 200, 200a‧‧‧ base

102, 208b‧‧‧ isolation structure

104, 204a‧‧‧Floating gate

106, 202, 202a‧‧‧ gate insulation

108, 210, 310‧‧‧ Inter-gate dielectric layer

110, 212a, 312‧‧‧ control gate

1101, 2121, 3121‧‧‧ first floor

1102, 2122a, 3122‧‧‧ second floor

204‧‧‧Conductor layer

204s‧‧‧ Surface of floating gate 204a

205‧‧‧ patterned mask layer

206‧‧‧ Ditch

208, 208a‧‧‧layer of insulating material

208s‧‧‧ Surface of isolation structure 208b

2101, 2102, 2103‧‧‧ dielectric layer

212‧‧‧Stack structure

2122‧‧‧Second material layer

2123‧‧‧ third material layer

2123a, 3123‧‧‧ third floor

1 is a transmission electron microscope (TEM) photograph of a conventional memory device. 2A-2H are schematic cross-sectional views showing a manufacturing process of a memory device according to an embodiment of the invention. Figure 3 is a transmission electron micrograph of a memory element in an example.

20‧‧‧ memory components

200a‧‧‧Base

202a‧‧‧gate insulation

204a‧‧‧Floating gate

208b‧‧‧Isolation structure

210‧‧‧Inter-tile dielectric layer

2101, 2102, 2103‧‧‧ dielectric layer

212a‧‧‧Control gate

2121‧‧‧ first floor

2122a‧‧‧ second floor

2123a‧‧‧ third floor

Claims (8)

A memory device comprising: a floating gate on a substrate; a gate insulating layer between the floating gate and the substrate; a gate dielectric layer on the floating gate; a control gate on the inter-gate dielectric layer, the control gate comprising a first layer, a second layer and a third layer, the second layer being located in the first layer and the third layer The first layer is a polycrystalline germanium layer, and the second layer and the third layer are metal germanide layers. The memory device of claim 1, wherein a thickness of the first layer of the control gate and the second layer of the control gate is smaller than the number of the control gate The thickness of the three layers. The memory device of claim 1, wherein the first layer of the control gate has a grain size smaller than the second layer of the control gate and the control gate The grain size of the third layer. The memory device of claim 1, wherein the first layer of the control gate is a carbon doped polysilicon. A method of fabricating a memory device, comprising: sequentially forming a gate insulating layer and a floating gate on a substrate; patterning the floating gate and the gate insulating layer; forming a plurality of layers in the substrate An isolation structure, a surface of the isolation structure being lower than a surface of the floating gate; Forming a gate dielectric layer on the floating gate and the isolation structure; and forming a control gate on the inter-gate dielectric layer, the control gate having a multilayer structure of three or more layers, wherein the formation The method for controlling a gate includes sequentially forming a first layer, a second layer, and a third layer on the inter-gate dielectric layer, wherein the first layer is a polysilicon layer, and the second layer is The third layer is a metal telluride layer. The method of manufacturing a memory device according to claim 5, wherein the forming of the first layer includes doping carbon. The method of manufacturing a memory device according to claim 5, wherein the forming of the second layer comprises doping carbon. The method of manufacturing a memory device according to claim 5, wherein the forming of the metal telluride layer further comprises performing a heat treatment.