TW201622063A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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本發明是有關於一種半導體元件及其製造方法，且特別是有關於一種具有空氣間隙的半導體元件及其製造方法。The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having an air gap and a method of fabricating the same.
在目前提高半導體元件積集度的趨勢下，會依據設計規則縮小元件的尺寸。然而，隨著尺寸愈來愈小，電容-電阻延遲（resistor-capacitor delay，RC delay）以及各組成構件之間的電性干擾使得積體電路的速度受限，並影響其可靠性與穩定性。因此，電容-電阻延遲造成半導體元件效能降低，為目前亟需解決的問題。In the current trend of increasing the degree of integration of semiconductor components, the size of components will be reduced according to design rules. However, as the size gets smaller and smaller, the resistor-capacitor delay (RC delay) and the electrical interference between the components make the speed of the integrated circuit limited and affect its reliability and stability. . Therefore, the capacitance-resistance delay causes a decrease in the performance of the semiconductor element, which is an urgent problem to be solved.
本發明提供一種半導體元件及其製造方法，其在相鄰閘極結構之間形成空氣間隙，而能夠有效地防止閘極結構之間的電容-電阻延遲，並改善各組成構件之間的電性干擾，以進一步提升半導體元件的效率。The present invention provides a semiconductor device and a method of fabricating the same that form an air gap between adjacent gate structures, thereby effectively preventing capacitance-resistance delay between gate structures and improving electrical properties between constituent members Interference to further improve the efficiency of semiconductor components.
本發明提供一種半導體元件，包括配置於基底上的多個堆疊結構；以及配置於基底上，覆蓋堆疊結構的介電層。相鄰兩個堆疊結構之間具有空氣間隙，空氣間隙的頂端高於堆疊結構的頂端。The present invention provides a semiconductor device including a plurality of stacked structures disposed on a substrate; and a dielectric layer disposed on the substrate to cover the stacked structure. There is an air gap between two adjacent stacked structures, and the top end of the air gap is higher than the top end of the stacked structure.
依照本發明一實施例所述，在上述半導體元件中，所述空氣間隙具有一寬部與一窄部，所述寬部位於所述窄部之下。According to an embodiment of the invention, in the semiconductor device, the air gap has a wide portion and a narrow portion, and the wide portion is located below the narrow portion.
依照本發明一實施例所述，在上述半導體元件中，所述堆疊結構包括矽化金屬層，所述矽化金屬層具有第一部分與第二部分，所述第一部分位於所述第二部分之下，所述矽化金屬層的所述第一部分的最大寬度小於所述矽化金屬層的所述第二部分的最大寬度，所述空氣間隙的所述寬部的最大寬度位於相鄰兩個所述堆疊結構之間，並且低於所述矽化金屬層的所述第二部分。According to an embodiment of the present invention, in the above semiconductor device, the stacked structure includes a deuterated metal layer, the deuterated metal layer having a first portion and a second portion, the first portion being located under the second portion, a maximum width of the first portion of the deuterated metal layer is less than a maximum width of the second portion of the deuterated metal layer, and a maximum width of the wide portion of the air gap is located in two adjacent stacked structures Between and below the second portion of the deuterated metal layer.
依照本發明一實施例所述，在上述半導體元件中，所述空氣間隙具有一寬部、第一窄部與第二窄部，所述第一窄部位於所述第二窄部之下，所述寬部位於所述第一窄部與所述第二窄部之間。According to an embodiment of the present invention, in the semiconductor device, the air gap has a wide portion, a first narrow portion and a second narrow portion, and the first narrow portion is located below the second narrow portion. The wide portion is located between the first narrow portion and the second narrow portion.
依照本發明一實施例所述，在上述半導體元件中，所述堆疊結構包括矽化金屬層與硬罩幕層，所述硬罩幕層配置於所述矽化金屬層上，所述矽化金屬層具有第一部分與第二部分，所述矽化金屬層的所述第一部分位於所述矽化金屬層的所述第二部分之下，所述矽化金屬層的所述第一部分的最大寬度大於所述矽化金屬層的所述第二部分的最大寬度，所述空氣間隙的所述寬部的最大寬度位於相鄰兩個所述堆疊結構之間，並且低於所述硬罩幕層，高於所述矽化金屬層的所述第一部分。According to an embodiment of the present invention, in the above semiconductor device, the stacked structure includes a deuterated metal layer and a hard mask layer, and the hard mask layer is disposed on the deuterated metal layer, and the deuterated metal layer has a first portion and a second portion, the first portion of the deuterated metal layer being under the second portion of the deuterated metal layer, the first portion of the deuterated metal layer having a maximum width greater than the deuterated metal a maximum width of the second portion of the layer, a maximum width of the wide portion of the air gap being between adjacent two of the stacked structures, and lower than the hard mask layer, higher than the deuteration The first portion of the metal layer.
依照本發明一實施例所述，在上述半導體元件中，所述空氣間隙的剖面為保齡球瓶形、飛碟形。According to an embodiment of the invention, in the semiconductor device, the cross section of the air gap is a bowling pin shape or a flying saucer shape.
依照本發明一實施例所述，在上述半導體元件中，所述矽化金屬層的剖面為磨菇形、倒T形。According to an embodiment of the invention, in the semiconductor device, the cross section of the deuterated metal layer is a mushroom shape or an inverted T shape.
本發明還提供一種半導體元件的製造方法，包括：於基底上形成多個堆疊結構。於相鄰兩個所述堆疊結構之間形成第一介電層，所述第一介電層之上表面低於所述堆疊結構之上表面，裸露出部分所述堆疊結構。使部分所述堆疊結構形成為矽化金屬層。移除部分所述第一介電層，以形成多數個凹槽。於所述基底上形成第二介電層，覆蓋所述堆疊結構，並在相鄰兩個所述堆疊結構之間形成空氣間隙，所述空氣間隙的頂端高於所述堆疊結構的頂端。The present invention also provides a method of fabricating a semiconductor device, comprising: forming a plurality of stacked structures on a substrate. A first dielectric layer is formed between two adjacent stacked structures, and an upper surface of the first dielectric layer is lower than an upper surface of the stacked structure, and a portion of the stacked structure is exposed. A portion of the stacked structure is formed as a deuterated metal layer. A portion of the first dielectric layer is removed to form a plurality of grooves. Forming a second dielectric layer on the substrate, covering the stacked structure, and forming an air gap between two adjacent stacked structures, the top end of the air gap being higher than the top end of the stacked structure.
依照本發明一實施例所述，上述半導體元件的製造方法更包括：於裸露出的部分所述堆疊結構的側壁上形成間隙壁，所述間隙壁包括非晶矽或多晶矽。使所述間隙壁形成為部分所述矽化金屬層。According to an embodiment of the present invention, the method of fabricating the semiconductor device further includes forming a spacer on a sidewall of the exposed portion of the stacked structure, the spacer comprising an amorphous germanium or a polysilicon. The spacer is formed into a portion of the deuterated metal layer.
依照本發明一實施例所述，在上述半導體元件的製造方法中，所述矽化金屬層具有第一部分與第二部分，所述第一部分位於所述第二部分之下，所述第一部分的最大寬度小於所述第二部分的最大寬度。According to an embodiment of the present invention, in the method of fabricating the semiconductor device, the deuterated metal layer has a first portion and a second portion, the first portion being located below the second portion, and the first portion being the largest The width is less than the maximum width of the second portion.
依照本發明一實施例所述，在上述半導體元件的製造方法中，所述矽化金屬層具有第一部分與第二部分，所述第一部分位於所述第二部分之下，所述第一部分的最大寬度大於所述第二部分的最大寬度。According to an embodiment of the present invention, in the method of fabricating the semiconductor device, the deuterated metal layer has a first portion and a second portion, the first portion being located below the second portion, and the first portion being the largest The width is greater than the maximum width of the second portion.
基於上述，本發明提供的半導體元件及其製造方法，可在相鄰兩個閘極結構之間形成空氣間隙，且所形成的空氣間隙之高度高於閘極結構，因此可有效地防止閘極結構之間的電容-電阻延遲，並改善各組成構件之間的電性干擾，進一步提升半導體元件的效能。Based on the above, the semiconductor device and the method of manufacturing the same according to the present invention can form an air gap between adjacent two gate structures, and the height of the formed air gap is higher than that of the gate structure, thereby effectively preventing the gate The capacitance-resistance between the structures is delayed, and the electrical interference between the constituent members is improved, further improving the performance of the semiconductor device.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
在以下的實施例中，相同或相似的元件符號代表相同或相似的構件，其可以相同或相似的材料，或是可以以相同或是相似的方法來形成。舉例來說，第二實施例中的第一介電材料層210的材料與形成方法可以是與第一實施例中的第一介電材料層110的材料相同或相似，或是可以以相同或相似的方法來形成。In the following embodiments, the same or similar component symbols represent the same or similar components, which may be the same or similar materials, or may be formed in the same or similar manner. For example, the material and formation method of the first dielectric material layer 210 in the second embodiment may be the same as or similar to the material of the first dielectric material layer 110 in the first embodiment, or may be the same or A similar approach to form.
圖1A至圖1H為根據本發明第一實施例所繪示之半導體元件的製造流程剖面示意圖。1A to 1H are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.
請參照圖1A，提供基底100，基底100例如為半導體基底、半導體化合物基底或是絕緣層上有半導體基底（Semiconductor Over Insulator，SOI）。半導體例如是IVA族的原子，例如矽或鍺。半導體化合物例如是IVA族的原子所形成之半導體化合物，例如是碳化矽或是矽化鍺，或是IIIA族原子與VA族原子所形成之半導體化合物，例如是砷化鎵。基底100可以具有摻雜，基底100的摻雜可以是P型或N型。P型的摻雜可以是IIIA族離子，例如是硼離子。N型摻雜可以是VA族離子，例如是砷或是磷。Referring to FIG. 1A, a substrate 100 is provided. The substrate 100 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator (SOI)). The semiconductor is, for example, an atom of the IVA group, such as ruthenium or osmium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of Group IVA, such as tantalum carbide or germanium telluride, or a semiconductor compound formed of a group IIIA atom and a group VA atom, such as gallium arsenide. The substrate 100 may have a doping, and the doping of the substrate 100 may be a P-type or an N-type. The P-type doping may be a Group IIIA ion, such as a boron ion. The N-type doping may be a Group VA ion such as arsenic or phosphorus.
請繼續參照圖1A，於基底100上形成多個堆疊結構108。在一實施例中，堆疊結構108包括穿隧介電層101、電荷儲存層102以及導體層104。穿隧介電層101，位於所對應的電荷儲存層102與基底100之間。穿隧介電層101的材料例如是氧化矽、氮化矽、氮氧化矽或其組合，形成的方法例如是化學氣相沉積法或是熱氧化法。在一實施例中，電荷儲存層102為浮置閘，其材料包括導體，例如為多晶矽。在另一實施例中，電荷儲存層102為電荷捕陷層，其是由介電材料形成。電荷捕陷層可以是堆疊層，例如是ONO（oxide-nitride-oxide）層，亦即其中包括氧化矽/氮化矽/氧化矽三層，形成的方法例如是化學氣相沉積法。導體層104做為控制閘，其材料可以是導體，例如是摻雜多晶矽、多晶矽化金屬、金屬層或其他可應用之導體，形成的方法例如是化學氣相沉積法。在一實施例中，電荷儲存層102為浮置閘，電荷儲存層102與導體層104之間還包括層間介電層106。層間介電層106可以是堆疊層，例如是ONO層，形成的方法例如是化學氣相沉積法或是熱氧化法。Referring to FIG. 1A, a plurality of stacked structures 108 are formed on the substrate 100. In an embodiment, the stacked structure 108 includes a tunneling dielectric layer 101, a charge storage layer 102, and a conductor layer 104. The tunneling dielectric layer 101 is located between the corresponding charge storage layer 102 and the substrate 100. The material of the tunneling dielectric layer 101 is, for example, hafnium oxide, tantalum nitride, hafnium oxynitride or a combination thereof, and the formation method is, for example, a chemical vapor deposition method or a thermal oxidation method. In one embodiment, the charge storage layer 102 is a floating gate, the material of which includes a conductor, such as a polysilicon. In another embodiment, the charge storage layer 102 is a charge trapping layer that is formed of a dielectric material. The charge trap layer may be a stacked layer, for example, an ONO (oxide-nitride-oxide) layer, that is, a layer including yttrium oxide/yttria/yttria, which is formed by, for example, chemical vapor deposition. The conductor layer 104 serves as a control gate, and the material thereof may be a conductor such as a doped polysilicon, a polycrystalline metal, a metal layer or other applicable conductor, and the formed method is, for example, a chemical vapor deposition method. In one embodiment, the charge storage layer 102 is a floating gate, and the interlayer dielectric layer 106 is further included between the charge storage layer 102 and the conductor layer 104. The interlayer dielectric layer 106 may be a stacked layer, such as an ONO layer, formed by, for example, a chemical vapor deposition method or a thermal oxidation method.
請參照圖1B，在基底100上形成第一介電材料層110，以將第一介電材料層110填入於多個堆疊結構108之間。第一介電材料層110的材料例如是氧化物。氧化物例如是旋塗式玻璃（Spin-On Glass, SOG）、高密度電漿氧化物（High Density Plasma, HDP Oxide）或未經摻雜的矽酸鹽玻璃（Undoped Silicate Glass, USG）。第一介電材料層110的形成方法例如是先進行化學氣相沉積法或是旋塗法，接著進行平坦化製程。平坦化製程可以是化學機械研磨製程或是回蝕刻製程。Referring to FIG. 1B, a first dielectric material layer 110 is formed on the substrate 100 to fill the first dielectric material layer 110 between the plurality of stacked structures 108. The material of the first dielectric material layer 110 is, for example, an oxide. The oxide is, for example, Spin-On Glass (SOG), High Density Plasma (HDP Oxide) or Undoped Silicate Glass (USG). The method of forming the first dielectric material layer 110 is, for example, first performing a chemical vapor deposition method or a spin coating method, followed by a planarization process. The planarization process can be a chemical mechanical polishing process or an etch back process.
請參照圖1C，移除部分第一介電材料層110，以形成第一介電層110a，並裸露出部分導體層104。在一實施例中，可以進行非等向性蝕刻，以移除部分第一介電材料層110，形成第一介電層110a，並裸露出部分導體層104。非等向性蝕刻例如是乾式蝕刻。Referring to FIG. 1C, a portion of the first dielectric material layer 110 is removed to form a first dielectric layer 110a, and a portion of the conductor layer 104 is exposed. In an embodiment, an anisotropic etch may be performed to remove a portion of the first dielectric material layer 110, form a first dielectric layer 110a, and expose a portion of the conductor layer 104. The anisotropic etch is, for example, a dry etch.
請參照圖1D與1E，於基底100上形成間隙壁材料層112，覆蓋裸露出的部分導體層104。間隙壁材料層112的材料包括導體，例如是非晶矽或多晶矽，形成間隙壁材料層112的方法例如是化學氣相沉積法。間隙壁材料層112的厚度例如是5nm～10nm。其後，移除部分間隙壁材料層112，於裸露出的部分導體層104的側壁上形成間隙壁112a。移除部分間隙壁材料層112的方法例如是進行非等向性蝕刻製程。Referring to FIGS. 1D and 1E, a spacer material layer 112 is formed on the substrate 100 to cover the exposed portion of the conductor layer 104. The material of the spacer material layer 112 includes a conductor such as an amorphous germanium or a polycrystalline germanium, and a method of forming the spacer material layer 112 is, for example, a chemical vapor deposition method. The thickness of the spacer material layer 112 is, for example, 5 nm to 10 nm. Thereafter, a portion of the spacer material layer 112 is removed, and a spacer 112a is formed on the sidewall of the exposed portion of the conductor layer 104. A method of removing a portion of the spacer material layer 112 is, for example, an anisotropic etching process.
請參照圖1F，對間隙壁112a與部分導體層104進行金屬矽化製程，以形成為矽化金屬層114。矽化金屬層114的材料可以是鈦、鎢、鈷、鎳、銅、鉬、鉭、鉺、鋯或鉑的矽化物。在一實施例中，矽化金屬層114的材料例如是矽化鈷（Cobalt Silicide，CoSi）。此時，所述金屬矽化製程例如是先沉積一層鈷，之後，進行第一快速熱製程（Rapid Thermal Process，RTP），接著進行矽化鈷選擇性蝕刻，移除未反應的鈷，之後再進行第二快速熱製程，以使鈷與間隙壁112a與部分導體層104中的矽反應，以形成材料為矽化鈷的矽化金屬層114。矽化金屬層114具有第一部分A1與第二部分A2。第一部分A1位於第二部分A2之下。第一部分A1的最大寬度小於第二部分A2的最大寬度。在一實施例中，第一部分A1的最大寬度為第二部分A2的最大寬度的60%～75%，使矽化金屬層114的剖面成為磨菇形。Referring to FIG. 1F, the spacer 112a and the portion of the conductor layer 104 are subjected to a metal deuteration process to form the deuterated metal layer 114. The material of the deuterated metal layer 114 may be a germanide of titanium, tungsten, cobalt, nickel, copper, molybdenum, niobium, tantalum, zirconium or platinum. In one embodiment, the material of the deuterated metal layer 114 is, for example, cobalt oxide (CoSi). At this time, the metal deuteration process is, for example, first depositing a layer of cobalt, and then performing a first Rapid Thermal Process (RTP), followed by selective etching of cobalt telluride to remove unreacted cobalt, and then performing the first A rapid thermal process is performed to react the cobalt with the spacers 112a and the germanium in the portion of the conductor layer 104 to form a deuterated metal layer 114 having a material of cobalt antimonide. The deuterated metal layer 114 has a first portion A1 and a second portion A2. The first part A1 is located below the second part A2. The maximum width of the first portion A1 is smaller than the maximum width of the second portion A2. In one embodiment, the maximum width of the first portion A1 is 60% to 75% of the maximum width of the second portion A2, so that the cross section of the deuterated metal layer 114 becomes a mushroom shape.
請參照圖1G，移除部分第一介電層110a，形成第一介電層110b。移除部分第一介電層110a的方法例如為進行濕式蝕刻製程或乾式蝕刻製程。第一介電層110b呈凹槽狀，覆蓋第一部分A1的側壁以及部分堆疊結構108a的側壁。堆疊結構108a包括穿隧介電層101、電荷儲存層102、層間介電層106以及導體層104與矽化金屬層114。第一介電層110b的厚度例如為5nm～10nm。Referring to FIG. 1G, a portion of the first dielectric layer 110a is removed to form a first dielectric layer 110b. The method of removing a portion of the first dielectric layer 110a is, for example, a wet etching process or a dry etching process. The first dielectric layer 110b has a groove shape covering the sidewall of the first portion A1 and the sidewall of the partial stacked structure 108a. The stacked structure 108a includes a tunneling dielectric layer 101, a charge storage layer 102, an interlayer dielectric layer 106, and a conductor layer 104 and a germanium metal layer 114. The thickness of the first dielectric layer 110b is, for example, 5 nm to 10 nm.
請參照圖1H，於基底100上形成第二介電層116，覆蓋堆疊結構108a，在相鄰兩個堆疊結構108a之間形成空氣間隙118。第二介電層116的材料例如是氧化物，其可與第一介電層110a的材料相同，亦可不同。第二介電層116的形成方法包括化學氣相沉積，例如是電漿輔助化學氣相沉積。適當控制第二介電層116的沉積速率，可減少或避免第二介電層116填入於第一介電層110b的凹槽之中，而形成具有足夠體積的空氣間隙118。Referring to FIG. 1H, a second dielectric layer 116 is formed on the substrate 100 to cover the stacked structure 108a, and an air gap 118 is formed between the adjacent two stacked structures 108a. The material of the second dielectric layer 116 is, for example, an oxide, which may be the same as or different from the material of the first dielectric layer 110a. The method of forming the second dielectric layer 116 includes chemical vapor deposition, such as plasma assisted chemical vapor deposition. By properly controlling the deposition rate of the second dielectric layer 116, the second dielectric layer 116 can be reduced or prevented from being filled into the recesses of the first dielectric layer 110b to form an air gap 118 having a sufficient volume.
在本發明的實施例中，空氣間隙118的頂端高於堆疊結構108a的頂端。更具體地說，空氣間隙118具有一寬部118a與一窄部118b。寬部118a位於窄部118b之下。寬部118a的最大寬度W11大於窄部118b的最大寬度W12。寬部118a的最大寬度W11位於相鄰兩個堆疊結構108a之間，並且低於矽化金屬層114的第二部分A2。窄部118b位於矽化金屬層114的第二部分A2之間，且窄部118b的頂端超過矽化金屬層114的第二部分A2的頂面。在一實施例中，空氣間隙118的剖面可為保齡球瓶形。In an embodiment of the invention, the top end of the air gap 118 is higher than the top end of the stack structure 108a. More specifically, the air gap 118 has a wide portion 118a and a narrow portion 118b. The wide portion 118a is located below the narrow portion 118b. The maximum width W11 of the wide portion 118a is greater than the maximum width W12 of the narrow portion 118b. The maximum width W11 of the wide portion 118a is located between the adjacent two stacked structures 108a and below the second portion A2 of the deuterated metal layer 114. The narrow portion 118b is located between the second portion A2 of the deuterated metal layer 114, and the top end of the narrow portion 118b exceeds the top surface of the second portion A2 of the deuterated metal layer 114. In an embodiment, the cross section of the air gap 118 may be a bowling pin shape.
圖2A至圖2F為根據本發明第二實施例所繪示之半導體元件的製造流程剖面示意圖。2A to 2F are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention.
請參照圖2A，依照上述第一實施例的方法與材料，在基底200上形成多個堆疊結構208。在一實施例中，堆疊結構208包括穿隧介電層201、電荷儲存層202、導體層204以及硬罩幕層222。在另一實施例中，堆疊結構208更包括層間介電層206，位於電荷儲存層202與導體層204之間。硬罩幕層222的材料例如是氧化矽、氮化矽、氮氧化矽、碳化矽、氮碳化矽或其組合，其形成的方法例如是化學氣相沉積法。硬罩幕層222的厚度例如是30nm～40nm。Referring to FIG. 2A, a plurality of stacked structures 208 are formed on the substrate 200 in accordance with the method and material of the first embodiment described above. In an embodiment, the stacked structure 208 includes a tunneling dielectric layer 201, a charge storage layer 202, a conductor layer 204, and a hard mask layer 222. In another embodiment, the stacked structure 208 further includes an interlayer dielectric layer 206 between the charge storage layer 202 and the conductor layer 204. The material of the hard mask layer 222 is, for example, cerium oxide, cerium nitride, cerium oxynitride, cerium carbide, cerium oxynitride or a combination thereof, which is formed by, for example, chemical vapor deposition. The thickness of the hard mask layer 222 is, for example, 30 nm to 40 nm.
請參照圖2B與2C，依照上述第一實施例的方法與材料，在基底200上形成第一介電材料層210，將第一介電材料層210填入於多個堆疊結構208之間。接著對第一介電材料層210進行非等向性蝕刻，以移除部分第一介電材料層210，形成第一介電層210a，並裸露出硬罩幕層222與部分導體層204。Referring to FIGS. 2B and 2C, in accordance with the method and material of the first embodiment described above, a first dielectric material layer 210 is formed on the substrate 200, and a first dielectric material layer 210 is filled between the plurality of stacked structures 208. The first dielectric material layer 210 is then anisotropically etched to remove a portion of the first dielectric material layer 210, forming a first dielectric layer 210a, and exposing the hard mask layer 222 and a portion of the conductor layer 204.
請參照圖2D，依照上述第一實施例的方法與材料，對部分導體層204進行金屬矽化製程，以形成為矽化金屬層214。矽化金屬層214具有第一部分B1與第二部分B2，第一部分B1位於第二部分B2之下。由於在金屬矽化製程中，導體層204裸露出的部分會有體積損失，故所形成的第一部分B1的最大寬度會大於第二部分B2的最大寬度。第二部分B2的最大寬度例如是第一部分B1的最大寬度的85%～90%。在一實施例中，矽化金屬層214的剖面成為倒T形。Referring to FIG. 2D, in accordance with the method and material of the first embodiment described above, a portion of the conductor layer 204 is subjected to a metal deuteration process to form a deuterated metal layer 214. The deuterated metal layer 214 has a first portion B1 and a second portion B2, the first portion B1 being located below the second portion B2. Since the exposed portion of the conductor layer 204 has a volume loss in the metal deuteration process, the maximum width of the first portion B1 formed is greater than the maximum width of the second portion B2. The maximum width of the second portion B2 is, for example, 85% to 90% of the maximum width of the first portion B1. In one embodiment, the cross-section of the deuterated metal layer 214 is inverted T-shaped.
請參照圖2E，依照上述第一實施例的方法與材料，移除部分第一介電層210a，以形成第一介電層210b。第一介電層210b呈凹槽狀，覆蓋第一部分B1的側壁以及部分堆疊結構208a的側壁。堆疊結構208a包括穿隧介電層201、電荷儲存層202、層間介電層206、導體層204、硬罩幕層222以及矽化金屬層214。第一介電層210b的厚度為5nm～10nm。Referring to FIG. 2E, in accordance with the method and material of the first embodiment described above, a portion of the first dielectric layer 210a is removed to form a first dielectric layer 210b. The first dielectric layer 210b has a groove shape covering the sidewall of the first portion B1 and the sidewall of the partial stacked structure 208a. The stacked structure 208a includes a tunneling dielectric layer 201, a charge storage layer 202, an interlayer dielectric layer 206, a conductor layer 204, a hard mask layer 222, and a germanium metal layer 214. The thickness of the first dielectric layer 210b is 5 nm to 10 nm.
請參照圖2F，依照上述第一實施例的方法與材料，於基底200上形成第二介電層216，覆蓋堆疊結構208a，在相鄰兩個堆疊結構208a之間形成空氣間隙218。第二介電層216的形成方法包括化學氣相沉積，例如是電漿輔助化學氣相沉積。適當控制第二介電層216的沉積速率，可減少或避免第二介電層216填入於第一介電層210b的凹槽之中，而形成具有足夠體積的空氣間隙218。Referring to FIG. 2F, in accordance with the method and material of the first embodiment described above, a second dielectric layer 216 is formed on the substrate 200, covering the stacked structure 208a, and an air gap 218 is formed between the adjacent two stacked structures 208a. The method of forming the second dielectric layer 216 includes chemical vapor deposition, such as plasma assisted chemical vapor deposition. By properly controlling the deposition rate of the second dielectric layer 216, the second dielectric layer 216 can be reduced or prevented from being filled into the recesses of the first dielectric layer 210b to form an air gap 218 having a sufficient volume.
空氣間隙218的頂端高於堆疊結構208a的頂端。空氣間隙218具有一寬部218b、第一窄部218a與第二窄部218c。第一窄部218a位於第二窄部218c之下，且寬部218b位於第一窄部218a與第二窄部218c之間。寬部218b的最大寬度W22大於第一窄部218a與第二窄部218c的最大寬度W21與W23。寬部218b的最大寬度W22位於相鄰兩個堆疊結構208a之間，並且低於硬罩幕層222，高於矽化金屬層214的第一部分B1。在一實施例中，空氣間隙218的剖面可為飛碟形。The top end of the air gap 218 is higher than the top end of the stacked structure 208a. The air gap 218 has a wide portion 218b, a first narrow portion 218a and a second narrow portion 218c. The first narrow portion 218a is located below the second narrow portion 218c, and the wide portion 218b is located between the first narrow portion 218a and the second narrow portion 218c. The maximum width W22 of the wide portion 218b is greater than the maximum widths W21 and W23 of the first narrow portion 218a and the second narrow portion 218c. The maximum width W22 of the wide portion 218b is located between the adjacent two stacked structures 208a and is lower than the hard mask layer 222 than the first portion B1 of the vaporized metal layer 214. In an embodiment, the cross section of the air gap 218 may be in the shape of a flying saucer.
請再次參照圖1H，根據本發明一實施例之半導體元件包括基底100、多個堆疊結構108a、以及介電層124。相鄰兩個堆疊結構108a之間具有空氣間隙118。堆疊結構108a包括矽化金屬層114。矽化金屬層114具有第一部分A1與第二部分A2。第一部分A1位於第二部分A2之下，第一部分A1的最大寬度小於所述第二部分A2的最大寬度。在一實施例中，第一部分A1的最大寬度為第二部分A2的最大寬度的60%～75%，使矽化金屬層114的剖面成為磨菇形。空氣間隙118的頂端高於堆疊結構108a的頂端。空氣間隙118具有一寬部118a與一窄部118b，寬部118a位於窄部118b之下，寬部118a的最大寬度W11大於窄部118b的最大寬度W12。在一實施例中，寬部118a的最大寬度W11位於相鄰兩個堆疊結構108a之間，並且低於矽化金屬層114的第二部分A2。空氣間隙118的剖面可為保齡球瓶形。Referring again to FIG. 1H, a semiconductor component in accordance with an embodiment of the present invention includes a substrate 100, a plurality of stacked structures 108a, and a dielectric layer 124. There is an air gap 118 between adjacent two stacked structures 108a. Stack structure 108a includes a deuterated metal layer 114. The deuterated metal layer 114 has a first portion A1 and a second portion A2. The first portion A1 is located below the second portion A2, and the maximum width of the first portion A1 is smaller than the maximum width of the second portion A2. In one embodiment, the maximum width of the first portion A1 is 60% to 75% of the maximum width of the second portion A2, so that the cross section of the deuterated metal layer 114 becomes a mushroom shape. The top end of the air gap 118 is higher than the top end of the stacked structure 108a. The air gap 118 has a wide portion 118a and a narrow portion 118b, the wide portion 118a being located below the narrow portion 118b, and the maximum width W11 of the wide portion 118a being greater than the maximum width W12 of the narrow portion 118b. In an embodiment, the maximum width W11 of the wide portion 118a is between the adjacent two stacked structures 108a and lower than the second portion A2 of the deuterated metal layer 114. The cross section of the air gap 118 can be a bowling pin shape.
請再次參照圖2F，根據本發明另一實施例之半導體元件包括基底200、多個堆疊結構208a、以及介電層224。相鄰兩個堆疊結構208a之間具有空氣間隙218。堆疊結構208a包括矽化金屬層214與硬罩幕層222，硬罩幕層222配置於矽化金屬層214上。矽化金屬層214具有第一部分B1與第二部分B2。第一部分B1位於第二部分B2之下，第一部分B1的最大寬度大於第二部分B2的最大寬度。在一實施例中，第二部分B2的最大寬度為第一部分B1的最大寬度的85%～90%，使矽化金屬層214的剖面成為倒T形。空氣間隙218的頂端高於堆疊結構208a的頂端。空氣間隙218具有一寬部218b、第一窄部218a與第二窄部218c。第一窄部218a位於第二窄部218c之下，寬部218b位於第一窄部218a與第二窄部218c之間。寬部218b的最大寬度W22大於第一窄部218a與第二窄部218c的最大寬度W21與W23。寬部218b的最大寬度W22位於相鄰兩個堆疊結構208a之間，並且低於硬罩幕層222，高於矽化金屬層214的第一部分B1。空氣間隙218的剖面可為飛碟形。Referring again to FIG. 2F, a semiconductor component in accordance with another embodiment of the present invention includes a substrate 200, a plurality of stacked structures 208a, and a dielectric layer 224. There is an air gap 218 between adjacent two stacked structures 208a. The stacked structure 208a includes a deuterated metal layer 214 and a hard mask layer 222, and the hard mask layer 222 is disposed on the deuterated metal layer 214. The deuterated metal layer 214 has a first portion B1 and a second portion B2. The first portion B1 is located below the second portion B2, and the maximum width of the first portion B1 is greater than the maximum width of the second portion B2. In one embodiment, the maximum width of the second portion B2 is 85% to 90% of the maximum width of the first portion B1, so that the cross section of the deuterated metal layer 214 is inverted T-shaped. The top end of the air gap 218 is higher than the top end of the stacked structure 208a. The air gap 218 has a wide portion 218b, a first narrow portion 218a and a second narrow portion 218c. The first narrow portion 218a is located below the second narrow portion 218c, and the wide portion 218b is located between the first narrow portion 218a and the second narrow portion 218c. The maximum width W22 of the wide portion 218b is greater than the maximum widths W21 and W23 of the first narrow portion 218a and the second narrow portion 218c. The maximum width W22 of the wide portion 218b is located between the adjacent two stacked structures 208a and is lower than the hard mask layer 222 than the first portion B1 of the vaporized metal layer 214. The cross section of the air gap 218 may be in the shape of a flying saucer.
以上的實施例中，是以非揮發性記憶元件來說明半導體元件。非揮發性記憶元件可以是快閃記憶體，或是電荷捕陷型記憶體。然而，本發明之半導體元件，並不以上述實施例為限。上述之半導體元件也可以是金氧半電晶體。金氧半電晶體可以是平坦型電晶體或是鰭狀電晶體。In the above embodiments, the semiconductor element is described as a non-volatile memory element. The non-volatile memory element can be a flash memory or a charge trap type memory. However, the semiconductor element of the present invention is not limited to the above embodiment. The above semiconductor element may also be a gold oxide semi-transistor. The gold oxide semi-transistor may be a flat type transistor or a fin-shaped transistor.
綜上所述，本發明提供的半導體元件及其製造方法，可在相鄰兩個閘極結構之間形成空氣間隙。由於所形成的空氣間隙之的頂端高於閘極結構頂面的高度，而且佔有相當大的體積，因此可有效地防止閘極結構之間的電容-電阻延遲，並改善各組成構件之間的電性干擾，充分提升半導體元件的效率。In summary, the semiconductor device and the method of manufacturing the same according to the present invention can form an air gap between adjacent two gate structures. Since the tip end of the formed air gap is higher than the height of the top surface of the gate structure and occupies a considerable volume, the capacitance-resistance delay between the gate structures can be effectively prevented, and the relationship between the constituent members can be improved. Electrical interference greatly improves the efficiency of semiconductor components.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100、200‧‧‧基底
101、201‧‧‧穿隧介電層
102、202‧‧‧電荷儲存層
104、104a、204、204a‧‧‧導體層
106、206‧‧‧層間介電層
108、108a、208、208a‧‧‧堆疊結構
110、210‧‧‧第一介電材料層
110a、110b、210a、210b‧‧‧第一介電層
112‧‧‧間隙壁材料層
112a‧‧‧間隙壁
114、214‧‧‧矽化金屬層
116、216‧‧‧第二介電層
118、218‧‧‧空氣間隙
118a、218b‧‧‧寬部
118b、218a、218c‧‧‧窄部
120、220‧‧‧空洞
222‧‧‧硬罩幕層
124、224‧‧‧介電層
A1、B1‧‧‧矽化金屬層的第一部分
A2、B2‧‧‧矽化金屬層的第二部分
W11、W12、W21、W22、W23‧‧‧寬度100, 200‧‧‧ base
101, 201‧‧‧ Tunneling dielectric layer
102, 202‧‧‧ charge storage layer
104, 104a, 204, 204a‧‧‧ conductor layer
106, 206‧‧‧ Interlayer dielectric layer
108, 108a, 208, 208a‧‧‧ stacked structure
110, 210‧‧‧ first dielectric material layer
110a, 110b, 210a, 210b‧‧‧ first dielectric layer
112‧‧‧ spacer material layer
112a‧‧‧ clearance
114, 214‧‧‧Deuterated metal layer
116, 216‧‧‧ second dielectric layer
118, 218‧‧‧ air gap
118a, 218b‧‧ Wide section
118b, 218a, 218c‧‧‧ narrow
120, 220‧‧‧ hollow
222‧‧‧ Hard mask layer
124, 224‧‧‧ dielectric layer
The first part of the A1, B1‧‧‧ deuterated metal layer
A2, B2‧‧‧ The second part of the deuterated metal layer
W11, W12, W21, W22, W23‧‧‧ width
圖1A至圖1H為根據本發明一實施例所繪示之半導體元件的製造流程剖面示意圖。 圖2A至圖2F為根據本發明另一實施例所繪示之半導體元件的製造流程剖面示意圖。1A-1H are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the invention. 2A-2F are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.
100‧‧‧基底 100‧‧‧Base
101‧‧‧穿隧介電層 101‧‧‧Tunnel dielectric layer
102‧‧‧電荷儲存層 102‧‧‧Charge storage layer
104a‧‧‧導體層 104a‧‧‧Conductor layer
106‧‧‧層間介電層 106‧‧‧Interlayer dielectric layer
108a‧‧‧堆疊結構 108a‧‧‧Stack structure
110b‧‧‧第一介電層 110b‧‧‧First dielectric layer
114‧‧‧矽化金屬層 114‧‧‧Deuterated metal layer
116‧‧‧第二介電層 116‧‧‧Second dielectric layer
118‧‧‧空氣間隙 118‧‧‧Air gap
118a‧‧‧寬部 118a‧‧ Wide section
118b‧‧‧窄部 118b‧‧‧narrow
120‧‧‧空洞 120‧‧‧ hollow
124‧‧‧介電層 124‧‧‧ dielectric layer
A1‧‧‧矽化金屬層的第一部分 The first part of the A1‧‧‧ chemicalized metal layer
A2‧‧‧矽化金屬層的第二部分 A2‧‧‧The second part of the eutectic metal layer
W11、W12‧‧‧寬度 W11, W12‧‧‧ width
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| TWI694571B (en) * | 2019-02-27 | 2020-05-21 | 旺宏電子股份有限公司 | Word line structure and method of manufacturing the same |
| US10892265B2 (en) | 2019-02-27 | 2021-01-12 | Macronix International Co., Ltd. | Word line structure and method of manufacturing the same |
| TWI717970B (en) * | 2020-01-14 | 2021-02-01 | 華邦電子股份有限公司 | Semiconductor structure and method for forming the same |
| US11101177B1 (en) | 2020-02-19 | 2021-08-24 | Winbond Electronics Corp. | Semiconductor structure and method for forming the same |
| TWI797467B (en) * | 2020-08-03 | 2023-04-01 | 華邦電子股份有限公司 | Non-volatile memory structure and method of manufacturing the same |
-
2014
- 2014-12-15 TW TW103143737A patent/TW201622063A/en unknown
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI694571B (en) * | 2019-02-27 | 2020-05-21 | 旺宏電子股份有限公司 | Word line structure and method of manufacturing the same |
| US10892265B2 (en) | 2019-02-27 | 2021-01-12 | Macronix International Co., Ltd. | Word line structure and method of manufacturing the same |
| TWI717970B (en) * | 2020-01-14 | 2021-02-01 | 華邦電子股份有限公司 | Semiconductor structure and method for forming the same |
| US11101177B1 (en) | 2020-02-19 | 2021-08-24 | Winbond Electronics Corp. | Semiconductor structure and method for forming the same |
| TWI797467B (en) * | 2020-08-03 | 2023-04-01 | 華邦電子股份有限公司 | Non-volatile memory structure and method of manufacturing the same |
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