4484 2 6 A7 B7 五、發明說明（1 ) 本發明係有關於一種用以於數位式儲存機器之時鐘信 號恢復裴置者。 依數位式儲存機器，為從再生信號高速抽出時鐘信號 ’而使用再生信號之前同步信號領域中所記錄之同步信號 。該同步信號係可與電壓控制振盪器（Voltage-Control Oscillator :以下簡稱VCO)之振盪頻率相對應者。VC0之 振盪頻率係藉控制電壓而可控制。作為時鐘信號恢復裝置 者，係為用以進行該VCO之振盪初期相位之控制者，而 使用一類比式零相位再開裝置。習知類比式零相位再開裝 置中，係使用有一類比式延遲元件。諸如將寫入於圓盤狀 之記錄媒想之資料’用以線性速度一定（Constant Linear Velocity :簡稱為CLV)控制之無振動模式再生時，其再生 信號之頻率幾乎成一定。又，因為頻率導致類比式延遲元 件之特性有不均之現象’難以將時鐘信號之振盪初期相位 控制在一安定之所需值》 以在一記錄媒體中使再生信號之頻率有大幅變化者為 例’寫入圓盤狀記錄媒體的資料也可用以角速度一定 (Constant Angular Velocity:以下簡稱為CAV)控制而再生 。此時’進行軌道搜尋時，使時鐘率在圓盤之内周與外周 頻繁變化。因此’對所處理之頻率的每個值都必須有事前 之學習’所以用以前述類比式零相位再開裝置之時鐘信號 恢復裝置難以充分發揮功能。 在此’即希望有一時鐘信號恢復裝置，係用以於再生 信號之頬率有變化時，不需事前學習，也可以所觀測之初 本紙張尺度逋用中國固家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁)4484 2 6 A7 B7 V. Description of the invention (1) The present invention relates to a clock recovery device for a digital storage machine. According to the digital storage device, in order to extract the clock signal from the reproduced signal at high speed, the synchronous signal recorded in the synchronous signal field before the reproduced signal is used. The synchronization signal can correspond to the oscillation frequency of a Voltage-Control Oscillator (hereinafter referred to as VCO). The oscillation frequency of VC0 is controlled by the control voltage. As a clock signal recovery device, an analog zero-phase reopening device is used to control the initial phase of the oscillation of the VCO. In the conventional analog zero-phase reopening device, an analog delay element is used. For example, when data written on a disc-shaped recording medium is reproduced in a vibration-free mode controlled by Constant Linear Velocity (CLV for short), the frequency of the reproduced signal becomes almost constant. In addition, because of the frequency, the characteristics of the analog delay element are not uniform. 'It is difficult to control the initial phase of the oscillation of the clock signal to a stable required value.' If the frequency of the reproduced signal is greatly changed in a recording medium, For example, the data written in the disc-shaped recording medium can be reproduced under constant angular velocity (Constant Angular Velocity: hereinafter referred to as CAV) control. At this time, when the track search is performed, the clock rate is frequently changed between the inner periphery and the outer periphery of the disc. Therefore, 'there must be prior learning for each value of the processed frequency', so it is difficult for the clock signal recovery device of the aforementioned analog zero-phase reopening device to fully function. Here, I hope that there is a clock signal recovery device, which is used when the rate of the reproduced signal changes, without the need to learn in advance, but can also observe the original paper size using the Chinese solid standard (CNS) A4 specification ( 210 X 297 public love) (Please read the notes on the back before filling this page)
經濟部智慧財產局員工消費合作社印製 4 經濟部智慧財產局員工消費合作社印f A7 ----------B7______ 五、發明說明（2 ) 期相位資訊為基準，進行一安定之振盪初期相位控制，而 施以相鎖迴路（Phase-Locked Loop :以下簡稱為PLL)之相 位與頻率之高速引進者。 第4圖係用以於數位式储存機器之習知時鐘信號恢復 裝置20之構成圖。頭部22係用以將寫入圓盤狀記錄媒體2 1 之資料讀出者。藉頭部22所讀出之再生信號係輸入於時鐘 信號恢復裝置20，施以初期的振盪相位控制。如同圖所示 ’由頭部22所輸出之再生信號係朝比長器23及相位比較器 27供給。比長器23係藉將再生信號與基準電壓比較，而可 轉換成零或零以外之數值，即2值化信號。脈衝生成電路24 係由所得到之2值化信號，用以生成可進行初期振盪相位 控制之脈衝信號。然後，延遲控制電路25係藉將脈衝信號 之輸出時機遲延而可調整者。 另一方面，為PLL構成元件之一的相位比較器27，係 用以檢測兩交流輸入信號之相位誤差者。在此，相位比較 器27係用以檢測由頭部22輸出之再生信號與由後述之 VC026所輸出之時鐘信號之相位差。同樣是Pll構成元件 之迴路濾波器28係藉積分一相位誤差信號：為相位比較器 27之輸出’而可對相位誤差信號進行帶域限制。在此所示 之迴路遽波器2 8係藉類比元件所構成，一般是使用低域通 過型之濾波器。為PLL之基本構成元件之vc〇26係用以使 因應迴路濾波器28輸出之相位誤差信號之數值之頻率的時 鐘信號振堡者。 通常’檢測朝相位比較器27供給之再生信號與vc〇26 未纸張反度適用中國國家標準（CNS)A4規格（21〇χ 297公釐） -———--I — — It I I I * 1 I I I ― I I . — I t I--I . ί請先閱讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作杜印製 4 c 3 A7 ---------- 五、發明說明（3 ) 輸出之時鐘信號間之相位誤差’將該相位誤差用以迴路渡 波器28積分而可向VC026回饋’藉此控制時鐘信號之頻 率與相位。由頭部22輸出之再生信號係由如第5A圊所示 之前同步信號領域以及資料領域讀出者。為了要進行從再 生信说西速抽出時鐘信號者，其主要關鍵在於：如何在前 同步信號領域中正確地檢測初期相位資訊，將該檢出之相 位資訊反映在時鐘信號控制者。具體而言，係藉下列方法 而進行PLL之高速引進。 在再生信號由前同步信號領域之同步信號變化成資料 領域之信號前’由比長器23將該再生信號切換成2值化信 號。為由比長器23將輸入信號分成2值時，必須提供一可 與該輸入信號相比較之基準水平（電壓）。作為在時鐘信號 恢復裝置中所使用之比長器23之基準水平，係選擇一近於 零之數值。尤其是經選擇一極端驅近於零之值作為一基準 水平’可正確將相位成為零之位置檢出。但是，基準水平 需用一不受DC變動之影響之程度之值。第5八圖之左側係 顯示比長器23所輸入之再生信號之前同步信號領域之波形 。又’第5B圖係顯示，使比長器23動作時，對應於基準 水平（示於第5A圖之臨界值ref)之輸出波形（2值化信號）。 示於第5B圖之比長器23之2值化信號係向第4圖之脈 衝生成電路24供給。脈衝生成電路24利用該2值化信號之 第1個上升’而可發生一如第5C圖所示之脈衝A。延遲控 制電路25將該脈衝A延緩一所定時間td，輸出一如第5D圖 所示之脈衝A’。該脈衝A，係可作為初期振盪相位控制用 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs f A7 ---------- B7______ V. Description of the Invention (2) Phase Information High-speed introducer of phase and frequency of phase control at the beginning of oscillation and phase-locked loop (hereinafter referred to as PLL). Fig. 4 is a block diagram of a conventional clock signal recovery device 20 used in a digital storage machine. The head 22 is a reader for reading data written on the disc-shaped recording medium 2 1. The reproduced signal read from the head 22 is input to the clock signal recovery device 20, and the initial oscillation phase control is performed. As shown in the figure, the reproduced signal outputted from the head 22 is supplied to the comparator 23 and the phase comparator 27. The comparator 23 can convert the reproduced signal to a reference voltage and convert it to a value other than zero, that is, a binary signal. The pulse generating circuit 24 is a binary signal obtained from the obtained binary signal, and is used to generate a pulse signal capable of controlling the initial oscillation phase. Then, the delay control circuit 25 can be adjusted by delaying the output timing of the pulse signal. On the other hand, a phase comparator 27, which is one of the components of the PLL, is used to detect a phase error between two AC input signals. Here, the phase comparator 27 is used to detect the phase difference between the reproduced signal output from the head 22 and the clock signal output from the VC026 described later. The loop filter 28, which is also a component of Pll, integrates a phase error signal: for the output of the phase comparator 27, the band error of the phase error signal can be limited. The loop wave filter 28 shown here is composed of analog components, and generally a low-pass filter is used. The vc26, which is the basic constituent element of the PLL, is used to vibrate the clock signal of the frequency corresponding to the value of the phase error signal output by the loop filter 28. Normally, the detection of the regeneration signal and vc〇26 supplied to the phase comparator 27 is in accordance with the Chinese National Standard (CNS) A4 specification (21〇χ 297 mm) -——--- I — — It III * 1 III ― II. — I t I--I. Ί Please read the notes on the back before filling out this page} Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Du Print 4 c 3 A7 --------- -V. Description of the invention (3) Phase error between the output clock signals 'Use this phase error to integrate the loop waver 28 and feedback to VC026' to control the frequency and phase of the clock signal. The reproduced signal output from the head 22 is read by the preamble area and the data area as shown in Section 5A 圊. In order to carry out the process of extracting the clock signal from the regeneration signal at the western speed, the main key lies in how to correctly detect the initial phase information in the preamble field and reflect the detected phase information to the clock signal controller. Specifically, the high-speed introduction of PLL is performed by the following method. Before the reproduction signal is changed from the synchronization signal in the preamble signal field to the signal in the data field, the reproduction signal is switched to a binary signal by the comparator 23. In order to divide the input signal into two values by the comparator 23, it is necessary to provide a reference level (voltage) which can be compared with the input signal. As a reference level of the proportionalizer 23 used in the clock signal recovery device, a value close to zero is selected. In particular, by selecting an extreme drive value close to zero as a reference level ', the position where the phase becomes zero can be accurately detected. However, the reference level needs to be a value that is not affected by DC fluctuations. The left side of Fig. 58 shows the waveform of the synchronous signal field before the reproduction signal input from the comparator 23. Fig. 5B shows the output waveform (binarized signal) corresponding to the reference level (critical value ref shown in Fig. 5A) when the comparator 23 is operated. The binarized signal of the proportionalizer 23 shown in Fig. 5B is supplied to the pulse generating circuit 24 in Fig. 4. The pulse generating circuit 24 can generate a pulse A as shown in Fig. 5C by using the first rise of the binary signal. The delay control circuit 25 delays the pulse A for a predetermined time td, and outputs a pulse A 'as shown in Fig. 5D. The pulse A can be used for the initial oscillation phase control. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm).
It — — — — I — It I J - — — III — — · I-------' \ <請先閱讀背面之注意事項再填寫本頁) A7 A7 五、發明說明（4 ) B7________ 之控制脈衝而供於VC026，用以於VC026之初期振盈之It — — — — — I — It IJ-— — III — — · I ------- '\ < Please read the notes on the back before filling this page) A7 A7 V. Description of the invention (4) B7________ The control pulse is provided to VC026, which is used to vibrate in the early stage of VC026.
相位控制者。VC026之振盪初期相位控制意指，如第5E 圖所示，在脈衝A‘之上升期間中，將VC026之振盪停止 後’等脈衝A·下降後，再開始VC026之振盪者。依此控 制的話，可用以在再生信號之前同步信號領域高速鎖定 PLL。 如果只是CLV再生時，由頭部22送出之再生信號之頻 率幾乎沒有變化。在該條件下’在PLL之高速引進面而言 ，前述方法可說是一有效的手法。但是，利用一作為數位 式储存機器的代表之圓盤狀記錄媒體丨者，藉由軌道向轨 道之移動（搜尋及探測等），可使再生信號之頻率大幅變化 。又在C A V再生中，如前述，也有可能使時鐘率頻繁 變化。在該情形下，使用如第4圖所示之類比式相位再開 裝置作為一時鐘信號恢復裝置時，因其再生信號之頻率大 幅變化，導致該功能難以充分發揮。 如此，在再生信號之頻率大幅變化之系統，或再生信 號之頻率頻繁變化之系統中會衍生下列問題，即，使用類 比式零相位再開裝置作為一時鐘信號恢復裝置時，只能針 對某限定頻率，進行一安定的vc〇之初期振盪相位控制 者。 有鑑於習知問題點，本發明之目的在於實現一種時鐘 仏號恢復裝置’即使在再生信號之頻率大幅變化之系統， 或再生信號之頻率頻繁變化之系统中，與類比式零相位再 開裝置相比較，可正確進行初期的振盪相位控制，並可安 裝--------訂---------線 (請先閉讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張反度適用中國國家標準(CNS)A4 規格（210 x 297公釐） 44 84 經濟部智慧財產局員工消费合作社印製 A7 B7 五、發明說明（5 ) 定且高速施行對PLL以及頻率之引進動作。 為解決如此問題，本發明係一種時鐘信號恢復裝置， 係用以將寫入記錄媒體之信號藉頭部之掃描再生，由再生 信號中所含之同步信號生成一用以恢復資料的信號之時鐘 信號者’其特徵在於包含有： a) —電禮控制振盪器，係藉以控制電壓而控制振盪頻 率’同時生成一基準相位以及一與該基準相位之相位相異 之時鐘信號者； b) —類比/數位轉換器，係使透過前述頭部所讀出之 再生信號’用以前述時鐘信號而可轉換成數位式再生信號 者； c) 广初期相位檢測器’係用以檢測一由前述類比/數 位轉換器輸出之再生信號，與前述電壓控制振盪器輸出之 基準相位之時鐘信號間之初期相位誤差者； d) —數位式相位切換器，係用以使前述初期相位誤差 為最小之狀態，選擇前述電壓控制振盪器之時鐘信號相位 ，將一特定相位之時鐘信號作為樣本信號而可供給前述類 比/數位轉換器者； e) —數位式相位比較器，係用以檢測由前述類比/數 位轉換益輸出之再生信號，與前述數位式相位切換器輸出 之時鐘信號之相位差，將檢測結果作為相位誤差信號而可 輪出者；及 f) 一迴路濾波器，係用以對數位式相位比較器輪出之 相位誤差信號進行帶域限制， 本紙張尺度適用中0國家標準<CNS)A4規格<2ϊ0 X 297公爱〉 ------1-----:裝---1---- 訂---------線 r ^ (請先閲讀背面之注意事項再填寫本頁) 8 A7 B7 經 濟 部 智 慧 財 產 局 I 工 消 費 合 作 社 印 五、發明說明（6 ) g) —數位/類比轉換器，係用以將迴路濾波器之輸出 轉換成類比式，作為一控制電壓而向前述電壓控制振盪器 供給者。 圖式簡單說明 第1圖係顯示本發明之實施形態之時鐘信號恢復裝置 之構成之塊圖。 第2 A圖係用以於本實施形態之時鐘信號恢復裝置中 之VCO的構成圖。 第2B圖係用以於本實施形態之時鐘信號恢復裝置中 ’且為VCO之構成元件之延遲元件之電路圖。 第3圖係本實施態樣之VCO之振盪波形圖。 第4圖係顯示習知時鐘信號恢復裝置之構成之塊圖。 第5A圖係習知時鐘信號恢復裝置中，由記錄媒體讀 出之再生信號之波形圖。 第5B圖係習知時鐘信號恢復裝置中，藉使再生^號 之前同步信號領域之信號通過比長器而可得到之波形圖。 第5C圖係習知時鐘信號恢復裝置中，脈衝生成電路 之輸出波形圖。 第5D圖係習知時鐘信號恢復裝置中，延遲控制電路 之輸出波形圖。 圖係習知時鐘信號恢復裝置中’進行初期振盪相 位控制時之VCO的振盪波形圖。 元件標號對照 1 ' 21…記錄媒體 本紙張尺度適用中國國家標準（CKS)A4規格（210 * 297公釐 -------------裝！----訂--------線 f請先閱讀背面之注意事項再填寫本頁> 44 44 經濟部智慧財產局員工消費合作杜印製 A7 _______ B7 五、發明說明（7 ) 2、22…頭部 3…ADC(類比/數位轉換器） 4…初期相位檢測器 5…數位式相位轉換器 6、26…VCO(電壓控制裝置） 7…數位式相位比較器 8、28…迴路濾波器 9…DAC(數位/類比轉換器） 11、12…電晶體 13…電壓控制定電流源 14…電容器 20·-"時鐘信號恢復裝置 24…脈衝生成電路 25…延遲控制電路 27…相位比較器 D、D1〜D7···延遲元件 P1〜P4…輸出端 用以實施本發明之最佳態樣 針對本發明之實施形態之時鐘信號恢復裝置，用以第 1圖至第3圖作說明。第1圖係顯示本發明之實施形態之時 鐘信號恢復裝置之構成之塊圖。記錄媒體1係一記錄有數 位式資料之圓盤狀記錄媒艘，係以扇形單位記錄有如第5 a 囷所示之形式的信號。頭部2係用以將寫入記錄媒艘1之信 號讀出者。由頭部2讀出之再生信號係向類比/數位轉換器 本紙張尺度適用中國國家標準（CNS)A4規格(210 X 297公釐） ---111----:裝！—訂------線 ^ <請先閲讀背面之注意事項再填寫本頁) 10 經濟部智慧財產局員工消費合作社印f A7 ---—____B7___ 五、發明說明（8 ) (以下稱為ADC)3供給。ADC3係用以由數位式相位切換器 5輸出之時鐘信號，將再生信號樣本化，轉換成數位式信 號者。由ADC3輸出之數位式再生信號係提供給初期相位 檢測器4及數位式相位比較器7。 初期相位檢測器4係用以，在頭部2進入前同步信號領 域時’將藉ADC3轉換之數位式再生信號之初期相位檢出 ’可保持該值的狀態者。數位式相位切換器5係以經初期 相位檢測器4檢測之初期相位為基準，藉選擇器而將電壓 控制振盪器（以下稱為VC0)6中之振盪相位變換者。VC06 係用以因應由數位/類比轉換器（以下稱為DAC)輸出之類 比式相位誤差信號，而可發生一時鐘信號之電路。 VC06之構成例示於第2圖。VC06係一具有如第2A圖 之構成之環狀振盪器，係用以η(奇數>個延遲元件D環狀直 列連接者β在此，使用7個延遲元件D1、D2、D3、D4、D5 、D6、D7 ’將延遲元件Dl ' D3、D5、D7之輸出端各設 為Ρ1、Ρ2、Ρ3、Ρ4，而將各輸出端之信號朝數位式相位 切換器5輸出。 第2Β圖係延遲元件D之構成圖。如本圖所示，延遲元 件D，其構成包含有：兩相補連接之MOS電晶體11、 12(CM0S驅動器）、一用以向電晶體11之排流供給電流之 電壓控制定電流源13、及一與CMOS驅動器以及地線相連 接之電容器14。電壓控制定電流源13係用以如第1圖之 DAC9輸出之類比式相位誤差信號為基準，向電晶體π、12 供給排流電流者。延遲元伴D之信號延遲時間r係藉電容 本纽、張尺度適用中國固家標準（CNSM4規格（210 X 297公釐） -------------裝--------訂---------線 <請先閱讀背面之注意事項再填寫本頁) 11 4 4 五 經濟部智慧財產局員工消費合作社印製 A7 發明說明（9 ) 器之充電時間而可控制者。因此，VC06之振盪頻率係藉 延遲疋件η與DAC9之輸出電壓而可決定。根據該構成， DAC9之輪出電壓為—定時，藉使選擇輸出端Ρ1至Ρ4中任 一輪出，可將_具所望相位之時鐘信號取出β 第1圖之數位式相位比較器7係檢測數位式再生信號之 基準點與由數位相位切換器5輸出之時鐘信號之相位差， 而可生成一數位式相位誤差信號者，迴路濾波器8係用以 對數位式相位誤差信號進行帶域限制者，係由相加器、相 乘器、選擇器等構成。數位/類比轉換器（DAC)9s用以將 迴路濾波器8輸出之數位式相位誤差信號轉換成一類比式 相位誤差信號者。如此，PLL係用以類比式控制之VCC)6 而可數位式構成。 又，雖未示於第丨囷，由數位式相位切換器5輸出之時 鐘信號不只供給ADC3，還供給初期相位檢測器4、數位 式相位比較器7、迴路濾波器8及DAC9。 其次，針對可向再生信號進行高速抽取時鐘信號時之 時鐘信號恢復裝置的動作作說明。在記錄媒體丨針對頭部2 發出搜尋及探測等命令，以及在PLL之鎖定完全解除時’ 可使初期相位檢測器4、數位式相位切換器5及數位式相位 比較器7之動作停止。此時，使v〇(：6之振㈣率可自動 變化成初期值至某一值間者，當該振盪頻率接近於再生信 號中所包含之時鐘信號之頻率時，可使初期相位檢測器4 、數位式相位切換器5及數位式相位比較器7開始動作。 在該狀態下，頭部2進入前同步信號領域時’不只 本紙張尺度適用中國國家標準(CNS)A4规格<210X 297公爱） <請先閱績背面之注意事項再填寫本頁) 衷--------訂---------線： 12 經濟部智慧財產局員工消費合作社印製 A7 __B7 五、發明說明（i〇 ) 正確進行初期相位誤差之檢測’還可保持該檢出之初期相 位误差資訊’用以該初期相位誤差資訊，可要求快速回饋 到VC06之振盪動作。為實現該機能，藉初期相位檢測器 4所檢出之初期相位誤差資訊向數位式相位切換器5傳遞後 ，進行以下之處理。 在示於第2A圖之環狀振盪器形式之VC06中，係令具 原有之基準相位之振盪輸出（時鐘信號）可由輸出端P4輸出 者。此時’將振盪周期（時鐘信號）設定為T時，針對基準 相位，可從輸出端P卜P2、P3得到每㈨⑻丁㈦為！或2)相 位相異之振盪輸出。如此，將輸出端P1~P4所得到之振盘 輸出之波形示於第3圖。而在數位式相位切換器5，係因應 由初期相位檢測器4檢出且力π.以保持之初期相位誤差資訊 ’可在VC06之多數相位相異之時鐘信號中，選擇一最靠 近初期相位誤差為〇之時鐘信號。藉此，可立即使用反映 出初期相位誤差之檢測結果之時鐘信號。 其次’數位式相位比較器7係可檢測數位式再生信號 之基準點與數位式相位切換器5所輸出之時鐘信號之相位 差’而生成數位式相位誤差信號。隨後將該相位誤差信號 透過迴路濾波器8與DAC9而供於VC06，可控制VC06之 振盈頻率’使之可與再生時鐘信號之頻率始終一致。 又’增加環形振盪器形式之VC〇6之構成元件數：諸 如延遲元件D之段數時，可高精度施行一由再生信號進行 抽出時鐘信號時之相位與頻率之引進者。 產業上之可利用性 本紙張又度適用中國國家標準（Ci\rS)A4規格（210 X 297公釐 I. 裝---II 訂 ----I---* 線 (請先閱讀背面之注意事項再填窝本頁) 13 Λ 4 Α7 _ Β7 五、發明說明（11 ) 依本發明，在再生信號之頻率有大幅變化之系統，或 再生化號之頻率頻繁變化之系統中，也可以再生信號之前 同步信號領域中所接收到之初期相位誤差資訊為基準，正 確且敏捷地設定時鐘信號之相位。因此，使PLL之相位以 及頻率之引進幾乎不會受到再生信號之頻率變動的影響， 而可高速進行者。 (請先閲讀背面之注意事項再填寫本I) 經濟部智慧財產局員工消費合作社印製 14 本紙張尺度適用中國國家標準（CNS)A4规格<210 X 297公釐）Phase controller. The initial phase control of the VC026 means that, as shown in Fig. 5E, during the rising period of the pulse A ', the VC026's oscillation is stopped' and the pulse A · 'is lowered before the oscillation of the VC026 is started. With this control, it can be used to lock the PLL at high speed in the synchronous signal field before regenerating the signal. In the case of CLV reproduction only, the frequency of the reproduction signal sent from the head 22 hardly changes. Under these conditions, the aforementioned method can be said to be an effective method in terms of the high-speed introduction of PLL. However, by using a disc-shaped recording medium as a representative of a digital storage device, the frequency of the reproduced signal can be greatly changed by moving from track to track (searching and detecting, etc.). In the CAV reproduction, as described above, it is possible to frequently change the clock rate. In this case, when the analog phase re-opening device shown in Fig. 4 is used as a clock signal recovery device, the frequency of the reproduced signal changes greatly, which makes it difficult to fully perform this function. In this way, in a system where the frequency of the regenerative signal changes greatly, or a system where the frequency of the regenerative signal changes frequently, the following problem arises: when using an analog zero-phase reopening device as a clock signal recovery device, it can only target a certain frequency , For a stable initial phase controller of vc0. In view of the conventional problems, the purpose of the present invention is to realize a clock signal recovery device 'even in a system where the frequency of the regenerative signal changes significantly, or in a system where the frequency of the regenerative signal changes frequently, it is similar to the analog zero-phase reopening device. For comparison, the initial oscillation phase control can be performed correctly and can be installed -------- order --------- line (please close the precautions on the back before filling this page) Ministry of Economic Affairs wisdom Printed by the Consumer Property Cooperative of the Bureau of Property, the paper is reversely applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 44 84 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed A7 B7 V. Description of the invention (5) High-speed implementation of PLL and frequency introduction. In order to solve such a problem, the present invention is a clock signal recovery device for regenerating a signal written in a recording medium by scanning the head, and generating a clock for recovering data from a synchronization signal contained in the reproduced signal. The signaler 'is characterized by including: a)-an electronically controlled oscillator that controls the oscillation frequency by controlling the voltage' while generating a reference phase and a clock signal having a phase different from the reference phase; b)- The analog / digital converter is used to make the reproduced signal read through the head 'convertible to a digital reproduced signal using the aforementioned clock signal; c) a wide-phase detector' is used to detect an analog by the aforementioned analog The initial phase error between the regenerative signal output from the digital converter and the clock signal of the reference phase output from the voltage-controlled oscillator; d)-a digital phase switcher used to minimize the initial phase error , Select the phase of the clock signal of the aforementioned voltage-controlled oscillator, and use a clock signal of a specific phase as a sample signal to be supplied before Analog / digital converter; e) — digital phase comparator, used to detect the phase difference between the regenerated signal output by the analog / digital conversion gain and the clock signal output by the digital phase switcher, and the detection result will be Can be rotated out as a phase error signal; and f) a loop filter is used to limit the band error of the phase error signal output by the digital phase comparator. The national standard of this paper applies to the national standard < CNS) A4 specifications < 2ϊ0 X 297 public love> ------ 1 -----: installed --- 1 ---- order --------- line r ^ (Please read the back first Note: Please fill in this page again) 8 A7 B7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs I Industrial and Commercial Cooperatives 5. Description of the invention (6) g)-Digital / analog converter, which is used to convert the output of the loop filter to analog To the aforementioned voltage controlled oscillator supplier as a control voltage. Brief Description of Drawings Fig. 1 is a block diagram showing the structure of a clock signal recovery device according to an embodiment of the present invention. Fig. 2A is a configuration diagram of a VCO used in the clock signal recovery device of this embodiment. Fig. 2B is a circuit diagram of a delay element used as a constituent element of the VCO in the clock signal recovery device of this embodiment. Fig. 3 is an oscillation waveform diagram of the VCO in this embodiment. Fig. 4 is a block diagram showing the structure of a conventional clock signal recovery device. Fig. 5A is a waveform diagram of a reproduced signal read from a recording medium in a conventional clock signal recovery device. FIG. 5B is a waveform diagram of a conventional clock signal recovery device, which can be obtained by regenerating a signal in the pre-sync signal field through a comparator. Fig. 5C is an output waveform diagram of a pulse generating circuit in a conventional clock signal recovery device. Fig. 5D is an output waveform diagram of the delay control circuit in the conventional clock signal recovery device. The figure shows the waveform of the VCO oscillation in the conventional clock signal recovery device when the initial oscillation phase control is performed. Component label comparison 1 '21 ... Recording medium This paper size is applicable to the Chinese National Standard (CKS) A4 specification (210 * 297 mm ------------ installed! ---- ordered --- ----- Line f, please read the notes on the back before filling in this page> 44 44 Consumer Cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs Du printed A7 _______ B7 V. Invention Description (7) 2, 22 ... Head 3 … ADC (analog / digital converter) 4… initial phase detector 5… digital phase converter 6,26… VCO (voltage control device) 7… digital phase comparator 8, 28… loop filter 9… DAC ( Digital / analog converter) 11, 12 ... Transistor 13 ... Voltage controlled constant current source 14 ... Capacitor 20 ... Clock clock recovery device 24 ... Pulse generation circuit 25 ... Delay control circuit 27 ... Phase comparators D, D1 ~ D7 ... The delay elements P1 ~ P4 ... The output terminals are used to implement the best mode of the present invention. The clock signal recovery device according to the embodiment of the present invention is described with reference to Figs. 1 to 3. Fig. 1 is Block diagram showing the configuration of a clock signal recovery device according to an embodiment of the present invention. The recording medium 1 is a record The disc-shaped recording medium vessel of digital data is recorded in a fan-shaped unit as shown in Section 5a. The head 2 is used to read the signal written in the recording medium vessel 1. From the head 2 The read-out reproduced signal is to an analog / digital converter. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --- 111 ----: installed! -Order ----- -Line ^ < Please read the notes on the back before filling out this page) 10 Printed by the Intellectual Property Bureau Employees Consumer Cooperatives of the Ministry of Economic Affairs f A7 ---______ B7___ V. Description of the Invention (8) (hereinafter referred to as ADC) 3 Supply. ADC3 is a clock signal output from the digital phase switcher 5 to sample the regenerated signal and convert it into a digital signal. The digital reproduction signal output from the ADC 3 is supplied to the initial phase detector 4 and the digital phase comparator 7. The initial phase detector 4 is used to detect the initial phase of the digital reproduction signal converted by the ADC3 when the head 2 enters the preamble area, and the state can maintain the value. The digital phase switcher 5 converts the oscillating phase in the voltage controlled oscillator (hereinafter referred to as VC0) 6 based on the initial phase detected by the initial phase detector 4 as a reference. VC06 is a circuit that can generate a clock signal in response to an analog phase error signal output by a digital / analog converter (hereinafter referred to as a DAC). An example of the structure of VC06 is shown in FIG. 2. VC06 is a ring oscillator with the structure as shown in Fig. 2A. It is connected with η (odd number> delay elements D ring in-line connected β here, using 7 delay elements D1, D2, D3, D4, D5, D6, D7 'Set the output terminals of the delay elements D1' D3, D5, D7 to P1, P2, P3, and P4, respectively, and output the signals of each output terminal to the digital phase switcher 5. Figure 2B Structure diagram of the delay element D. As shown in this figure, the structure of the delay element D includes: two MOS transistors 11, 12 (CM0S drivers) connected in a complementary manner, and a circuit for supplying current to the drain of the transistor 11. Voltage-controlled constant-current source 13 and a capacitor 14 connected to the CMOS driver and ground. The voltage-controlled constant-current source 13 is based on the analog phase error signal output by DAC9 as shown in Figure 1 to the transistor π , 12, who supply the drain current. The delay time r of the signal of the delay element companion D is based on the capacitance of the capacitor, and the scale is applicable to the Chinese solid standard (CNSM4 specification (210 X 297 mm) ---------- --- install -------- order --------- line < please read the notes on the back before filling this page) 11 4 4 5 The Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed A7 Invention Note (9) The charging time of the device can be controlled. Therefore, the oscillation frequency of VC06 can be determined by the delay element η and the output voltage of DAC9. According to this structure, The output voltage of DAC9 is-timing. If any one of the output terminals P1 to P4 is selected, the clock signal with the desired phase can be taken out. Β The digital phase comparator 7 in Figure 1 detects the digital regeneration signal. The phase difference between the reference point and the clock signal output by the digital phase switcher 5 can generate a digital phase error signal. The loop filter 8 is used to limit the digital phase error signal with a band. Adder, multiplier, selector, etc. The digital / analog converter (DAC) 9s is used to convert the digital phase error signal output by the loop filter 8 into an analog phase error signal. Thus, the PLL is used to Analog control VCC) 6 can be constructed digitally. Although not shown in the figure, the clock signal output from the digital phase switcher 5 is not only supplied to the ADC 3, but also to the initial phase detector 4, the digital phase comparator 7, the loop filter 8, and the DAC9. Next, the operation of the clock signal recovery device when a clock signal can be extracted from the reproduced signal at high speed will be described. Commands such as search and detection for the head 2 are issued on the recording medium, and when the PLL lock is completely released, the operations of the initial phase detector 4, the digital phase switcher 5, and the digital phase comparator 7 can be stopped. At this time, the vibration rate of v0 (: 6 can be automatically changed from the initial value to a certain value. When the oscillation frequency is close to the frequency of the clock signal included in the reproduction signal, the initial phase detector can be made. 4. The digital phase switcher 5 and digital phase comparator 7 start to operate. In this state, when the head 2 enters the preamble field, not only the paper size applies the Chinese National Standard (CNS) A4 specification < 210X 297 (Public Love) < Please read the notes on the back of the record before filling out this page) Sincerely -------- Order --------- Line: 12 Printed by the Consumers ’Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs A7 __B7 V. Description of the invention (i〇) Correctly detect the initial phase error 'can also maintain the detected initial phase error information' For this initial phase error information, you can request fast feedback to the VC06's oscillation action. In order to realize this function, after the initial phase error information detected by the initial phase detector 4 is transmitted to the digital phase switcher 5, the following processing is performed. In the VC06 in the form of a ring oscillator shown in Fig. 2A, the oscillation output (clock signal) with the original reference phase can be output by the output terminal P4. At this time, when the oscillation period (clock signal) is set to T, the reference phase can be obtained from the output terminals P2, P2, and P3! Or 2) Oscillation output with different phases. In this way, the waveforms of the vibrating plate outputs obtained from the output terminals P1 to P4 are shown in FIG. 3. In the digital phase switcher 5, it is detected by the initial phase detector 4 and has a force of π. To maintain the initial phase error information, 'the majority of VC06 clock signals with different phases can be selected to be closest to the initial phase. Clock signal with an error of 0. Thereby, the clock signal reflecting the detection result of the initial phase error can be used immediately. Secondly, the 'digital phase comparator 7 can detect the phase difference between the reference point of the digital reproduction signal and the clock signal output from the digital phase switcher 5' to generate a digital phase error signal. This phase error signal is then supplied to VC06 through the loop filter 8 and DAC9, and the oscillating frequency of VC06 can be controlled so that it is always consistent with the frequency of the regenerated clock signal. In addition, the number of components of VC06 in the form of a ring oscillator is increased: for example, when the number of segments of the delay element D is high, an introducer that can extract the phase and frequency of the clock signal from the reproduced signal with high accuracy. Industrial availability This paper is again suitable for the Chinese National Standard (Ci \ rS) A4 specification (210 X 297 mm I. Packing --- II order-I --- * line (please read the back first Note for refilling this page) 13 Λ 4 Α7 _ B7 V. Description of the invention (11) According to the present invention, in a system where the frequency of the reproduction signal changes significantly, or in a system where the frequency of the reproduction number frequently changes, The initial phase error information received in the pre-synchronous signal field of the reproduced signal can be used as a reference to set the phase of the clock signal accurately and quickly. Therefore, the introduction of the phase and frequency of the PLL is hardly affected by the frequency variation of the reproduced signal. (Please read the notes on the back before filling in this I) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 14 This paper size is applicable to China National Standard (CNS) A4 specifications < 210 X 297 mm )