CN1277720A - Clock recovery device - Google Patents

Clock recovery device Download PDF

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Publication number
CN1277720A
CN1277720A CN99801575A CN99801575A CN1277720A CN 1277720 A CN1277720 A CN 1277720A CN 99801575 A CN99801575 A CN 99801575A CN 99801575 A CN99801575 A CN 99801575A CN 1277720 A CN1277720 A CN 1277720A
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CN
China
Prior art keywords
phase
signal
clock
digital
output
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Pending
Application number
CN99801575A
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Chinese (zh)
Inventor
佐藤慎一郎
丸川昭二
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Publication of CN1277720A publication Critical patent/CN1277720A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
    • G11B20/1024—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation wherein a phase-locked loop [PLL] is used
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10305—Improvement or modification of read or write signals signal quality assessment
    • G11B20/10398—Improvement or modification of read or write signals signal quality assessment jitter, timing deviations or phase and frequency errors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

Data written in a recording medium (1) are reproduced by a head (2) and converted into a digital signal by an ADC (3). An initial phase detector (4) detects the initial phase of the signal and holds it. A VCO (6) is composed in the form of a ring oscillator, whose oscillation frequency is controlled by phase error signals, with its phase selectable. The restart oscillation phase of the VCO (6) is switched on the basis of the initial phase error information. When the scanning speed of the head (2) changes, a digital phase comparator (7) compares reproduced signals with the phase of the clock signal from the VCO (6), and the control voltage of the VCO (6) is varied depending on the phase error.

Description

Clock recovery device
Invention field
The present invention relates to be used for the clock recovery device of digital memory device.
Background of invention
Digital memory device is utilized the synchronizing signal of storage in replay signal preamble zone (preamble area) in order to extract time clock from the replay signal high speed.This synchronizing signal is corresponding to the voltage-controlled oscillator oscillation frequency of (after this being called for short ' VCO ').The oscillation frequency of this VCO is by the control Control of Voltage.In order to control the initial phase of VCO vibration, adopt the analogue zero phase place to restart device as clock recovery device, the analogue zero phase place restarts device and adopts the simulation time-delay element in the prior art.For example, adopt constant linear speed control (after this abbreviating ' CLV control ' as) that the data that write down in the discoid recording medium are reset under the non-jitter pattern, it is constant that the frequency of replay signal generally becomes.In addition, because the inherent dispersing characteristic that the simulation time-delay element has the frequency of depending on, so be difficult to the stable expectation value that is controlled at of the initial phase of clock oscillation signal.
A kind of situation is to adopt constant linear angular velocity control (after this being called for short ' CAV the control ') data of playback of recorded in discoid recording medium, the very big situation of frequency change of replay data in for example single recording medium.When carrying out tracking in this case, clock rate is frequent variations between the inner track of disc and outer track.Therefore, the clock recovery device that adopts the analogue zero phase place to restart device is difficult to make full use of its function, because it all needs to learn in advance to handled each frequency values.
Correspondingly, when the replay signal frequency shift, need a kind of clock recovery device that can stable regulation oscillator signal initial phase on the basis of initial phase observation information, thereby realize the phase place of phaselocked loop (after this being called for short ' PLL ') and frequency to introduce synchronously fast and learning process in advance.
Fig. 4 is for being used in the block scheme of the clock recovery device 20 in the digital memory device in the prior art.22 read the data of record in the discoid recording medium 21.Be input in the clock recovery device 20 by 22 replay signal that read, and accept initial oscillation phase control.More specifically, the replay signal of 22 output enters comparer 23 and phase comparator 27.Thereby comparer 23 converts replay signal and reference voltage comparison to replay signal to the binary signal of null value or nonzero value.Pulse-generator circuit 24 produces the vibration initial phase that pulse signal is used to control its resulting binary signal.Delay control circuit 25 is adjusted the time limit with the time-delay output pulse signal subsequently.
On the other hand, as the phase differential between two A.C input signals of phase comparator 27 detections of PLL element.Wherein, the phase differential between the replay signal of phase comparator 27 detection heads 22 outputs and the clock of VCO 26 outputs, this will be explained below.The same phase signal integration of exporting as 28 pairs of phase comparators of loop filter 27 of PLL element is to limit the frequency band of phase signal.Loop filter shown here 28 is made up of analog element, adopts low-pass filter usually.Produce the running clock of corresponding frequencies as the phase signal value of corresponding loop filters 28 outputs of VCO 26 of PLL basic composition element.
Usually, enter the phase differential between the clock of the replay signal of phase comparator 27 and VCO 26 outputs by detection, clock recovery device is controlled the frequency and the phase place of clock, will feed back to VCO 26 behind the phase differential integration then in loop filter 28.Shown in Fig. 5 A, the replay signal of 22 output is exactly the signal of reading from preamble area and data field.The high speed of clock signal is extracted the degree of accuracy that only depends on detected initial phase information from preamble area in the replay signal, and simultaneously, the phase information of returning detection is used to control clock.More particularly, the high-speed synchronous of PLL is introduced and is carried out in the following manner.
Before the synchronizing signal of replay signal from preamble area became signal in the data field, comparer 23 usefulness binary signals replaced above-mentioned replay signal.In order to make comparer 23 that input signal is converted to binary mode, need provide a datum (voltage) and compare with input signal.Select one near the datum of zero value as comparer in the clock recovery device 23.But the numerical value of datum must not be subjected to the DC influence of fluctuations.Fig. 5 A left side one side of something is the preamble area waveform of the replay signal of input comparator 23.Further, Fig. 5 B is depicted as the output waveform (binary signal) when comparer 23 is worked on the basis of datum (threshold value shown in Fig. 5 A ' ref ').
The binary signal of the comparer 23 as shown in Fig. 5 B enters pulse-generator circuit 24 as shown in Figure 4.Pulse-generator circuit 24 adopts the pulse A of first rising edge generation shown in Fig. 5 C of this binary signal.Delay control circuit 25 is with the pulse A ' shown in the output map 5D of the lucky delay predetermined time of pulse A ' td ' back.This pulse A ' enters VCO 26 as gating pulse and is used for initial oscillation phase control, is used for the VCO phase control of 26 vibration starting stages simultaneously.VCO 26 vibration starting stage phase control represent that VCO 6 suspends vibration duration of pulse A ', and restart vibration after pulse A ' descends, shown in Fig. 5 E.Above-mentioned control mode can lock PLL at a high speed in the replay signal preamble area.
If only adopt CLV to reset, from the beginning the frequency of 22 replay signal that forward is almost constant.Under this condition, said method can be regarded the effective means that the PLL high speed is introduced synchronously as.Yet in using the Typical Digital memory device of discoid recording medium 1, the frequency change of replay signal is very big when moving (tracking, search etc.) to another magnetic track from a magnetic track.In addition, as mentioned above, in the CAV playback procedure, exist clock rate to change frequent phenomenon.In the case, because replay signal alters a great deal, the analogue zero phase place restarts device will be difficult to make full use of this device as clock recovery device function shown in Fig. 4 if adopt.
Correspondingly, if being restarted device, this analogue zero phase place is used for the system that replay signal alters a great deal or the replay signal variation is frequent as clock recovery device, unless the problem that exists is for the limited frequency range of determining, otherwise this device can not provide stable phase control in the VCO vibration starting stage.
Summary of the invention
The present invention proposes in view of the above-mentioned problems in the prior art.Restarting device with the analogue zero phase place compares, target of the present invention is to realize a kind of clock recovery device, even make in the system that replay signal alters a great deal or the replay signal frequency change is frequent, also can carry out precise phase control, and phase place and the frequency stabilization of PLL are introduced at high speed synchronously in the vibration starting stage.
In order to realize above-mentioned target, the invention relates to the clock recovery device that utilizes head to scan the signal of playback of recorded in recording medium.Clocking is used for carrying out data decode from the synchronizing signal that replay signal comprises simultaneously.This device characteristic is to have:
A) voltage-controlled oscillator, its oscillation frequency are used for producing simultaneously the clock of fixed phase clock and another out of phase by the control Control of Voltage;
B) replay signal of utilizing above-mentioned clock that head is read converts the analogue-to-digital converters of digital replaying signal to;
C) be used to detect the initial phase detecting device of initial phase difference between the fixed phase clock signal of the replay signal of analogue-to-digital converters output and voltage-controlled oscillator output;
D), and the clock signal of particular phases is offered the digital phase shifter of analogue-to-digital converters as sampled signal so that the mode of initial phase difference minimum is selected the voltage-controlled oscillator clock phase;
E) be used to detect phase differential between the clock of the replay signal of analogue-to-digital converters output and digital phase shifter output, and the output testing result is as the digital phase comparator of phase signal;
F) be used to limit the loop filter of the phase signal frequency band of digital phase comparator output; And be used for converting loop filter output to analog form, and with its digital-analog convertor as control voltage service voltage control generator.
Brief description
Fig. 1 is the block scheme of the clock recovery device structure of the embodiment of the invention;
Fig. 2 A is the structural drawing of used VCO in the clock recovery device of same embodiment;
Fig. 2 B be in the clock recovery device of same embodiment among the used VCO as the time-delay element circuit diagram of its element;
Fig. 3 is the VCO waveform figure of same embodiment;
Fig. 4 is the clock recovery device block diagram of prior art;
Fig. 5 A is the replay signal oscillogram of reading in the recording medium of clock recovery device of prior art;
Fig. 5 B is that the signal in the replay signal preamble area passes through the oscillogram that obtains behind the comparer of clock recovery device in the prior art;
Fig. 5 C is the oscillogram of the pulse-generator circuit output of clock recovery device in the prior art;
Fig. 5 D is the oscillogram of the delay control circuit output of clock recovery device in the prior art;
Fig. 5 E is when adopting phase control in the vibration starting stage, the VCO waveform figure of clock recovery device in the prior art.
Preferred embodiment is described
Clock recovery device to the embodiment of the invention describes according to Fig. 1～3.Fig. 1 is a clock recovery device block diagram in the preferred embodiment of the present invention.The recording medium 1 of storage numerical data is discoid recording medium.The signal storage of form is in each sector of recording medium shown in Fig. 5 A.2 from recording medium 1 playback record signal therein.2 replay signal of reading enter analogue-to-digital converters 3 (after this with ' ADC ' expression).ADC 3 utilizes the clock of digital phase shifter 5 outputs that replay signal is sampled, and converts thereof into digital form.The digital replaying signal of ADC 3 outputs enters initial phase detecting device 4 and digital phase comparator 7.
2 when entering preamble area, and initial phase detecting device 4 detects the initial phase of the digital replaying signal of ADC 3 conversion outputs, and keeps its value.Based on the initial phase that initial phase detecting device 4 detects, digital phase shifter 5 is shifted the oscillation phase of voltage-controlled oscillator 6 (after this with ' VCO ' expression) with selector switch.VCO 6 produces the circuit of clock according to digital-analog convertor 9 (after this with ' DAC ' expression) the analogue phase difference signal of output.
Figure 2 shows that the typical structure of VCO 6.The ring oscillator of VCO 6 for having structure shown in Fig. 2 A, wherein the individual time-delay element D of ' n ' (odd number) is in series into the ring.Use 7 groups of time-delay element D1, D2, D3, D4, D5, D6 and D7 in the present embodiment.The output terminal of time-delay element D1, D3, D5 and D7 is represented with P1, P2, P3 and P4 respectively, and the signal of each output terminal outputs to digital phase shifter 5.
Fig. 2 B is the structural drawing of time-delay element D.As shown in the figure, time-delay element D comprises the complementary MOS transistor 11 and 12 (cmos driver) that connects, provides the Control of Voltage constant-current supply 13 of electric current and the capacitor 14 that is connected with COMS output end of driver and ground wire for the drain electrode of transistor 11.Control of Voltage constant-current supply 13 provides leakage current according to the phase signal of 9 outputs of DAC shown in Fig. 1 for transistor 11 and 12.The delay time of signal ' τ ' is by the duration of charging control of capacitor 14 among the time-delay element D.Therefore, the oscillation frequency of VCO 6 is by the output voltage decision of progression ' n ' and the DAC 9 of time-delay element D.In the aforesaid structure, if the output voltage of DAC 9 is constant, the clock that can obtain having required phase place so by arbitrary output of selecting between the output terminal P1-P4.
Phase differential among Fig. 1 between the clock of digital phase comparator 7 detection digital replaying signal reference point and digital phase shifter 5 outputs, thus the digit phase difference signal produced.The loop filter 8 that is used to limit digital phase signal frequency band comprises totalizer, multiplier and selector switch etc.Digital-analog convertor (' DAC ') 9 becomes the analogue phase difference signal with the Digital Phase Difference conversion of signals of loop filter 8 outputs.By using the VCO 6 of simulation control, PLL forms with digital form.
The clock of digital phase shifter 5 outputs not only offers ADC 3, also offers initial phase detecting device 4, digital phase comparator 7, loop filter 8 and DAC 9, although this does not draw in the drawings.
When the replay signal high speed is extracted clock, clock recovery device is worked in mode hereinafter described.When to order such as 2 send tracking to recording medium 1, search, initial phase detecting device 4, digital phase shifter 5 and digital phase comparator 7 quit work respectively, otherwise PLL is with complete release.In the case, the oscillation frequency of VCO 6 changes to predetermined value from initial value automatically, when oscillation frequency near replay signal in during the frequency of clock, initial phase detecting device 4, digital phase shifter 5 and digital phase comparator 7 begin respectively to start.
Under this state, right overhead 2 when entering preamble area, not only need accurately to detect initial phase difference information but also will keep it, also will feed back to the VCO 6 that uses initial phase difference information to vibrate rapidly.For realizing this function, after sending digital phase shifter 5 to, the initial phase difference information of initial phase detectors 4 detections carries out following processing.
In the VCO that constitutes with ring oscillator shown in Fig. 2 A, has the vibration output (clock) of initial reference phase place from output terminal P4 output.In the case, when be ' T ' oscillation period, obtain the vibration output of the out of phase that increases progressively with (m/n) T with respect to fixed phase (m equals 1 or 2) respectively from output terminal P1, P2 and P3.The vibration output waveform that obtains from output terminal P1-P4 with said method as shown in Figure 3.According to the initial phase difference information that is detected and kept by initial phase detecting device 4, digital phase shifter 5 is selected the most approaching zero the clock of initial phase difference from the clock of a plurality of outs of phase of VCO 6 outputs.Aforesaid operations can use the clock that can preferably reflect the initial phase difference testing result at once.
Then, the phase differential between the clock of digital phase comparator 7 detection digital replaying signal reference point and digital phase shifter 5 outputs, and produce the digit phase difference signal.Digital comparator by loop filter 8 and DAC 9 with the corresponding mode of playback clock frequency phase signal is offered the oscillation frequency of VCO 6 with control VCO 6 all the time.
In addition, if the element number (as the progression of time-delay element) of the VCO 6 that constitutes with the ring oscillator form increases, in the process that from replay signal, extracts clock, can more accurately introduce so phase place and Frequency Synchronization.
Industrial applicibility
According to the present invention, though in the replay signal frequency change very big or replay signal frequency change In the system, also can believe according to the initial phase difference that obtains from the replay signal preamble area frequently Breath arranges clock phase accurately and fast. Therefore can be to the height of phase place and the frequency of PLL Speed is introduced synchronously, and the replay signal frequency change is exerted an influence hardly.

Claims (2)

1. a clock recovery device with the signal of a scan recording media to reset and wherein to write down, and produces the clock that is used for data decode in the synchronizing signal that comprises from replay data, and this clock recovery device comprises:
A) voltage-controlled oscillator, its oscillation frequency is used for producing simultaneously the fixed phase clock clock different with its phase place with another by the control Control of Voltage;
B) replay signal that adopts above-mentioned clock that described head is read converts the analogue-to-digital converters of digital replaying signal to;
C) the initial phase detecting device of the initial phase difference between the fixed phase clock of the replay signal of the described analogue-to-digital converters output of detection and the output of described voltage-controlled oscillator;
D), then the clock of particular phases is given the digital phase shifter of described analogue-to-digital converters as sampled signal so that the mode of initial phase difference minimum is selected the clock phase of described voltage-controlled oscillator;
E) phase differential between the clock of the replay signal of the described analogue-to-digital converters output of detection and the output of described digital phase shifter, and the output testing result is as the digital phase comparator of phase signal;
F) be used to limit the loop filter of the phase signal frequency band of described digital phase comparator output; And
G) convert described loop filter output to analog form, offer the digital-analog convertor of described voltage-controlled oscillator then as control voltage.
2. the clock recovery device described in claim 1, wherein said voltage-controlled oscillator comprises ring oscillator, it has the time-delay element that n (n is an odd number) is in series into the ring, and described digital-analog convertor with time-delay element first, second ... each in n output terminal is exported the mode of the clock of out of phase respectively, and output was controlled the signal lag time of time-delay element according to voltage.
CN99801575A 1998-09-11 1999-09-08 Clock recovery device Pending CN1277720A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP258042/1998 1998-09-11
JP10258042A JP2000090589A (en) 1998-09-11 1998-09-11 Clock recovering device

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Publication Number Publication Date
CN1277720A true CN1277720A (en) 2000-12-20

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CN99801575A Pending CN1277720A (en) 1998-09-11 1999-09-08 Clock recovery device

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JP (1) JP2000090589A (en)
KR (1) KR20010031917A (en)
CN (1) CN1277720A (en)
TW (1) TW448426B (en)
WO (1) WO2000016331A1 (en)

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CN100442380C (en) * 2003-04-23 2008-12-10 索尼株式会社 Reproduction apparatus and method
CN101820340A (en) * 2010-02-22 2010-09-01 中兴通讯股份有限公司 Clock recovery device and method
CN101288259B (en) * 2005-11-17 2011-05-25 哉英电子股份有限公司 Clock data restoration device
CN101316369B (en) * 2007-05-29 2011-08-17 索尼株式会社 Image processing device and method

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CN100442379C (en) * 2004-06-17 2008-12-10 瑞昱半导体股份有限公司 Method and apparatus for detecting synchronous signal of CD reading signals
CN100411046C (en) * 2004-06-23 2008-08-13 瑞昱半导体股份有限公司 Adjustment and adjuster for sampling clock phase and synchronizing signal forescasting time sequence
US9246480B2 (en) * 2014-06-02 2016-01-26 Mediatek Inc. Method for performing phase shift control in an electronic device, and associated apparatus
US9608798B2 (en) 2014-06-02 2017-03-28 Mediatek Inc. Method for performing phase shift control for timing recovery in an electronic device, and associated apparatus
US9654116B1 (en) 2015-10-27 2017-05-16 Mediatek Inc. Clock generator using resistive components to generate sub-gate delays and/or using common-mode voltage based frequency-locked loop circuit for frequency offset reduction
EP3163754A1 (en) * 2015-10-27 2017-05-03 MediaTek Inc. Method for performing phase shift control for timing recovery in an electronic device, and associated apparatus

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JPH01181323A (en) * 1988-01-14 1989-07-19 Nec Corp Initial phase matching circuit for phase locked loop oscillator
JP3646313B2 (en) * 1993-08-31 2005-05-11 ソニー株式会社 CLOCK GENERATOR AND DATA REPRODUCER
JPH07201136A (en) * 1993-12-28 1995-08-04 Sony Corp Delay line capable of selecting phase amount
JP3411120B2 (en) * 1995-03-08 2003-05-26 富士通株式会社 PLL circuit
JPH09326689A (en) * 1996-06-03 1997-12-16 Hitachi Ltd Clock generation circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100442380C (en) * 2003-04-23 2008-12-10 索尼株式会社 Reproduction apparatus and method
CN101288259B (en) * 2005-11-17 2011-05-25 哉英电子股份有限公司 Clock data restoration device
CN101316369B (en) * 2007-05-29 2011-08-17 索尼株式会社 Image processing device and method
CN101820340A (en) * 2010-02-22 2010-09-01 中兴通讯股份有限公司 Clock recovery device and method

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WO2000016331A1 (en) 2000-03-23
KR20010031917A (en) 2001-04-16
TW448426B (en) 2001-08-01
JP2000090589A (en) 2000-03-31

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