經濟部中央標準局貝工消費合作社印裝 4443 24 4360twf.doc/006 A7 B7 五、發明説明（ί ) 本發明是有關於一種介電層的製造方法，且特別是 有關於一種低介電係數介電層的製造方法β 隨著半導體元件的線寬不斷地縮小，金屬線與金屬 線間的距離也越來越短，導致寄生電容(Parasitic Capacitor) 的現象越來越嚴重，因此內金屬介電層（Inter-Metal Dielectrics ; IMD)介電係數（Dielectric Constant)的大小 也愈來愈重要。而介電層的介電係數越大，寄生電容越易 產生，導致 RC 時間延遲（Resistance Capacitance Time Delay ; RC delay)更形嚴重，而降低電路傳輸速度。因此藉由降低 介電層的介電係數，可降低RC時間延遲，增進元件的操 作速度。 但習知使用低介電係數介電層時，常常因爲介電係 數不夠低而無法降低金靥線間的寄生電容》或於後續金屬 化製程中，由於低介電係數介電材料具有吸水性，導致介 電層內部含有水氣，使得後續所形成的金屬插塞產生毒化 (Poison)的現象》 本發明提出一種低介電係數介電層的製造方法，於 基底上形成金屬線，再於金屬線之側壁形成間隙壁，然g 使用常壓化學氣相沈積法、次常壓化學氣相沈積法或電漿 加強型化學氣相沈積法於基底上形成一層氧化層，藉由控 制氧化層的的形成方法同時使位於金屬線之間的氧化層开多 成孔洞。 由於本發明之介電層係由氧化層與孔洞所構成，使 間距較小的金屬線間的介電層具有極低的介電係數可避 3 本紙張尺度適用中ββΓ家^率（CNS ) Λ4规格（210>ί297ϋ 〜 ---------#------II-------ί' (請先閱讀背面之注意事項再填寫本頁) A7 B7 4443 24 4360twf.doc/006 五、發明説明（i) 免間距較小的金屬線間產生寄生電容，降低RC時間延遲’ 增進元件的操作速度。因此本發明之介電層可取代習知無 孔洞之低介電係數材料，避免低介電係數材料容易造成# 屬毒化之缺點。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉較佳實施例，並配合所附圖式’作詳 細說明如下： 圖式之簡單說明： 第1A圖〜第1D圖繪示依照本發明一較佳實施例的一 種低介電係數介電層的製造方法剖面示意圖。 圖式之標記說明： 100 :基底 102 :金屬層 102a、102b :金屬線 104、106 :氧化層 104a、104b :間隙壁 120 :孔洞 150 :介電層 官施例 第1A圖~第1D圖繪示依照本發明一較佳實施例的一 種低介電係數介電層的製造方法剖面示意圖。 請參照第1A圖，提供一已完成半導體元件之基底 100，比如基底100上已形成金氧半電晶體元件(未繪示）， 於基底100上形成圖案化之金屬層102，金靥層1〇2包括 4 本紙張尺度適用中Η國家操率（CNS ) A4规格（2丨0X297公釐） 一一 ----：-----)策------π------J (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作杜印製 4443 2 4 A7 B7 43 60twf_doc/006 五、發明説明（>) (請先閲讀背面之注意事項再填寫本頁) 有金屬線102a、l〇2b’其形成方法例如先沉積一層金屬材 料後，再進行微影蝕刻製程，而金屬線l〇2a與金屬線102b 之間距例如約小於0.6以下。 請參照第1B圖，於基底100與金屬線102a ' 102b上 形成一層氧化層104，例如使用化學氣相沈積法。 請參照第1C圖，進行回蝕刻，例如乾蝕刻，使氧化 層104 (第1Β圖）分別於金屬線102a和金屬線102b之側 壁形成間隙壁104a與104b » 請參照第ID圖，於基底100上沈積一層氧化層106， 例如使用常壓化學氣相沈積法（Atmospheric Pressure Chemical Vapor Deposition ; APCVD)、次常壓化學氣相沈 積法（Sub-Atmospheric Pressure Chemical Vapor Deposition : SACVD)或電漿力口強型化學氣相沈積法(Plasma Enhanced Chemical Vapor Deposition ; PECVD)，使氧化層 106 於金屬 線102a、102b之間形成均勻且高度不會太高的孔洞 (Void)120，而氧化層106與孔洞120則共同組成介電層 150。 經濟部中央梯準局貝工消費合作社印裝 完成介電層150之製作後，氧化層106於金屬線102a、 102b之間形成有孔洞120。由於兩相鄰金屬線l〇2a、102b 間的介電層150爲孔洞120與氧化餍106所構成。而氧化 層106之二氧化矽材料介電係數爲4.0-4.9，孔洞120中空 氣的介電係數爲1.00059，使得金屬線l〇2a、102間所形成 之介電層150的等效介電係數會較二氧化矽低，甚至低於 一般低介電係數材料。一般而言，間距愈短的金屬線間， 5 本紙張尺度通用中國國家樣牟（CNS ) A4说格（210X297公漦) 4443 24 4360twf.doc/006 A7 B7 五、發明説明（V ) 寄生電容及RC延遲的現象尤其明顯。藉由降低金屬線 102a、102b間介電層150的介電係數，可避免間距較小的 金屬線102a與金屬線102b間產生寄生電容，並降低RC 時間延遲，因此能增進元件的操作速度。 由上述本發明較佳實施例可知，應用本發明具有下 列優點： 1) 由於本發明之介電層係由二氧化矽與孔洞所構成， 使金屬線間的介電層具有極低的介電係數。可避免金屬線 間產生寄生電容，得以降低RC時間延遲，增進元件的操 作速度。 2) 由於本發明之介電層結構具有孔洞，使得高介電係 數之材料因爲配合孔洞而具有低介電係數之效果，因此可 取代低介電係數材料，避免使用低介電係數材料所容易導 致的金屬毒化現象 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 --------「冬II (請先閲讀背面之注$項再填寫本頁) 訂 經濟部中央梂準局貞工消费合作杜印製 適 公Printed by Shellfish Consumer Cooperative of Central Standards Bureau of the Ministry of Economic Affairs 4443 24 4360twf.doc / 006 A7 B7 V. INTRODUCTION TO THE INVENTION The invention relates to a method for manufacturing a dielectric layer, and in particular to a low dielectric constant Manufacturing method of dielectric layer β As the line width of semiconductor devices is continuously reduced, the distance between metal lines and metal lines is getting shorter and shorter, resulting in more and more parasitic capacitance. Therefore, the internal metal dielectric The size of the dielectric constant (Inter-Metal Dielectrics; IMD) is also more and more important. The larger the dielectric constant of the dielectric layer, the more easily the parasitic capacitance is generated, resulting in a more severe RC time delay (RC delay), which reduces the circuit transmission speed. Therefore, by reducing the dielectric constant of the dielectric layer, the RC time delay can be reduced and the operation speed of the device can be improved. However, when using a low dielectric constant dielectric layer, it is often impossible to reduce the parasitic capacitance between the metal wires because the dielectric constant is not low enough. Or in the subsequent metallization process, the low dielectric constant dielectric material has water absorption properties. This causes the dielectric layer to contain water vapor, which causes the subsequent formation of metal plugs to cause poisoning (Poison). The present invention provides a method for manufacturing a low-dielectric-constant dielectric layer, forming a metal line on a substrate, and then The side wall of the metal wire forms a gap. Then, an atmospheric pressure chemical vapor deposition method, a sub-normal pressure chemical vapor deposition method, or a plasma enhanced chemical vapor deposition method is used to form an oxide layer on the substrate. At the same time, the oxide layer between the metal lines is formed into holes. Since the dielectric layer of the present invention is composed of an oxide layer and a hole, the dielectric layer between the metal wires with a small distance has a very low dielectric coefficient, which can be avoided. ΒβΓ family rate (CNS) Λ4 specifications (210 > ί297ϋ ~ --------- # ------ II ------- ί '(Please read the precautions on the back before filling this page) A7 B7 4443 24 4360twf.doc / 006 V. Description of the invention (i) No parasitic capacitance is generated between the metal wires with a small pitch, and the RC time delay is reduced, thereby improving the operation speed of the device. Therefore, the dielectric layer of the present invention can replace the conventional low-hole-free low Dielectric material, to avoid the disadvantage of low-dielectric material that is susceptible to poisoning. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following exemplifies preferred embodiments and cooperates with all The detailed description of the drawings is as follows: Brief description of the drawings: FIGS. 1A to 1D are schematic cross-sectional views illustrating a method for manufacturing a low-k dielectric layer according to a preferred embodiment of the present invention. Explanation of symbols: 100: substrate 102: metal layers 102a, 102b: metal wires 104, 106: Chemical layers 104a, 104b: spacers 120: holes 150: dielectric layers. Figures 1A to 1D show schematic cross-sectional views of a method for manufacturing a low-k dielectric layer according to a preferred embodiment of the present invention. Please refer to FIG. 1A to provide a completed semiconductor device substrate 100, for example, a metal oxide semiconductor device (not shown) has been formed on the substrate 100, and a patterned metal layer 102 and a gold layer are formed on the substrate 100. 1〇2 includes 4 paper standards applicable to the Central European National Operation (CNS) A4 specifications (2 丨 0X297 mm) one by one ------------) policy ------ π --- --- J (Please read the notes on the back before filling out this page) Duty printing of employee cooperation of the Central Standards Bureau of the Ministry of Economic Affairs 4443 2 4 A7 B7 43 60twf_doc / 006 V. Description of the invention (>) (Please read the back first For details, please fill in this page again.) There are metal wires 102a, 102b '. The method of forming them is, for example, depositing a layer of metal material, and then performing the lithography etching process. The distance between the metal wires 102a and 102b is, for example, less than about 0.6 or less. Referring to FIG. 1B, an oxide layer 104 is formed on the substrate 100 and the metal lines 102a 'to 102b. For example, a chemical vapor deposition method is used. Please refer to FIG. 1C for etch-back, such as dry etching, so that the oxide layer 104 (FIG. 1B) forms gaps 104a and 104b on the sidewalls of the metal lines 102a and 102b respectively. »Please refer to the ID chart on the substrate 100. An oxide layer 106 is deposited thereon, for example, using Atmospheric Pressure Chemical Vapor Deposition (APCVD), Sub-Atmospheric Pressure Chemical Vapor Deposition: SACVD, or plasma pressure Strong chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition; PECVD) enables the oxide layer 106 to form uniform and not too high holes 120 (Void) 120 between the metal lines 102a, 102b, and the oxide layer 106 and the holes 120 collectively constitute the dielectric layer 150. Printed by the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, after the fabrication of the dielectric layer 150, the oxide layer 106 forms a hole 120 between the metal wires 102a, 102b. The dielectric layer 150 between the two adjacent metal lines 102a and 102b is composed of the hole 120 and the hafnium oxide 106. The dielectric coefficient of the silicon dioxide material of the oxide layer 106 is 4.0-4.9, and the dielectric coefficient of the air in the hole 120 is 1.00059, which makes the equivalent dielectric coefficient of the dielectric layer 150 formed between the metal lines 102a and 102 Will be lower than silicon dioxide, or even lower than the general low dielectric constant materials. Generally speaking, the shorter the distance between the metal lines, the 5 paper sizes are common to the Chinese National Sample (CNS) A4 grid (210X297 cm) 4443 24 4360twf.doc / 006 A7 B7 V. Description of the invention (V) Parasitic capacitance And the phenomenon of RC delay is particularly obvious. By reducing the dielectric constant of the dielectric layer 150 between the metal lines 102a and 102b, it is possible to avoid parasitic capacitance between the metal lines 102a and 102b with a small pitch, and reduce the RC time delay, thereby improving the operation speed of the device. It can be known from the foregoing preferred embodiments of the present invention that the application of the present invention has the following advantages: 1) Since the dielectric layer of the present invention is composed of silicon dioxide and holes, the dielectric layer between the metal lines has extremely low dielectric coefficient. It can avoid the parasitic capacitance between the metal lines, which can reduce the RC time delay and increase the operating speed of the component. 2) Since the dielectric layer structure of the present invention has holes, the material with high dielectric constant has the effect of low dielectric constant because of the holes, so it can replace the low dielectric constant material and avoid the use of low dielectric constant materials. Resulting metal poisoning phenomenon Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. -------- "Winter II (please read the note on the back before filling in this page) Order Print