p P432613 A7 3686twf.doc/008 ^ B7 五、發明説明（i ) •本發明是有關於一種具有低介電常數之高熱導（High Thermal Conductivity)層的半導體元件製造方法，且特別 I I t ' 1 rt ^ (11·先閱讀背而之注意事項再硝寫本頁} 是有關於一種可在半導體元件之內金屬介電層中，增加垂 直熱導（Vertical Thermal Conductivity)的製造方法。 對於積體電路的設計而言，內連線的延遲對於操作速 度的發展是一很重大的限制。爲了減少訊號傳播在內連線 中所造成的延遲，對於超大型積體電路（VLSI)的設計而 言，內連線的延遲已藉由利用多種介電常數較氧化砂層爲 低的新式絕緣材料而降低。一般而言，此種新式介電材料 的熱導都較傳統之氧化矽低，然而此種趨勢發展的結果， 會影響到諸如VLSI可靠性(Reliability)的問題。例如，具 有較差的附著能力（Adhesion)、容易導致出氣（Outgassing) 的現象、增加熱阻而導致溫度場（Temperature Field)之問 題等。在目前的硏究報告中指出，介電材料的垂直熱導大 約是基底二氧化矽材料的1/6 ;而相鄰金屬線間之側向熱 導大約與基底的二氧化矽相同。_ •傳統爲了克服上述問題，故而利用部份回蝕刻的方法’ 然而卻降低了袠面的平坦度；或是利用非回蝕刻的方法， 但亦需利用其它處理步驟，卻也因而增加了介電層的厚 度，亦導致內連線延遲的問題。 第1A〜1C圖所示乃傳統半導體元件之內介電層的製程 剖面圖。首先’請參照第1A圖，在一形成有一金屬內連 線I2之半導體基底1〇上方沉積一下層氧化層I4，覆蓋半 導體基底’作爲後續內金屬介電層之下層。 .__ —丨 一 一- 3 r F4 3261 3 3686twf.d〇c/〇〇Q A7 ____ _____ B7 __ - _ ——- 五、發明説明（7) HI ^^^1 mf .^n I 女^ -10 ("*先閱讀背而之注意事項再填寫本頁) 接著’如第1B圖所示，塗佈一旋塗式玻璃（SOG)或以 次常壓化學氣相沉積法（SACVD)形成一氧化層16於下層 氧化層14上方^並以回蝕刻的方法，例如是以乾蝕刻法 去除部份氧化層16至下層氧化層14或金屬內連線12處， 以利後續平坦化的製程。 •然後’如第1C圖所示，以電漿化學氣相沉積法形成 一內金屬介電層18於氧化層16上方。最後，再以化學機p P432613 A7 3686twf.doc / 008 ^ B7 V. Description of the Invention (i) • The present invention relates to a method for manufacturing a semiconductor device having a high thermal conductivity (High Thermal Conductivity) layer with a low dielectric constant, and particularly II t '1 rt ^ (11 · Read the precautions before writing this page} This is a manufacturing method that can increase the vertical thermal conductivity in the metal dielectric layer of the semiconductor device. For circuit design, the delay of the interconnect is a significant limitation on the development of operating speed. In order to reduce the delay caused by signal propagation in the interconnect, for the design of very large-scale integrated circuits (VLSI) The delay of the interconnect has been reduced by using a variety of new insulation materials with a lower dielectric constant than the sand oxide layer. Generally speaking, the thermal conductivity of this new type of dielectric material is lower than that of traditional silicon oxide, but this kind of As a result of trends, issues such as VLSI reliability (Reliability) will be affected. For example, it will have poor adhesion, easily lead to outgassing, Increasing thermal resistance causes problems with Temperature Field, etc. In the current research report, it is pointed out that the vertical thermal conductivity of a dielectric material is about 1/6 of that of a silicon dioxide substrate; The lateral thermal conductivity is about the same as that of the silicon dioxide in the substrate. _ • Traditionally, in order to overcome the above-mentioned problems, partial etch-back methods are used. However, the flatness of the surface is reduced; or non-etch-back methods are used, but It also needs to use other processing steps, but it also increases the thickness of the dielectric layer, which also causes the problem of interconnect delay. Figures 1A to 1C are cross-sectional views of the manufacturing process of the dielectric layer of a conventional semiconductor device. First, ' Referring to FIG. 1A, an oxide layer I4 is deposited on a semiconductor substrate 10 having a metal interconnection I2 formed thereon, covering the semiconductor substrate as the lower layer of the subsequent internal metal dielectric layer. .__ — 丨 一 -1-3 r F4 3261 3 3686twf.d〇c / 〇〇Q A7 ____ _____ B7 __-_ ——- V. Description of the Invention (7) HI ^^^ 1 mf. ^ n I Female ^ -10 (" * read first (Further considerations should be completed on this page) and then 'as in Section 1B As shown, a spin-on-glass (SOG) coating or a sub-normal pressure chemical vapor deposition (SACVD) method is used to form an oxide layer 16 over the lower oxide layer 14 and etch back, such as dry etching. Method to remove part of the oxide layer 16 to the lower oxide layer 14 or the metal interconnects 12 to facilitate subsequent planarization processes. • Then, as shown in Figure 1C, an internal metal is formed by plasma chemical vapor deposition. The dielectric layer 18 is above the oxide layer 16. Finally, the chemical machine
械硏磨法平坦化內金屬介電層18，並留下厚度約爲8000A β內金屬介電層18的厚度，完成傳統半導體元件之內介 電層的製程。 程中，所得到的內金屬介電層，由於在垂直 方向之熱導能力（如上所稱之垂直熱導）遠較其餘部份熱導 fg力’例如爲相鄰金屬線間之側向熱導或是基底之熱 導的1/6 °亦即在垂直方向的散熱能力不佳，因而容易影 響半導體元件之電氣特性，甚而破壞元件。 有鑑於此，本發明的主要目的就是在提供一種具有低 介電常數之高熱導層的半導體元件製造方法，利用低介電 常數之介電材料來作爲內金屬介電層，以氮氣離子植入來 增加內金屬介電層之垂直熱導，改善介電材料之散熱能 力。並同時利用平坦化效果極佳之高分子化合物等來改善 平坦化的效果’不需利用化學機械硏磨法即可有效達到介 電學的平坦化。 根據本發明的目的，提出一種具有低介電常數之高熱 導層的半導體元件製造方法’用以在具有一金屬內連線之 4 本紙张尺度诚川屮 1¾ ‘樣蜱（CNs ) AAiUi ( 2ϊ〇Χ 297^7} "— - Γ 霡4326 1 3 3686twf.d〇c/008 A7 B7 f n· ， II .·Ι·ί. J . , I .....---- - --- 五、發明説明（4 ) ^^^1 s ^^^1 ^^^1 ^^^1 n t L9^ n^i I - HI TJ 、-" ("先間讀背而之注意事項再"寫本頁) 半^體基底上方形成一內金屬介電層。首先，形成一下層 氧化層於半導體基底上方，作爲內金屬介電層與金屬內連 線接觸之下層。接著，形成一具有低介電常數之可流動性 的溝塡層，具有較佳的平坦化效果。然後，形成一光阻層 於溝塡層上方，並定義溝塡層以得到一反調光阻覆蓋於金 屬內連線以外之部份。之後，以反調光阻爲離子植入罩幕， 進行氮氣離子植入，於溝塡層中形成一高熱導結構，再移 除反調光阻，改善傳統造成低垂直熱導之缺點。最後，沉 積一頂氧化層於溝塡層上方，完成內金屬介電層的製造方 法。 根據本發明的目的，另外提出一種具有低介電常數之 高熱導層的半導體元件製造方法，其中，內金屬介電層係 形成於具有複數個金屬內連線之半導體基底上方。在內金 屬介電層中包括有一下層氧化層、一具有低介電常數之可 流動性的溝塡層與一頂氧化層。其中，形成高垂直熱導之 方法，係以一反調光阻覆蓋於金屬內連線以外之部份，然 後利用反調光阻爲離子植入罩幕，進行氮氣離子植入，將 未被反調光阻所覆蓋之原有薄膜的特性改變’使其不具有 低介電常數，但有高的熱穩定性’進而具有較好的熱導性 質。 本發明在高熱導層的半導體元件製造方法中’利用有 機高分子化合物或氫三氧矽甲烷以得到平坦之內金屬介電 層’不需以化學機械硏磨法，來得到較佳的平坦化’進而 避免以乾蝕刻法作回蝕刻時’在晶片表面形成副產物（By- 5 木紙认尺度述川屮( (.NS ) Λ4规梠（公勢） Α7 Β7 12, 22 :金屬內連線 16 :氧化層 26 :溝塡層 28 :光阻層 29 :頂氧化層 醪43261 3 3 6 8 6 twf . doc/0 0 8 五'發明説明（0)The mechanical honing method planarizes the inner metal dielectric layer 18 and leaves the thickness of the inner metal dielectric layer 18 with a thickness of about 8000 A β to complete the process of the inner dielectric layer of the conventional semiconductor device. In the process, the obtained inner metal dielectric layer has a higher fg force than the rest of the thermal conductivity due to its thermal conductivity in the vertical direction (such as the vertical thermal conductivity mentioned above). For example, it is the lateral heat between adjacent metal lines. 1/6 ° of the substrate or the thermal conductivity of the substrate, that is, the heat dissipation ability in the vertical direction is not good, so it is easy to affect the electrical characteristics of the semiconductor device, and even damage the device. In view of this, the main object of the present invention is to provide a method for manufacturing a semiconductor device with a high thermal conductivity layer having a low dielectric constant, using a low dielectric constant dielectric material as an inner metal dielectric layer, and implanting with nitrogen ions. To increase the vertical thermal conductivity of the inner metal dielectric layer and improve the heat dissipation capability of the dielectric material. At the same time, the use of high-molecular compounds that have excellent planarization effects to improve the planarization effect 'can effectively achieve dielectric planarization without using a chemical mechanical honing method. According to the purpose of the present invention, a method for manufacturing a semiconductor device with a high thermal conductivity layer having a low dielectric constant is proposed to be used on a 4-sheet paper with a metal interconnect, Cheng Chuan 屮 1¾ ', like ticks (CNs), AAiUi (2ϊ 〇Χ 297 ^ 7} "--Γ 霡 4326 1 3 3686twf.d〇c / 008 A7 B7 fn ·, II. · Ι · ί. J., I .....---------- -V. Description of the invention (4) ^^^ 1 s ^^^ 1 ^^^ 1 ^^^ 1 nt L9 ^ n ^ i I-HI TJ 、-" (" Precautions for reading first &Quot; Write this page) An internal metal dielectric layer is formed over the semi-substrate substrate. First, a lower oxide layer is formed over the semiconductor substrate as the lower layer of the internal metal dielectric layer in contact with the metal interconnects. Next, a layer is formed A flowable gully layer having a low dielectric constant has a better planarization effect. Then, a photoresist layer is formed over the gully layer, and the gully layer is defined to obtain an inverse photoresistance covering The part other than the metal interconnects. After that, an inversion photoresist was used as the ion implantation mask, and nitrogen ion implantation was performed to form a high thermal conductivity structure in the trench layer, and the inversion was removed. Resistance, improving the traditional disadvantage of low vertical thermal conductivity. Finally, a top oxide layer is deposited over the trench layer to complete the manufacturing method of the inner metal dielectric layer. According to the purpose of the present invention, another method with a low dielectric constant is proposed. A method for manufacturing a semiconductor element with a high thermal conductivity layer, wherein an inner metal dielectric layer is formed over a semiconductor substrate having a plurality of metal interconnects. The inner metal dielectric layer includes a lower oxide layer and a low dielectric constant. The flowable gully layer and an oxide layer. Among them, the method of forming a high vertical thermal conductivity is to cover an area outside the metal interconnect with an inverting photoresistor, and then use the inverting photoresistor for ions. Implanting the mask and performing nitrogen ion implantation will change the characteristics of the original film not covered by the inverting photoresist 'to make it not have low dielectric constant, but high thermal stability' and thus have better Thermal conductivity. In the method for manufacturing a semiconductor element with a high thermal conductivity layer, the present invention does not need to use an organic polymer compound or hydrogen oxytrimethane to obtain a flat inner metal dielectric layer. Mechanical honing method to obtain better flattening, thereby avoiding the formation of by-products on the wafer surface when dry etching is used as an etch back (By-5 Wood and Paper Recognition Standards described in Kawasaki ((.NS) Λ4 gauge) ( Public potential) Α7 Β7 12, 22: metal interconnects 16: oxide layer 26: trench layer 28: photoresist layer 29: top oxide layer 43261 3 3 6 8 6 twf.doc / 0 0 8 5 'Description of the invention (0)
Product)高分子化合物，導致可靠度的問題。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： ’圖式之簡單說明： 第1A〜1C圖繪示乃傳統半導體元件之內介電層的製程 剖面圖；以及 第2A〜2D圖繪示依照本發明一較佳實施例的一種具有 低介電常數之高熱導層的半導體元件製程剖面圖。 標號說明： 10, 20 :半導體基底 14, 24 :下層氧化層 18 :內金屬介電層 26a :高熱導結構 28a :反調光阻 較佳實施例 請參照第2A〜2D圖，其繪示依照本發明一較佳實施例 的一種具有低介電常數之高熱導層的半導體元件製程剖面 圖。首先，如第2A圖所示，在一形成有一金屬內連線22 之半導體基底20上方沉積一下層氧化層24’覆蓋半導體 基底20，作爲後續內金屬介電層與金屬內連線22接觸之 下層，因此具有較緻密之結構°此一下層氧化層24例如 是以電漿化學氣相沉積法形成，其厚度可依照設計準則 (Design Rule)以及製程裕度（Process Window)作調整’較佳 的厚度約爲500〜3000A左右。Product) polymer compounds, causing reliability problems. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: 'A brief description of the drawings: Sections 1A to 1C 2A to 2D are cross-sectional views of a semiconductor device with a high thermal conductivity layer having a low dielectric constant according to a preferred embodiment of the present invention; . DESCRIPTION OF SYMBOLS: 10, 20: semiconductor substrate 14, 24: lower oxide layer 18: inner metal dielectric layer 26a: high thermal conductivity structure 28a: inverting photoresistor. For a preferred embodiment, please refer to FIGS. 2A to 2D. A cross-sectional view of a semiconductor device with a high thermal conductivity layer having a low dielectric constant in a preferred embodiment of the present invention. First, as shown in FIG. 2A, an oxide layer 24 'is deposited on a semiconductor substrate 20 having a metal interconnect 22 formed thereon to cover the semiconductor substrate 20 as a subsequent contact between the metal dielectric layer and the metal interconnect 22. The lower layer has a denser structure. The lower oxide layer 24 is formed by plasma chemical vapor deposition, for example, and its thickness can be adjusted according to the Design Rule and Process Window. 'Better The thickness is about 500 ~ 3000A.
In ^^^1 1 ^^^1 I ^^^1 ml In - 1 Λν 、-·· (1ft先閱讀背而之注意事項再蛾ΪΪ?本頁) ί) .1 ίΐί ίί η 印 本纸张尺度进川屮呤（（.NS )八4现祀（2!〇Χ297公t ) ηriii-1v*:pifipil':+· 「羼4 32 6 1 3 A7 3686twf.doc/008 ____________—^ 五、發明説明（《） 厚度約爲500〜300〇A左右。 接著’如第2B圖所示’形成一具有低介電常數之可 流動性的溝塡層20 ’例如是黏稠性高、平坦化效果佳的有 機高分子化合物R7或是氫三氧矽甲烷（Hydrogen Silses-quioxane，HSQ) ’利用溝塡層26之低介電常數與高流動 性而得到較佳的平坦化效果。並且不需再以乾蝕刻的方 法來回蝕刻去除旋塗式玻璃’避免在晶片表面形成高分 子化合物’導致可靠度的問題。另外，更可改善出氣 (Out-gassing)現象所形成之中毒介層（p〇is〇n Via)的問 題。然後’如第2C圖所示，形成一厚度約5000〜1000A之 光阻層28覆蓋於溝塡層26上方，並以微影與蝕刻的方法 定義光阻層28,得到一金屬內連線22的反調(Reverse T〇ne) 光阻28a ’反調光阻28a係覆蓋於金屬內連線22以外之部 份。之後，並以反調光阻28a作爲離子植入罩幕，進行氮 氣離子植入於金屬內連線22上方之溝塡層26，得到一高 熱導結構26a，使得此部份之溝塡層26具有較高之熱導， 亦即使得內金屬介電層具有較高之垂直熱導，並具有較低 之元件電容値。 最後，如第2D圖所示，將反調光阻移除，並沉 積〜頂氧化層（Cap Oxide Layer)29於溝塡層26上方，厚 度約爲1000〜1〇0〇A左右，完成本發明內金屬介電層的製 造方法。 因此，本發明的特徵之一是提供一種具有低介電常數 之高熱導層的半導體元件製造方法’利用有機高分子化合In ^^^ 1 1 ^^^ 1 I ^^^ 1 ml In-1 Λν,-·· (1ft read the precautions before going back then the moth? This page) ί) .1 ίΐί ίί η Size of printed paper Into the Chuanxiongxuan ((NS) Eighty-four present offering (2! 〇 × 297 public t) ηriii-1v *: pifipil ': + · "羼 4 32 6 1 3 A7 3686twf.doc / 008 ____________ — ^ V. Invention Explanation (") The thickness is about 500 to 300 Å. Then, as shown in Fig. 2B, a flowable trench layer 20 having a low dielectric constant is formed. For example, the thickness is high and the planarization effect is good. Organic polymer compound R7 or Hydrogen Silses-quioxane (HSQ) 'uses the low dielectric constant and high fluidity of the trench layer 26 to obtain a better planarization effect. The dry etching method etches back and forth to remove the spin-on glass 'to avoid the formation of polymer compounds on the surface of the wafer' leading to reliability problems. In addition, it can also improve the toxic interposer formed by the out-gassing phenomenon (pois. n Via) problem. Then, as shown in FIG. 2C, a photoresist layer 28 having a thickness of about 5000 to 1000 A is formed to cover the trench layer 26. The photoresist layer 28 is defined by lithography and etching methods to obtain a Reverse Tone photoresistor 28a. The photoresist 28a 'reverse photoresistor 28a is covered on the part other than the metal interconnect 22 Then, the inversion photoresist 28a is used as an ion implantation mask, and nitrogen ion implantation is performed on the trench layer 26 above the metal interconnect 22 to obtain a high thermal conductivity structure 26a, which makes the trench of this part Layer 26 has a higher thermal conductivity, which means that the inner metal dielectric layer has a higher vertical thermal conductivity and a lower component capacitance. Finally, as shown in Figure 2D, the inverse photoresist is removed. A cap oxide layer 29 is deposited on the trench layer 26 and has a thickness of about 1000 to 1000 A to complete the manufacturing method of the metal dielectric layer in the present invention. Therefore, the features of the present invention One is to provide a method for manufacturing a semiconductor device with a high thermal conductivity layer having a low dielectric constant.
(对先間讀背而之注意事項再功寫本頁；I -裝_ 訂 1 J|) Ψ K 1¾ % UK1 ( ('NS ) A4iUt f 210Χ 297^ϊΤ "' r P4326 1 3 Λ7 3 6 8 6 twf . doc / Ο Ο 8 B7 五、發明说明（么） 物或氫三氧矽甲烷以得到平坦之內金屬介電層，不需以化 學機械硏磨法來得到較佳的平坦化。 .本I發明的特徵之二是避免以乾蝕刻法作回蝕刻時在晶 片表面形成副產物的高分子化合物，導致可靠度的問題。 本發明的特徵之三是利用反調光阻作爲離子植入罩 幕，並進行氮氣離子植入以使得內金屬介電層具有較高之 垂直熱導與元件電容値。 綜上所述，雖然本發明已以一較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者，在不脫離 本發明之精神和範圍內，當可作各種之更動與潤飾，因此 本p明之保護範圍當視後附之申請專利範圍所界定者爲 準。 J ·3ΪΤ. n - - Ί (詞先閱讀背而之注意事項再楨寫本頁) "、.;r-:''r 屮吹"''"d.··-1·^·於合 0"印；^ 8 本_紙张尺度进州十ΚΡϋΆ.今(ΓΝί；)Λ4^^(210Χ 297&|)(Notes for the first reading and writing this page; I-book_order 1 J |) Ψ K 1¾% UK1 (('NS) A4iUt f 210Χ 297 ^ ϊΤ "' r P4326 1 3 Λ7 3 6 8 6 twf. Doc / 〇 〇 8 B7 V. Description of the invention (H) or hydrogen trioxosilane to obtain a flat inner metal dielectric layer, no chemical mechanical honing method is needed to obtain better planarization The second feature of the present invention is to avoid the formation of high-molecular compounds that are by-products on the surface of the wafer when dry etching is used to etch back, which causes a problem of reliability. The third feature of the present invention is the use of inverse photoresist as the ion The mask is implanted, and nitrogen ion implantation is performed so that the inner metal dielectric layer has a higher vertical thermal conductivity and element capacitance. In summary, although the present invention has been disclosed above in a preferred embodiment, it is It is not intended to limit the invention. Any person skilled in the art can make various modifications and retouching without departing from the spirit and scope of the invention. Therefore, the scope of protection of this patent shall be defined by the scope of the attached patent Whichever prevails. J · 3ΪΤ. N--词 (read the words first and pay attention (I will write this page again) "、.; R-: `` r 屮 吹 " '' " d. ·· -1 · ^ · 于 合 0 "印; ^ 8 copies _ paper scale into the state十 ΚΡϋΆ. 今 (ΓΝί;) Λ4 ^^ (210Χ 297 & |)