TW459370B - Method to manufacture MIM capacitor by dual damascene process - Google Patents

Abstract

The present invention is a method to manufacture MIM capacitor, which can be matched with dual damascene process. First, form metal layer/dielectric layer/metal layer capacitor in the interconnect dielectric layer, then use dual damascene etching process to complete the electrode connection of interconnection, dielectric layer and the top electrode of the capacitor.

Description

459 37 〇 5. Description of the invention (i) I Field of invention: The present invention relates to semiconductor processes, especially a process capable of cooperating with dual damascene to manufacture metal layer / dielectric layer / metal layer (MI) capacitors. Method. Background of the invention: In addition to the goal of the integrated circuit manufacturing process, in addition to making the volume of the components in the chip small in order to achieve high density, high yield and reduce unit cost, other performance of the component is more critical, such as the speed of the component which performed. However, as the size of components! Shrinks, as the components become denser, the metal wires connecting subsequent components will become thinner, which will increase the resistance value and become unfavorable for its speed I performance. In addition, the internal connection The dielectric constant of the metal layer and even the dielectric layer between interconnects is an important factor in the speed performance of the device. This is because the resistance value R of the wire has a capacitance between the upper and lower wires and adjacent wires of the same layer ( : Exist, as everyone familiar with the related technology knows, the lower the RC value is, the lower the time delay and the faster the response speed. | Therefore, the industry is always developing low-value metal wires and low dielectrics. I work hard with the dielectric layer between the interconnects within the constant I. At present, there are reports on the use of copper instead of aluminum in the interconnects. For example, I BM declared in 1977; Explains the arrival of the copper process era. In addition to reducing the resistance value and enhancing the speed of the copper process, copper wires have been researched on the problem of electromigration.

Page 4 4 59 37 0 5. Description of the invention (2) The report confirms that it is smaller than the aluminum wire. Therefore, the wire resistance value has already been solved for many temporary periods. And low-k dielectric layer products have been successfully developed, for example, Shen Jixi by chemical vapor deposition method _ _k, Ά ^ i〇wk W ^ and so on, each product has its own Pros and cons, so most of the major brands / Ulr, Hοsp τ conductor factories are # 4- ^ 〇3 its prestige Man coral or low-k ..., diamonds, objects of high-order deposition of red-painted method Complementary metal-oxide-semiconductor (CMOS) logic circuits> Processes of m or below 'have begun to use copper as a dual-inlay material / · 11 ΐ ~ Shou', which is bound to become a future development trend. In addition, the embedded "embedded DR AM) DRA M technology 'combines advanced DRAM parts and logic mines: it is a high-performance " system and DRA M memory cells on the same chip11 (system- The high-end technology of on-chip) is also a current and future trend. i

I | However, most of the current DRAM manufacturing capacitors are manufactured before the first-stage metal interconnects are manufactured. However, when the DRAM memory cell part is manufactured together with the logic circuit, there is a problem that the height of the DRAM area is larger than that of the logic network area. The reason is nothing else, mainly from the f = degrees of electricity produced in the DRAM area. High terrain DRAM areas will cause high-aspect-ratio problems in the contact holes of the logic circuit area. > In order to solve the above-mentioned problem, the conventional embedded DRAM technology will increase the cost, and a more complicated process is needed. In this way, it will be better with 459370 V. Description of the invention (3) The dilemma of limited rate improvement is because the conditions that can be improved by high aspect ratio contact holes are really limited. Unfortunately, the currently known manufacturing methods still do not have a 3-D capacitor manufacturing process that can be used with copper dual inlays, so the conventional technology is no longer sufficient. In view of the facts described above, the present invention will provide a vertical 3-D capacitor capacitor manufacturing method. This manufacturing method can completely match the copper dual damascene process technology of embedded DRAM. Therefore, for the conventional technology, The trouble caused by high aspect ratio contact holes can also be eliminated. OBJECTS AND SUMMARY OF THE INVENTION The purpose of the present invention is to solve the problem of high aspect ratio of the contact holes in the logic area caused by the height of the capacitor during the manufacturing process of the conventional embedded DRAM memory cell. Another object of the present invention is to provide a vertical 3-D capacitor capacitor manufacturing method, which can be completely matched with the copper dual damascene process technology. The invention discloses a method in which a metal layer / dielectric layer / metal layer (M IM) capacitor is first formed between interconnect dielectric layers by a damascene process, and then the interconnect, dielectric layer and Capacitor top electrode connection. This issue 4 59 37 0 V. Description of the invention (4) The first form, the second figure, the first, and the second hindering form a clear connection, forming one. Upper shape and midline again. The guide plate is formed into a gold layer on the upper canal, the groove is shaped and the back-end supply line layer is finally electrically conductive. Yixian belongs to the first deposit of deposit money, one layer at a time: first, the first electricity, which is less than the step from the first step to the lower layer of the second layer. The first layer of the first layer, the second layer, the second layer, the first layer, the second layer, the first layer, and the second layer were engraved in the Ming Yicheng re-etching case. Next, an etching technique was applied to etch the second etch stop layer to form an opening and etch the second A dielectric layer to form a capacitor trench with the first photoresist pattern as a mask; the first photoresist pattern is removed; and then, the second dielectric layer is etched through the opening so that the second dielectric layer faces both sides of the opening The edge is retracted to expand: the surface area of the large-capacity trench; the first etch stop layer exposed at the bottom of the capacitance trench is removed; and then a first conductor layer is formed at the bottom of the capacitance trench, the side wall, the opening sidewall, and the capacitance trench On shore ("W" on the shore of the capacitor trench described herein refers to the surface of the dielectric layer on both sides of the upper edge of the capacitor trench); and then, a protective layer is formed in the capacitor trench to protect the first conductor layer, As the bottom electrode. Subsequently, an etching technique is applied to etch the first conductive layer on the bank of the capacitor trench and the side wall I of the opening, and the first conductive layer in the capacitor trench is used as the bottom electrode; the protective layer is removed, and a capacitor dielectric layer is formed on The bottom electrode and the capacitor trench are formed; a second conductor layer is formed to fill the capacitor trench; after that, a chemical / mechanical polishing process is performed, and the second etching stop layer is used as a polishing stop layer; and a third dielectric is formed. Layer on the second etch stop layer; 459 37 〇 Ⅴ. Description of the invention (5) a hard mask layer is formed on the third dielectric layer; then, a second photoresist pattern is formed on the hard mask layer To define the mesoscopic hole. Then transfer the second photoresist pattern to the hard mask layer; remove the second photoresist pattern and use the hard mask as the mask to etch the third dielectric layer, the second etch stop layer, and the second dielectric layer ' Stopping on the first etch stop layer to form a via hole; forming a third photoresist pattern on the hard mask layer to define a wire channel; subsequently, the third dielectric layer is stopped on the first layer On the stop layer, a first etch stop layer in the via hole is simultaneously touched to expose the metal wires. Then the third photoresist pattern is removed; subsequently, a metal barrier layer is formed on all of the vias and the lead trenches: the surface; finally, the vias and the lead trenches are backfilled with copper metal; and a chemical mechanical polishing process is applied to the The third dielectric layer is a polishing stop layer. Detailed description of the invention: Please refer to the schematic cross-sectional view shown in FIG. First, a substrate with a component (not shown) is provided, and a first dielectric layer 110 is coated thereon. In addition, a lead 105, such as a copper lead, is buried in the first dielectric layer 1 10. Its upper surface and the upper surface of the first dielectric layer 105 are close to the same plane.

I | Still refer to FIG. 1, and then a first etch stop layer 1 1 5 is on the first dielectric: electrical layer 1 1 0, and the first etch stop layer 1 1 5 may be a chemically assisted chemical vapor deposition method. (PECVD) deposits a Ti oxide layer (SiON) or a carbonized layer, with a thickness of about 300-600 angstroms. In order to reduce the effect of the parasitic capacitance between the i-conducting layer and the layer, the second dielectric layer 120 is further deposited. The second dielectric layer 120 is implemented with a preferred 459 37 0 5 'invention description (6) For example, it is a 10w-k dielectric layer. For example, 10 w-k black diamond deposited by chemical vapor deposition method, c 0 r a 1 or low-k SiLK, Flair, HOSP, etc. deposited by spin coating method (s p i η-ο η). Then, a second etch stop layer 1 2 5 is deposited on the second dielectric layer 1 2 0 by the same method. The second etch stop layer 1 2 5 can also be a plasma-assisted chemical vapor deposition method ( PECVD) deposits a silicon nitride layer or a silicon carbide: layer, with a thickness of about 800-1200 angstroms. Please note that the second etching stop layer 2 5 preferably has a lower etching rate than the first last stop layer 1 1 5. Therefore, in a preferred embodiment, the second last stop layer 1 2 5 is an It fossil evening layer and the first _ last minute stop layer 1 1 5 is a nitrogen oxide layer, so it can satisfy the first Second, the etch stop layer 1 2 5 requires a lower etch rate than the first etch stop layer 1 1 5.丨 In addition, the second etch stop layer 1 2 5 is thicker than the first etch stop layer 1 丨 5, which can further ensure that when the first etch stop layer 11 5 is removed, a part of the 1 second The etch stop layer 1 2 5 has not been removed. In addition, the thickness of the second dielectric layer 1 2 0 will depend on the height of the capacitor. ! i A typical range is 50 Angstroms to 12 Angstroms. Then, a photoresist pattern 130 is formed on the second etch stop layer 125 to define the position of the capacitor trench. The capacitor trench is formed in the DRAM region 126 as shown in the figure. Part of the dual damascene process will be performed at the same time as the 126 capacitors in the DRAM area and the vias in the logic circuit area and the top electrode wires in the capacitor. 1 Please refer to Figure 2. A plasma dry etching followed by a photoresist pattern as a mask

Page 9 4 59 37 〇 5 'Description of the invention (7) The second etch stop layer 1 2 5 and the second dielectric layer 1 2 0 are etched, and stop at the first etch stop layer 115. After the photoresist pattern 130 is peeled off, an isotropic etching is then performed on the second dielectric layer 120 to form a recessed portion that is enlarged toward both sides of the opening 13 5. For example, as shown in the figure, the lengths of " a1 'are retracted toward the openings 13 and 5 respectively. Taking a preferred embodiment of | i, the length of n a " is about 500 angstroms to 100 angstroms is the best. The isotropic surname engraving in this step may be the selection of an appropriate chemical button. The etchants can be dry or wet, for example, dry isotropic shoe engraving can be done with 〇 cream slurry | 丨 etchants are used in the dielectric layer material of organic L 〇w-K, and CVD dielectric layer oxide For the substrate material, fluorine-containing etching gas can be used, and wet etching can use diluted hydrofluoric acid or BOE solution. 1! Please refer to Figure 3 ’and then apply a comprehensive surname engraving method. The first etch stop layer 1 1 5 exposed through money is used to expose the metal wire 1 0 5 to connect the subsequent bottom electrode of the capacitor. The second etch stop layer 1 2 5 uses a material with a lower surname engraving rate than the first money etch stop layer 1 15 as described previously. It is thicker than the first etch stop layer 115, so it can still keep part of the second etch stop layer 125 unremoved. i! | Subsequently, the capacitor bottom electrode 1 4 0 is formed by a chemical vapor deposition method. In a preferred embodiment, the material of the capacitor bottom electrode 1 40 can be conductive | Material that is less than 450 ° C and has uniformity during chemical vapor deposition as the material of the bottom electrode 140, for example, metal materials such as TiN and TiN / W are selected. In general, the thickness of the bottom electrode is only slightly smaller than the above " a '', for example, about 300 to 600 Angstroms.

Page 10 4 5 9 37 〇 5. Description of the invention (8) Yes, the typical thickness is about 40 Angstroms. A protective material 1 4 5 is then deposited on the bottom of the capacitor trench j electrode 1 40 and overflows onto the surface on the bank of the capacitor trench. The protective material 1 4 5 is used to protect the bottom electrode 1 40 in the capacitor trench, and is etched by subsequent i 丨 etching steps. Therefore, a photoresist that can be formed by spin coating, an anti-reflection coating at the bottom, or other organic materials that can be formed by spin coating can be used. Etching is then performed one after the other to etch back the protective material 1 4 5 so that only the protective material 1 4 5 remains in the capacitor trench. If the protective material 1 4 5 is a photoresist material, such as a positive photoresist, then a low-energy partial exposure method can also be used. In this way, only the upper protective material 1 4 5 is developed, so it can be developed. It is easy to remove. In addition, the height of the protective material 1 4 5 remaining in the capacitor trench is not critical, as long as it can cover the inner wall of the capacitor trench and the bottom electrode at the bottom, and expose the bottom of the capacitor trench bank.

I electrode is sufficient. Please refer to the cross-sectional diagram shown in Figure 4, and then use protective material 14 5 to protect the bottom electrode in the capacitor trench, and apply an anisotropic etching technique to remove the upper surface of the capacitor trench bank and the second etching stop The layer 125 is a bottom electrode material on the side wall of the opening. In order to ensure that the bottom electrode material of the opening side wall is removed to achieve the effect of separating the bottom electrode and the top electrode. Immediately after the protective material 1 4 5 is removed, a high dielectric constant

Page 11 459 37 0 j --------——- 丨 V. Description of the invention (9) A dielectric layer 1 50 is then deposited on the bottom electrode in the capacitor trench as a capacitor dielectric layer. In a preferred embodiment, the dielectric layer 1 50 is preferably selected: one suitable for uniform deposition during chemical vapor deposition and suitable for low temperature material deposition, such as Ta 20 as an example. . The thickness of the dielectric layer 150 is about 40-100 Angstroms.

I Subsequently, the capacitor top electrode material 1 5 is then deposited on the dielectric layer 1 50. In addition to filling the capacitor trench and spilling onto the surface of the capacitor trench bank, an etch-back or chemical / mechanical grinding process is performed to remove the top electrode material on the capacitor trench bank. The material of the capacitor top electrode can also be selected as the above-mentioned metal material of the bottom electrode 140 or other conductive materials such as a crystalline silicon layer.丨 The etch-back or chemical / mechanical polishing process uses the second etching stop layer 1 2 5 as the polishing stop layer. Therefore, the dielectric layer 150 on the bank of the capacitor trench is also removed. Please refer to the schematic diagram of the cross section shown in Figure 5. The third dielectric layer 160 is connected; deposited on the second etch stop layer 125, the material of the third dielectric layer 160 is selected as the second dielectric layer. Low_k dielectric layer can be selected, such as

I 1 learn black diamond deposited by vapor deposition method, 〇ra 1 or S i L κ, F 1 air, Η 0 S Ρ etc. deposited by spin coating method (sp 1 η-q η), one. Of course, before depositing the third dielectric layer 160, a third etch stop layer (not shown) may be deposited on the second etch stop layer 1 2 5 to protect the top electrode 1 5 5

Page 12 459370 V. Description of the invention (ίο) Erosion should be the only one before, and better than the one that is not. Or force. Injury-resistant g can be selected Inu. JJ to, "S 5 migration button Yes, the middle layer of the stop, the end of the stop, the final embedded etched etched double two or three lines first, in the second order Please refer to the schematic cross-sectional view shown in Figure 5 at a time when there is no engraving. Next, a hard i-type mask 1 6 5 is formed on the third dielectric layer 16 0, and a hard-type mask 1 6 5 is selected. From SiM or SiC. Then, a photoresist pattern (not shown) is formed. The photoresist pattern (not shown) defines a via hole | 1 6 8 in the logic circuit area 1 2 7 to connect the first layer of wires 105. First, an anisotropic etching is performed to transfer the photoresist pattern (not shown in the figure) to the hard mask. After removing the photoresist pattern, a hard mask is used

I i screen, and then perform an anisotropic etching, the third dielectric layer 160, the second etching

I i stop layer 125 and the second dielectric layer 120. Etching stops on the first etch stop layer: 1 i 5. : After that, please refer to the schematic diagram of the horizontal plane shown in FIG. 6, and use the photoresist pattern 1 5 5 as the mask, and then apply an anisotropic etching again to etch the hard mask 1 6 5 and the third dielectric layer 1 60 to form a wire trench 1 8 0 a, 1 8 0 b therein, and stop on the second etch stop layer 1 2 5 to expose the top electrode of the capacitor, and at the same time, the first of the via holes 1 6 8 The etch stop layer 1 1 5 is also etched away to expose the i metal wire 105. After removing the photoresist pattern 175, a metal barrier layer 185 is then deposited on all surfaces. The metal barrier layer 185 is selected from the group consisting of a nitride group, titanium nitride, and titanium. . Finally, copper is deposited again and filled in separately.

Page 13 4 59 37 G: V. Description of the invention (11) j 丨 Interlayer hole 1 6 8 and wire channel 1 8 0 a, 1 8 0 b ° The chemical / mechanical grinding process is used to remove the Excess copper layer, hard mask 165, and complete capacitor and dual damascene process. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; any other equivalent changes or modifications made without departing from the spirit of the present invention: It is included in the scope of patent application described below.

459370 on page 14 illustrates the preferred embodiment of the present invention briefly in the following explanatory texts with the following figures for more detailed explanation: Figure 1 shows a method of defining a DRAM area with a photoresist pattern according to the method of the present invention 丨Schematic cross-section of a capacitor. FIG. 2 is a schematic diagram of a cross-section of a second dielectric layer i in which a capacitive trench receding to the opening is formed by applying anisotropic etching and then applying isotropic etching according to the method of the present invention. j FIG. 3 is a schematic cross-sectional view of forming a bottom electrode and a protective layer inside the capacitor trench according to the method of the present invention. Figure 4 shows the formation of a capacitor dielectric layer and a top electrode according to the method of the present invention. A schematic cross-sectional view of a chemical / mechanical grinding process to remove excess metal layers on the banks of capacitor trenches. i Figure 5 is a schematic cross-sectional view of a method for forming a via hole in a logic region according to the present invention, and then defining a connection line trench with a photoresist pattern. Figure 6 shows a cross-sectional schematic diagram of forming a metal barrier layer on the interconnects according to the method of the present invention, and backfilling copper metal on the sidewalls and bottoms of trenches and vias and applying a chemical / mechanical polishing process to complete the present invention. No. comparison table: j wire 105 first dielectric layer 110 i first etch stop layer 115 second dielectric layer 120 second etch stop layer 125 DRAM area 126 j

Page 15 459370 I Schematic description of the logic circuit area 1 2 7 Opening 135 Protective material 1 4 5 Top electrode 1 5 5: Hard mask 165 Photoresist pattern 1 7 5 Metal barrier layer 1 8 5 5 6 ο pole 1 — — — 1 3 1 Electrical layer bottom case Electrical diagram Bottom Dielectric resistance Capacitance Three Photoelectric first dielectric layer hole 1 6 8 Wire trench 1 8 0 a, 1 8 0 b Copper 1 9 Ο

Page 16

Claims (1)

459 37 〇 6. Application scope 丨 1. A method for manufacturing a capacitor between interconnect metal layers, the method at least includes the following steps: I Provide a substrate, the substrate has formed a first dielectric layer on Thereon, and; a metal wire is formed therein, and the metal wire is coplanar with the first dielectric layer; I forms a first etch stop layer on the first dielectric layer and the metal wire Li; Forming a second dielectric layer on the first #etch stop layer; forming a second etch stop layer on the second dielectric layer; applying lithography and etching techniques to form a capacitor trench region on the second dielectric layer In the electrical layer, the capacitor trench region uses the first photoresist pattern as a mask to etch the i-second etch stop layer to form an opening formed as an opening, and the width of the opening is smaller than the capacitor trench in the second dielectric layer. The width of the capacitor trench, and the bottom of the capacitor trench and the bottom of the capacitor trench are connected to the metal wire under the first etch stop layer; i forming a first conductor layer on the bottom of the capacitor trench, the sidewall, the opening sidewall and the bank of the capacitor trench; Page 17 459370 6. Scope of patent application Grind the stop layer to complete the capacitor top electrode. II j: 2 The method according to item 1 of the scope of patent application, wherein the step of forming the capacitor trench region at least includes: forming a first photoresist pattern on the second etch stop layer to define the I capacitor trench region; Anisotropic etching is used to etch the second etch stop layer to form an I opening and etch the second dielectric layer to form a capacitor trench. The first photoresist pattern is used as a mask. The first light is removed. Resist pattern; isotropically etch the second dielectric layer through the opening, so that the second i dielectric layer recedes to both sides of the opening to expand the surface area of the capacitor trench; and etch through the bottom of the capacitor trench The exposed first etch stop layer. ; 3. The method according to item 2 of the scope of patent application, wherein the above-mentioned isotropic surname is engraved so that the second dielectric layer recedes to about 50 angstroms to 1,000 angstroms toward both sides of the opening. 4. The method according to item 1 of the scope of patent application, wherein the thickness of the first etching stop layer is about 300-600 angstroms, and is one selected from the group consisting of silicon nitride oxide or S 1 C; I 5. The method according to item 1 of the scope of patent application, wherein the above-mentioned second etching ends Page 丨 8 4 59 37 Ο i π --- VI. Scope of patent application The thickness of the stop layer is about 800-120 Angstroms, and it is one of the silicon nitride layer or Si C layer. 6. The method according to item 1 of the scope of patent application, wherein the first dielectric layer and the second dielectric layer are 10wk dielectric layers and are selected from low-k black deposited by chemical vapor deposition. Diamond, coral or low-k SiLK, Flair, HOSP etc. deposited by spin-on method. 7. The method according to item 1 of the patent application scope, wherein the protective layer is one of photoresist formed by spin coating, bottom anti-reflection coating, or organic coating formed by spin coating. 8 · The method of item 1 of the scope of patent application, after applying the chemical / mechanical grinding process, further includes a wire forming a via to connect the logic region, and a wire trench to connect the top electrode of the capacitor. j 9. The method according to item 8 of the scope of patent application, wherein the above-mentioned formation of a via hole: a wire connecting the logic region and a wire trench connecting the top electrode of the capacitor includes at least the following steps: forming a third dielectric layer On the second etch stop layer;! Forming a hard mask layer on the third dielectric layer; i forming a second photoresist pattern on the hard mask layer to define a via hole; transferring the second A photoresist pattern to the hard mask curtain layer; Page 19 4 5 9 37 0: Sixth, the scope of patent application for removing the second photoresist pattern; | Using the hard mask as a mask, etching the third dielectric layer, the second etch stop layer, the second A dielectric layer is stopped on the first etch stop layer i to form a dielectric hole; a third photoresist pattern is formed on the hard mask layer to define a wire channel; the third dielectric layer is engraved to stop On the first button stop layer, and simultaneously engraving the first etch stop layer in the via hole to expose the metal wire; removing the third photoresist pattern; forming a metal barrier layer on the via hole and All surfaces of the lead trench; backfill the via hole and the lead trench with copper metal; and a process of chemical / mechanical polishing using the third dielectric layer as a polishing: stop layer. 10. The method of item 9 in the scope of patent application, wherein the hard mask I layer is a silicon nitride layer or silicon carbide. ll, as in the method of claim 9 of the scope of patent application, wherein the above-mentioned metal barrier, the layer is selected from the group consisting of titanium nitride and titanium. I 1 2. —A method for simultaneously manufacturing capacitors using a dual damascene process, which at least includes the following steps: 'Provide a substrate on which a first dielectric layer has been formed, and Page 20 459370 6. The scope of the patent application metal wire is formed in it; a first stop layer, a second dielectric layer, and a second stop layer are sequentially formed on the first dielectric layer and the metal conductive layer. Online;! Forming a second etch stop layer on the second dielectric layer; and applying lithography and etching techniques to form a capacitor trench region in the second dielectric layer, wherein the capacitor trench region starts with the first The photoresist pattern is a mask to etch the second etch stop layer to form an opening formed as an opening, and the width of the opening is smaller than that; the width of the capacitor trench region in the second dielectric layer, and the capacitor trench in the capacitor trench region The bottom is connected to the metal wire under the first silver etch stop layer; 丨 forming a first conductor layer on the bottom of the capacitor trench, the sidewall, the opening sidewall and the bank of the capacitor trench; forming a protective layer in the capacitor trench to protect the capacitor trench The first conductor layer is used as the bottom electrode; i is an etching technique to etch the first conductor layer on the bank of the capacitor trench and the side wall of the opening, and the first conductor layer in the capacitor trench serves as the bottom electrode I t Removing the protective layer; forming a capacitor dielectric layer on the bottom electrode and the bank of the capacitor trench; forming a second conductor layer to fill the capacitor trench; applying a chemical / mechanical polishing process to the second etching The stop layer is a grinding stop layer; 1 a third dielectric layer is formed on the second etch stop layer; a hard Qin curtain layer is formed on the third dielectric layer; a via hole and a wire trench are applied; Double damascene etch, in which the interlayer hole Page 21 4 59 37 0 6. The patent application scope is a wire connected to the logic area, at least one of the wire trench is connected to the top electrode; a second photoresist pattern is formed on the hard mask layer to define a via hole; transfer The second photoresist pattern to the hard mask layer; removing the second photoresist pattern; using the hard Qin curtain as a mask, etching the third dielectric layer, the second etch stop layer, and the second dielectric Layer to stop on the first I etch stop layer to form a via hole; to form a third photoresist pattern on the hard mask layer to define a wire channel; I etch the third dielectric layer to stop On the first engraved termination layer, and simultaneously engraving the first engraved termination layer in the via hole to expose the metal wire; removing the third photoresist pattern; forming a metal barrier layer on the via hole And all surfaces of the lead trench; backfilling the via hole and the lead trench with copper metal; and performing a chemical / mechanical polishing process using the third dielectric layer as a polishing stop layer. 13. The method according to item 12 of the scope of patent application, wherein the step of forming a capacitor trench region in the second dielectric layer at least includes: forming a first photoresist pattern on the second etch stop layer, To define the capacitor trench area, Page 22 ^ -59 37 0 I. Application scope: Applying non-isotropic etching technology to etch the second etch stop layer to form an opening and etch the second dielectric layer to form a capacitor trench. A photoresist pattern is a mask; the first photoresist pattern is removed; the second dielectric layer is isotropically etched through the opening so that the second: the dielectric layer recedes to both sides of the opening to expand the capacitor The surface area of the trench; k I; etched through the first etch stop layer exposed at the bottom of the capacitor trench. 14. The method according to item 13 of the scope of patent application, wherein the thickness of the first etch stop layer is about 300-600 angstroms, and is selected from a silicon nitride oxide layer, or SiC, which makes- 0: 1 5. The method according to item 13 of the scope of patent application, wherein the thickness of the second etching stop layer is about 8 0 0-1 2 0 0 angstroms, and is selected from a silicon nitride layer or an S 1 C layer. I 1 is one of them. 1 1 6. The method according to item 13 of the scope of patent application, wherein the second dielectric layer, the second dielectric layer, and the second dielectric layer are a low-k dielectric layer and are selected from chemical gas One of iW-k black diamonds, cora, or low-k SiLK, Flair, HOSP, etc. deposited by a spin-on method using phase deposition. Page 23