經濟部智慧財產局員工消費合作社印製 546758 Α7 44 5 3 twf.doc/0 08 07 五、發明説明（丨） 本發明是有關於一種具有低介電係數介電層的製作方 法，且特別是有關於一種具有空氣間隙之介電層的製作方 法。 隨著半導體元件的線寬不斷地縮小，金屬線與金屬線 間的距離也越來越短’導致寄生電容（parasitic Capacitor) 的現象越來越嚴重，因此內金屬介電層（Inte卜Metal Dielectrics，IMD)之介電係數(Dielectric Constant)大小對 於兀件操作速率的影響也跟著越來越大。介電層的介電係 數和寄生電容时關係爲，介電層的介電係數越大，寄生電 容越大，導致 RC 時間延遲（Resistance Capacitance Time Delay ; RC delay)的問題更形嚴重，因而降低電路傳輸速 度。因此希望可藉由降低介電層的介電係數，而降低RC 時間延遲，以增進元件的操作速度。 但習知使用低介電係數材料爲介電層時，常常因爲介 電係數不夠低而無法有效降低金屬線間的寄生電容。或於 後糸買金屬化製程中，由於低介電係數材料的吸濕性，使得 低介電係數材料內部含有水氣，造成後續在形成金屬插塞 曰寸’產生毒化（Poison)的現象。 因此本發明提供一種具有空氣間隙之介電層的製作方 法’以形成具有低介電係數的介電層。該方法包括依序形 成金屬層和圖案化之罩幕層於基底上，然後以圖案化之罩 幕層爲罩幕，對金屬層進行蝕刻步驟，例如用反應性離子 倉虫d法’使卓幕層在金屬層之上朗周緣造成突出。再沈積 介電層於罩幕層之上，使其因罩幕層在金屬層的上端周緣 L---^--------- (請先閲讀背面之注意事項再填寫本頁) 訂 ( CNS ) Μ規格(2Η);ϋ) 546758 A7 B7 44 53 twf.doc/008 五、發明説明（7) 突出，於介電層中形成空氣間隙。 (請先閱讀背面之注意事項再填寫本頁) 依據本發明的方法，因爲罩幕層在金屬層的上端周緣 具有突出，使得介電層在沈積時階梯覆蓋性變差，因此極 易在介電層中造成空氣間隙，而空氣的介電係數又低，可 使介電層在材質不變的情況下，即可達成低介電係數材料 的優點。亦即可避免間距較小的金屬線之間產生寄生電 容，以降低RC時間延遲，增進元件的操作速率。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特·舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A - 1C圖是繪示依照本發明較佳實施例的一種具 有空氣間隙介電層的製作流程剖面圖。 圖式之標記說明： 經濟部智慧財產局員工消費合作社印製 100 :基底 no :金屬層 115 :金屬導線 120 :罩幕層 125 :突出 130 :開口 140 :介電層 145 :空氣間隙 實施例 請參照第1A - 1C圖，其係繪示依照本發明較佳實施 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 546758 A7 B7 44 5 3twr.doc/〇〇8 五、發明説明（％ ) 例的一種具有空氣間隙介電層的製作流程剖面圖。 請參照第1A圖，依序形成金屬層110和圖案化之罩 幕層120於基底100上。金屬層110的材質例如可爲鋁合 金、金屬銅等等，而其形成的方法包括物理氣相沈積法或 化學氣相沈積法。圖案化罩幕層120的材質，例如可爲氧 化砂’其形成的方法包括先以化學氣相沈積法沈積完整的 胃胃J1 ’再:以微影蝕刻法將其圖案化。 請參照第1B圖，以圖案化之罩幕層120爲罩幕，對 金屬層110進行蝕刻步驟，以形成金屬導線115，而金屬 導線之間則形成溝渠開口 130。在此之結構特徵爲罩幕層 120在金屬導線115之上端周緣具有突出I25的部份，好 像金屬導線115之屋簷。而在此蝕刻的方法，例如可用反 應性離子蝕刻法，利用電漿內反應性離子和金屬層110表 應、β等向性蝕刻機制，同時又有離子向下撞擊之非等 向性触刻機制，以形成第1Β圖的金屬導線115結構。 請參照第1C圖，再沈積介電層140於罩幕層120之 上以及開口 130之中。在此因罩幕層120在金屬導線115 之上端周緣具有突出I25，使得在沈積介電層14〇時之階 梯覆盖能力變差，因此於開口 130內之介電層140中形成 空氣間隙141。如此一來，因爲空氣的介電係數很低，使 得整個介電層140的等效介電係數亦變低。 由上述本發明較佳實施例可知，應用本發明具有降低 介電層介電係數之優點，此乃因爲介電層中產生空氣間隙 之故。如此一來，即可避免間距較小的金屬線之間產生寄 ,-I^------Φ------1T------#1 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Μ規格（21〇χ297公釐） 1 546758 A7 4453tvv t'.doc/008 B7 五、發明説明（ψ ) 生電容，以降低RC時間延遲，增進元件的操作速率。 雖然本發明已以較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作各種之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐）Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 546758 Α7 44 5 3 twf.doc / 0 08 07 V. Description of the Invention (丨) The present invention relates to a method for manufacturing a dielectric layer with a low dielectric constant, and particularly The invention relates to a method for manufacturing a dielectric layer having an air gap. As the line width of semiconductor devices continues to shrink, the distance between metal lines and metal lines is getting shorter and shorter, which leads to the phenomenon of parasitic capacitance becoming more and more serious, so the inner metal dielectric layer (Inte and Metal Dielectrics , IMD) the influence of the dielectric constant (Dielectric Constant) on the operating speed of the element is also increasing. The relationship between the dielectric constant of the dielectric layer and the parasitic capacitance is that the larger the dielectric constant of the dielectric layer, the larger the parasitic capacitance, resulting in a more serious problem of the RC time delay (RC delay). Circuit transmission speed. Therefore, it is hoped that the RC time delay can be reduced by reducing the dielectric constant of the dielectric layer to improve the operation speed of the device. However, when it is known to use a low dielectric constant material as the dielectric layer, the parasitic capacitance between metal lines cannot be effectively reduced because the dielectric constant is not low enough. Or in the metallization process of Houyi, due to the hygroscopicity of the low-dielectric-constant material, the low-dielectric-constant material contains moisture inside, which causes subsequent poisoning in the formation of metal plugs. Therefore, the present invention provides a method of making a dielectric layer having an air gap 'to form a dielectric layer having a low dielectric constant. The method includes sequentially forming a metal layer and a patterned mask layer on a substrate, and then using the patterned mask layer as a mask, performing an etching step on the metal layer, for example, by using a reactive ion worm method. The curtain layer protrudes on the peripheral edge of the metal layer. Then deposit a dielectric layer on the mask layer, so that the mask layer is on the upper edge of the metal layer L --- ^ --------- (Please read the precautions on the back before filling this page ) (CNS) M specifications (2Η); ϋ) 546758 A7 B7 44 53 twf.doc / 008 5. Description of the invention (7) Protruded, forming an air gap in the dielectric layer. (Please read the precautions on the back before filling this page.) According to the method of the present invention, because the mask layer has protrusions on the upper peripheral edge of the metal layer, the step coverage of the dielectric layer during deposition is poor, so it is extremely easy to An air gap is caused in the electrical layer, and the dielectric constant of the air is low, so that the dielectric layer can achieve the advantages of a low dielectric constant material without changing the material. In other words, parasitic capacitance can be avoided between the metal wires with a small pitch, so as to reduce the RC time delay and increase the operation speed of the device. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes in detail the preferred embodiments and the accompanying drawings, as follows: Brief description of the drawings: Section 1A- FIG. 1C is a cross-sectional view illustrating a manufacturing process of an air gap dielectric layer according to a preferred embodiment of the present invention. Description of the symbols of the drawings: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 100: substrate no: metal layer 115: metal wire 120: cover layer 125: protrusion 130: opening 140: dielectric layer 145: air gap Refer to Figures 1A-1C, which shows the preferred implementation in accordance with the present invention. 4 The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 546758 A7 B7 44 5 3twr.doc / 〇〇8 5 2. A cross-sectional view of the manufacturing process of the invention description (%) example with an air gap dielectric layer. Referring to FIG. 1A, a metal layer 110 and a patterned mask layer 120 are sequentially formed on the substrate 100. The material of the metal layer 110 may be, for example, aluminum alloy, metal copper, or the like, and a method for forming the metal layer 110 includes a physical vapor deposition method or a chemical vapor deposition method. The material of the patterned mask layer 120 may be, for example, oxidized sand. The method of forming the patterned mask layer 120 includes firstly depositing a complete stomach and stomach J1 ′ by chemical vapor deposition, and then patterning it by lithographic etching. Referring to FIG. 1B, the patterned mask layer 120 is used as a mask, and the metal layer 110 is etched to form metal wires 115, and trench openings 130 are formed between the metal wires. The structural feature here is that the cover layer 120 has a portion protruding I25 on the periphery of the upper end of the metal wire 115, like the eaves of the metal wire 115. In this etching method, for example, a reactive ion etching method can be used, which utilizes reactive ions in the plasma and the surface of the metal layer 110, β isotropic etching mechanism, and at the same time, there is an anisotropic etching where the ions strike down Mechanism to form the metal wire 115 structure of FIG. 1B. Referring to FIG. 1C, a dielectric layer 140 is further deposited on the mask layer 120 and in the opening 130. Here, because the mask layer 120 has a protrusion I25 on the periphery of the upper end of the metal wire 115, the step coverage ability at the time of depositing the dielectric layer 140 is deteriorated, so an air gap 141 is formed in the dielectric layer 140 in the opening 130. In this way, because the dielectric constant of air is very low, the equivalent dielectric constant of the entire dielectric layer 140 also becomes low. It can be known from the above-mentioned preferred embodiments of the present invention that the application of the present invention has the advantage of reducing the dielectric constant of the dielectric layer because air gaps are generated in the dielectric layer. In this way, you can avoid sending between the metal wires with a small pitch, -I ^ ------ Φ ------ 1T ------ # 1 (Please read the note on the back first Please fill in this page for further information.) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The paper size is applicable to Chinese National Standards (CNS) M specifications (21 × 297 mm). (Ψ) to generate a capacitor to reduce the RC time delay and increase the operating speed of the component. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy