4950twf.doc/008 408441 A7 B7 五、發明說明（ί ) 本發明是有關於一種半導體之製造方法，且特別是有關 於一種多重內連線之製造方法。 現今的積體電路元件’除包括在半導體基底上形成的場 效電晶體(FET)與雙極兀件(bipolar device)外，更包括在元 件上形成的的多重內連線結構（multilevel interconnect structure)。藉由多重內連線結構可連接基底上不同的元 件。在諸多的積體電路中，多重內連線結構以一或多陣列 導線且以平行的方式延伸，而在高集積度堆疊彤成的元件 中提供導線的功能。而在窄小的空間中，平行的導線會在 相鄰接的導線間產生不、必要的電容式(capacitive)與電感式 (inductive)耦接（coupling)，特別是在經由平行導線進行較 高的傳輸資料速率時。當元件尺寸縮小時，導線間電容値 (intra-metal capacitance)將明顯增加]。電容式與電感式耦揆 將降低資料的傳輸速率，而以此方式增加能量的耗損量， 同時亦限制了元件的效能。 請參照第1圖，爲降低多重內連線之間電容式與電感式 耦接，因此在導線1〇2之間的介電層104中形成空氣間隙 (air gap)106。由於空氣之介電常數較小（約爲1)，因此， 以空氣間隙做爲多重內連線之間的內金屬介電材質，可以 降低平行的導線間的介電常數以及平行導線間之電容，並 提高資料傳輸速率以及元件效能。 然而，當形成介層窗口 U2發生對準失誤時或是未接著 型（inlanded)介層窗口（未繪示）之關鍵尺寸（critical dimension，CD)偏大時，由於介電層110、108與HM之材 質相似，所以在形成介層窗口 Π2時不易控制蝕刻終點， 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本-!) ^//¾.-------- 訂-------！線、 經濟部智慧財產局員工消費合作杜印製 408441 A7 B7 4950twf.doc/008 五、發明說明（v) 介層齒口 II2容易穿透介電層110、i〇8與1〇1，並打鬥你 氣間隙106，形成連通介層窗口 112與空氣間隙1〇6之門 的開口 106a。而於介電層110上以及介層窗口 112中以化 學氣相沉積法（chemical vapor deposition，CVD)形成阻障 層(ban:ierlayer)ii4時，阻障層1U不易塡入空氣間隙ι〇6 中’因此在後續形成鎢插塞（未繪示）時，反應氣體六氣化 鎢（WFe)擴散進入空氣間隙1〇6，與介電.層1〇4中所^之 氧化物進行反應，造成介層窗毒化(poison via)的現象^ 因此本發明就是在提供一種多重內連線之形成方法，其 方法簡述如下：於基底上形成一第一導線與一第二導線Y 並且於第一與第二導線之間裸露部分基底。接著，於^底 與第一與第二導線'上形成一層第一介電層，其中在第—介 電層、第一與第二導線所界定的區域形成一空氣間隙。續 之，於空氣間隙上方之第一介電層上，形成一抗蝕刻層。 之後’於抗蝕刻層與第一介電層上，形成一層第二介電 層。繼之，以抗蝕刻層爲罩幕，形成裸露第一導線之介層 窗開口。接著，於介層窗開口之側壁以及介層窗開口所裸 露之第一導線之表面上，形成一層阻障層。最後，於介層 窗開口中’形成介層窗插塞’且介層窗插塞塡滿介層窗 口。其中，抗蝕刻層係爲絕緣材質，其較佳的包括氮化矽、 氧化鈦或是氧化鉬，且抗蝕刻層對於第一介電層以及第二 介電層有較大的蝕刻選擇比再者，在進行化學機械硏磨 製程時，抗蝕刻層之硏磨率較第一介電層低。 ,由於抗蝕刻層對於第一介電層與第二介電層具有較大 的蝕刻選擇比，因此在形成介層窗口發生對準失誤時，可 (請先閲讀背面之注意事項再填寫本頁) n I n I 1 1 訂---------線、 經濟部智慧財產局員工消費合作杜印製 1 本紙張尺度適用中國國家標準（CNS)A4規格（21。x 297公楚） 經濟部智慧財產局員工消費合作社印製 408441 A7 4950i\vf.doc/008 五、發明說明（>) 以抗蝕刻層爲罩幕，則介層窗口不會穿透空氣間隙上方之 第一介電層，而開啓空氣間隙。所以可以解決習知因介層 窗口開啓空氣間隙，造成介層窗毒化等問題。 爲讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖係顯示習知形成介層窗口對準失誤，以至於介層 窗口穿透電層，並連通空氣間隙之剖面簡圖； 第2A圖至第2E圖係顯示根據本發明較佳實施例之一種 形成多重內連線之方法；以及 第3圖係顯示當形成介層窗口發生對準失誤時之剖面簡 圖。 其中，各圖標號與構件名稱之關係如下： 100，200 :基底 102 :圖案化導電層 104，，108，110，204，208，210，211 :介電層 106，206 :空氣間隙 112，212，312 :介層窗開口 112a，212a，312a :介層窗插塞 114，214，314 :阻障層 202a，202b :導線 207，207a :抗蝕刻層 實施例 第2A圖至第2E圖係顯示根據本發明較佳實施例之一種 5 木紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ! (諳先閱讀背面之注意事項再填寫本頁) /裝--------訂----- 線' 408441 A7 B7 4950twf.doc/008 五、發明說明) 形成多重內連線之方法。 請參照第2A圖，首先’提供一基底200，基底200中 已形成有半導體元件(未繪示）。接著於基底200上形成導 線 2〇2a、2〇2b 與 2〇2c ’ 此導線 2〇2a、2〇2b 與 2〇2c 係做 爲元件之導線結構。續之，於基底200與導線2〇2a、202b 與202c上形成一層介電層204 ’且介電層2〇4於導線 202a、202b與202c之間之空間（space)形成空氣間隙2〇6。 其中’介電層2〇4可以是一階梯覆蓋性較差之介電層，較 佳的是以電黎加強型化學氣相沉積法（plasma-enhanced chemical vapor deposition，PEC VD)所形成之氧化矽層，且 其於導線202a、2〇2b與2〇2c上之厚度約介於2〇〇〇到4000 埃之間，較佳的厚度約爲3000埃。利用介電層204之材 質爲階梯覆蓋性較差之材質，在導線202a、202b與202c 之間的空間中塡滿介電層204時，會在導線202a、202b 與202c之間的空間上方，先形成懸突結構，導致後續沉積 之電層204之材質不易塡入圖案化導電層之間的空間，並 在形成介電層2〇4過程中，彼此連結，以在導線202a、202b 與202c之間的空間中形成空氣間隙206。 請參照第2B圖，之後，於介電層204上方形成一層抗 蝕刻層207。其中，抗蝕刻層207對於介電層2〇4具有較 大的蝕刻選擇比，且在進行化學機械硏磨製程時，抗蝕刻 層207之硏磨率較介電層204低，而抗蝕刻層2〇7係在低 溫(約攝氏500度以下）形成，較佳的是以電漿加強型化學 氣相沉積法或是光子產生型化學氣相沉積法（Photo-induced chemical vapor deposition ， PICVD) 所形成之氣化 6 (請先閲讀背面之注意事項再填寫本頁)4950twf.doc / 008 408441 A7 B7 V. Description of the Invention The invention relates to a method for manufacturing a semiconductor, and more particularly to a method for manufacturing multiple interconnects. Today's integrated circuit elements include field-effect transistors (FETs) and bipolar devices formed on semiconductor substrates, and multilevel interconnect structures formed on the elements. ). Multiple interconnects can connect different components on the substrate. In many integrated circuits, multiple interconnect structures extend in parallel with one or more arrays of wires, and provide the function of wires in highly integrated components. In a narrow space, parallel wires will cause unnecessary and capacitive coupling between adjacent wires, especially when parallel wires are used for higher coupling. Data rate. As component size shrinks, the intra-metal capacitance 値 (intra-metal capacitance) will increase significantly]. Capacitive and inductive coupling will reduce the data transmission rate, increase the energy consumption in this way, and also limit the performance of the component. Referring to FIG. 1, in order to reduce the capacitive and inductive coupling between multiple interconnects, an air gap 106 is formed in the dielectric layer 104 between the wires 102. Because the dielectric constant of air is small (about 1), using air gap as the inner metal dielectric material between multiple interconnects can reduce the dielectric constant between parallel wires and the capacitance between parallel wires , And improve data transfer rates and component performance. However, when the alignment window U2 is misaligned or the critical dimension (CD) of an inland interlayer window (not shown) is too large, the dielectric layers 110, 108 and The material of HM is similar, so it is not easy to control the etching end point when forming the interlayer window Π2. 3 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this- !) ^ // ¾ .-------- Order -------! Line, Consumer Cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs, printed 408441 A7 B7 4950twf.doc / 008 V. Description of the invention (v) The interlayer tooth gap II2 easily penetrates the dielectric layers 110, i08 and 101, and Fight the air gap 106 to form an opening 106a connecting the interlayer window 112 and the door of the air gap 106. When a barrier layer (ban: ierlayer) ii4 is formed on the dielectric layer 110 and the dielectric window 112 by chemical vapor deposition (CVD), the barrier layer 1U is difficult to penetrate into the air gap. During the subsequent formation of a tungsten plug (not shown), the reaction gas tungsten tungsten (WFe) diffuses into the air gap 106 and reacts with the oxide contained in the dielectric layer 104. The phenomenon of causing via via poisoning ^ Therefore, the present invention is to provide a method for forming multiple interconnects. The method is briefly described as follows: forming a first conductive line and a second conductive line Y on a substrate; and A portion of the substrate is exposed between the first and second wires. Next, a first dielectric layer is formed on the bottom and the first and second wires, and an air gap is formed in the area defined by the first dielectric layer and the first and second wires. Continuing, an anti-etching layer is formed on the first dielectric layer above the air gap. After that, a second dielectric layer is formed on the anti-etching layer and the first dielectric layer. Then, an etching-resistant layer is used as a mask to form an interlayer window opening exposing the first conductive line. Then, a barrier layer is formed on the sidewall of the via of the via and the surface of the first conductive line exposed by the via of the via. Finally, a via plug is formed in the via window opening and the via window plug fills the via window. The anti-etching layer is an insulating material, which preferably includes silicon nitride, titanium oxide, or molybdenum oxide, and the anti-etching layer has a larger etching selection ratio for the first dielectric layer and the second dielectric layer. Or, during the chemical mechanical honing process, the honing rate of the anti-etching layer is lower than that of the first dielectric layer. Since the anti-etching layer has a larger etching selection ratio for the first dielectric layer and the second dielectric layer, when an alignment error occurs in the formation of the dielectric window, you can (Please read the precautions on the back before filling this page ) n I n I 1 1 Order --------- line, consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs, Du printed 1 This paper size is applicable to China National Standard (CNS) A4 (21. x 297) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 408441 A7 4950i \ vf.doc / 008 V. Description of the Invention (>) With the anti-etching layer as the cover, the interlayer window will not penetrate the first above the air gap The dielectric layer opens the air gap. Therefore, it is possible to solve the problems such as the poisoning of the interlayer window caused by the air gap opened by the interlayer window. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 It is a schematic cross-sectional view showing that the formation of the dielectric window is misaligned so that the dielectric window penetrates the electrical layer and communicates with the air gap. Figures 2A to 2E show a formation according to a preferred embodiment of the present invention. The method of multiple interconnections; and FIG. 3 is a schematic cross-sectional view showing that an alignment error occurs when a via window is formed. The relationship between each icon number and the component name is as follows: 100, 200: substrate 102: patterned conductive layer 104, 108, 110, 204, 208, 210, 211: dielectric layer 106, 206: air gap 112, 212 312: via window openings 112a, 212a, 312a: via window plugs 114, 214, 314: barrier layers 202a, 202b: conductive wires 207, 207a: examples of anti-etching layers Figures 2A to 2E show According to a preferred embodiment of the present invention, a 5-wood paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)! (谙 Read the precautions on the back before filling this page) / Installation ----- --- Order ----- Line '408441 A7 B7 4950twf.doc / 008 V. Description of the invention) Method for forming multiple internal connections. Referring to FIG. 2A, first, a substrate 200 is provided. A semiconductor element (not shown) has been formed in the substrate 200. Next, conductive wires 2202a, 2202b, and 2202c are formed on the substrate 200. The conductive wires 2002a, 2202, and 2202 are used as the lead structure of the device. Continuing, a dielectric layer 204 'is formed on the substrate 200 and the wires 202a, 202b, and 202c, and the dielectric layer 204 forms an air gap 20 between the wires 202a, 202b, and 202c. . The 'dielectric layer 204 may be a dielectric layer with poor step coverage, preferably silicon oxide formed by a plasma-enhanced chemical vapor deposition (PEC VD) method. Layer, and its thickness on the wires 202a, 202b, and 202c is between about 2000 and 4000 angstroms, and the preferred thickness is about 3000 angstroms. The dielectric layer 204 is made of a material with poor step coverage. When the dielectric layer 204 is filled in the space between the wires 202a, 202b, and 202c, it will be above the space between the wires 202a, 202b, and 202c. The overhang structure is formed, which causes the material of the subsequently deposited electrical layer 204 to not easily penetrate into the space between the patterned conductive layers, and is connected to each other in the process of forming the dielectric layer 204, so that the wires 202a, 202b, and 202c are formed. An air gap 206 is formed in the interspace. Referring to FIG. 2B, an anti-etching layer 207 is formed on the dielectric layer 204 afterwards. Among them, the anti-etching layer 207 has a larger etching selection ratio for the dielectric layer 204, and during the chemical mechanical honing process, the honing rate of the anti-etching layer 207 is lower than that of the dielectric layer 204, and the anti-etching layer 207 is formed at low temperature (less than about 500 degrees Celsius), preferably by plasma enhanced chemical vapor deposition or photo-induced chemical vapor deposition (PICVD). Formation of gasification 6 (Please read the precautions on the back before filling this page)
-- — fill — — — — — — — — — I 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） 408441 A7 B7 4950twf.doc/008 五、發明說明) 砍層、氧化欽層或氧化钽層。 請參照第2C圖，繼之，剝除部分抗鈾刻層207，直到 裸露部分介電層204之表面，並在空氣間隙206上方之部 分介電層204上形成抗蝕刻層207a。其中，剝除部分抗蝕 刻層207之方法包括化學機械硏磨法（chemical-mechanical polishing，CMP)。由於在導線 202a、202b 與 202c 之間的 空間中形成空氣間隙206時，介電層204之表面輪廓，會 隨著導線202a、202b與202c之輪廓而起伏，因此位於空 氣間隙206上方之介電層204之高度低於位於導線202a、 202b與202c上之介電層2〇4，此外，在化學機械硏磨製程 時，抗蝕刻層207之磨除率較介電層204低。所以在以化 學機械硏磨法剝除部分抗蝕刻層2〇7後，會在空氣間隙206 上方之介電層204上形成抗蝕刻層207a。 請參照第2D圖，接著依序在基底200上方形成介電層 208與210。其中，介電層2〇8對於抗蝕刻層2〇7a具有較 大的蝕刻選擇比，且介電層2〇8例如是以高密度電漿化學 氣相沉積法（high-density-plasma chemical vapor deposition，HDPCVD)所形成之氧化砂層，而介電層210 例如是以電漿加強型化學氣相沉積法所形成之氧化矽 層。爲簡化說明’以下將介電層208與210標示爲介電層 211。 接著，請參照第2Ε圖’定義介電層211與介電層204， 形成穿透介電層211與204並裸露導線202a、202b與202c 之一介層窗口 212。續之’於介層窗口 212之周圍側壁以 及介層窗口所裸露之導線202a、與2〇2c上，形成阻 7 本紙張尺度適用中國國家標準（CNS>A4規格（210x297公釐） (請先閱讀背面之注意事項再填寫本茛)-— Fill — — — — — — — — — — I Printed on the paper by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economy Standards for Chinese papers (CNS) A4 (210 χ 297 mm) 408441 A7 B7 4950twf.doc / 008 5. Description of the invention) Cutting layer, oxide layer or tantalum oxide layer. Referring to FIG. 2C, then, a part of the anti-uranium etched layer 207 is stripped until the surface of the dielectric layer 204 is exposed, and an anti-etched layer 207a is formed on the part of the dielectric layer 204 above the air gap 206. Among them, a method for stripping a part of the etching resist 207 includes chemical-mechanical polishing (CMP). When the air gap 206 is formed in the space between the wires 202a, 202b, and 202c, the surface profile of the dielectric layer 204 fluctuates with the outline of the wires 202a, 202b, and 202c, so the dielectric located above the air gap 206 The height of the layer 204 is lower than that of the dielectric layers 204 located on the wires 202a, 202b, and 202c. In addition, the removal rate of the anti-etching layer 207 is lower than that of the dielectric layer 204 during the CMP process. Therefore, after a part of the anti-etching layer 207 is removed by chemical mechanical honing, an anti-etching layer 207a is formed on the dielectric layer 204 above the air gap 206. Referring to FIG. 2D, the dielectric layers 208 and 210 are sequentially formed on the substrate 200. Among them, the dielectric layer 208 has a larger etching selection ratio to the anti-etching layer 207a, and the dielectric layer 208 is, for example, a high-density-plasma chemical vapor method. deposition (HDPCVD), and the dielectric layer 210 is, for example, a silicon oxide layer formed by a plasma enhanced chemical vapor deposition method. To simplify the description ', the dielectric layers 208 and 210 are hereinafter referred to as a dielectric layer 211. Next, referring to FIG. 2E, the dielectric layer 211 and the dielectric layer 204 are defined to form a dielectric window 212 that penetrates the dielectric layers 211 and 204 and exposes one of the wires 202a, 202b, and 202c. Continued 'on the sidewalls of the interposer window 212 and the exposed wires 202a and 20c of the interposer window to form a resistance 7 This paper size applies to Chinese national standards (CNS > A4 size (210x297 mm) (please first (Read the notes on the back and fill in this buttercup)
，装--------訂---------線I 經濟部智慧財產局員工消費合作社印製 408441 A7 4950twf,doc/008 B7 五、發明說明) (請先閱讀背面之注意事項再填寫本頁) 障層214。此阻障層2 14例如是一層欽/氮化欽層。之後， 於介層窗口 212中，形成一介層窗插塞212a，以塡滿介層 窗口 212。其中，介層窗插塞2Ua例如是一鎢插塞。 線、 在形成介層窗口，發生對準失誤時，請參照第3圖，圖 中所示之物件除了因對準失誤所形成之介層窗口以及介 層窗插塞分別標示爲312與3 12a外，由於製程步驟相同， 因此，其餘物件之標號均與第2E圖相同。由於抗蝕刻層 207a對於介電層204與208具有較大的蝕刻選擇比，因此 在形成介層窗口 3 I2發生對準失誤時，可以抗蝕刻層207a 做爲空氣間隙206上方的介電層204之罩幕層，並利用控 制蝕刻氣體的蝕刻選擇比，使得對準失誤所形成之介層窗 口 312僅蝕刻穿透圖案化導電層212上方之部分介電層 211與204，直到裸露部分導線202a、202b與202c。換句 話說，在形成介層窗口 312，發生對準失誤時，因爲空氣 間隙206上方之介電層204有抗蝕刻層207a之保護，因此 對準失誤之介層窗口 312不會穿透介電層204而開啓空氣 間隙206。 經濟部智慧財產局員工消費合作社印製 再者，由於抗蝕刻層207a保護空氣間隙206不被介層 窗口穿透，因此後續形成之阻障層214可以完全隔離介層 窗插塞312a與介電層211與204，因此可解決習知因爲開 啓空氣間隙，而阻障層無法完全隔離介電層與介層窗插 塞，造成介層窗毒化等問題。 雖然本發明已以一較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 4950twf,doc/008 408441 _B7_ 五、發明說明（） 範圍當視後附之申請專利範圍所界定者爲準。 (請先閲讀背面之注意事項再填寫本頁) 訂---------線、' 經濟部智慧財產局員Η消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐）-------- Order --------- Line I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 408441 A7 4950twf, doc / 008 B7 V. Description of Invention) (Please read the back first (Notes on this page, please fill in this page) barrier layer 214. The barrier layer 2 14 is, for example, a Chin / nitride Chin layer. Thereafter, a via plug 212a is formed in the via window 212 to fill the via window 212. The via window plug 2Ua is, for example, a tungsten plug. In the case of misalignment when forming a via window, please refer to Figure 3. The objects shown in the figure are marked as 312 and 3 12a, except for the via window and via plug formed by the misalignment. In addition, because the process steps are the same, the reference numerals of the remaining objects are the same as those in Figure 2E. Since the anti-etching layer 207a has a large etching selection ratio for the dielectric layers 204 and 208, when an alignment error occurs in the formation of the dielectric window 3 I2, the anti-etching layer 207a can be used as the dielectric layer 204 above the air gap 206 Mask layer, and use the etching selection ratio of the control etching gas, so that the interlayer window 312 formed by the misalignment only etches through the dielectric layers 211 and 204 above the patterned conductive layer 212 until the exposed portion of the conductor 202a , 202b, and 202c. In other words, when the alignment window 312 is formed and an alignment error occurs, because the dielectric layer 204 above the air gap 206 is protected by the anti-etching layer 207a, the misaligned dielectric window 312 does not penetrate the dielectric Layer 204 while opening an air gap 206. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Since the anti-etching layer 207a protects the air gap 206 from being penetrated by the interlayer window, the subsequent barrier layer 214 can completely isolate the interlayer window plug 312a from the dielectric. The layers 211 and 204 can solve the problems that the barrier layer cannot completely isolate the dielectric layer and the dielectric window plug because the air gap is opened, which causes the poisoning of the dielectric window. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. Protection of the invention 8 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A7 4950twf, doc / 008 408441 _B7_ V. Description of the invention () Scope The scope of the patent application as defined in the appendix is defined as quasi. (Please read the precautions on the back before filling this page) Order --------- line, 'Member of the Intellectual Property Bureau of the Ministry of Economy ΗConsumer Cooperative Co., Ltd. This paper is printed in accordance with China National Standard (CNS) A4 Specification (210 χ 297 mm)