525258 4047twf.doc/006 A7 B7 五、發明説明（ί) 本發明是有關於一種介電層的製造方法，且特別是有 關於一種低介電係數介電層的製造方法。 隨者半導體兀件的線覓不斷地縮小，金屬線與金屬線 間的距離也越來越短，導致寄生電容(ParasitK： Capacitor)的 現象越來越嚴重，因此內金屬介電層（Inter—Metal525258 4047twf.doc / 006 A7 B7 V. Description of the Invention The invention relates to a method for manufacturing a dielectric layer, and more particularly to a method for manufacturing a low-k dielectric layer. With the continuous shrinking of the semiconductor metal parts, the distance between metal lines and metal lines is getting shorter and shorter, resulting in parasitic capacitance (ParacitK: Capacitor) phenomenon is getting more and more serious, so the inner metal dielectric layer (Inter- Metal
Dielectrics ; IMD)介電係數（Dielectric Constant)的大小 也愈來愈重要。而介電層的介電係數越大，寄生電容越易 產生，導致 RC 時間延遲（Resistance Capacitance Time Delay ; RC delay)更形嚴重，而降低電路傳輸速度。因此藉由降低 介電層的介電係數，可降低RC時間延遲，增進元件的操 作速度。 但習知使用低介電係數介電層時，常常因爲介電係數 不夠低而無法降低金屬線間的寄生電容。或於後續金屬化 製程中，由於低介電係數介電材質具有吸水性，而因低介 電係數介電層內部所含有的水氣，使得所形成的金屬插塞 產生毒化(Poison)的現象。 因此本發明的目的就是在提供一種低介電係數介電層 的製造方法，藉形成低介電係數介電層而降低電路上的RC 時間延遲，因此增進元件的速度，提升產品品質，並且避 免金屬毒化現象。 爲達成本發明之目的，提出一種低介電係數介電層的 製造方法，於一已完成半導體元件之基底上形成金屬線’ 再於基底上形成第一層介電層，而此介電層於金屬線之間 具有孔洞，再於第一層介電層上形成第二層介電層。 3 本紙張尺度適用中國國家標準（CNS ) A4規格（21 OX297公釐） (請先閱讀背面之注意事pif填寫本頁) 、言 經濟部中央標準局員工消費合作社印製 525258 4047twf.doc/006 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（2) 由於所形成之介電層於金屬線間具有孔洞’因此介電 係數會比不具孔洞之介電層爲低，得以減少金屬線間寄生 電容的產生，降低RC時間延遲，增進元件的操作速度。 並由於無須採用低介電常數之介電材質，可避免金屬毒化 現象。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下= 圖式之簡單說明： 第1A圖〜第1D圖繪示依照本發明一較佳實施例的一 種低介電係數介電層的製造方法剖面示意圖。 圖式之標記說明： 100 :基底 102、102a、102b :金屬線 104、105 :孔洞 110、140 :二氧化矽層 實施例 第1A圖〜第1D圖繪示依照本發明一較佳實施例的一 種低介電係數介電層的製造方法剖面示意ffl。 請參照第1A圖，提供一已完成半導體元件之基底 100 ’比如基底100上已形成金氧半電晶體元件(未繪示）， 於基底100上形成圖案化之金屬層102，金屬層1〇2包括 有金屬線102a、102b、102c ’其形成方法例如先沉積一層 金屬材質後，再進行微影蝕刻製程。 ~ 4 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇ϋ7公釐） "" (請先閱讀背面之注意事填寫本頁) -裝· 訂 線 525258 4047twf.doc/006 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（；） 請參照第1B圖，於基底100與金屬線102a、102b、102c 上形成一層當作內金屬介電層的二氧化矽層110,例如使 用電漿加強型化學氣相沈積步驟(Plasma Enhanced Chemical Vapor Deposition ; PECVD)進行快速沈積，控制其階梯覆蓋 程度，於金屬線102a、102b、102c之間產生孔洞（V〇1d)l〇4、 105，而孔洞104與105距基底100表面之高度與金屬線 102a、102b、102c之間的距離有關。於間距較小之金屬線 102a、102b之間，會有距離基底100表面較近之孔洞104 產生。而於間距較大之金屬線l〇2b、102c之間，會有距離 基底100表面較遠之孔洞105產生。 請參照第1C圖，進行回蝕(Etch Back)，例如使用乾蝕 刻，直到暴露出高於金屬線l〇2a、102b、102c高度的孔洞 105，而介於金屬線102a、102b之間的孔洞104，則不會 暴露出來。且透過回蝕步驟，可得到一較平坦之表面。由 於本發明以回蝕取代化學機械硏磨，因此不會因爲硏漿進 入被暴露出之孔洞105,而影響半導體元件或內金屬介電 層之品質。並且，此回鈾步驟使孔洞104變得更爲圓滑， 使得後續於其他製程中進行化學機械硏磨時，孔洞1〇4不 會破裂，介電層結構得以維持穩定’並保持所得到的低介 電係數。 請參照第1D圖，進行PECVD-TEOS的沉積，以形成 一層二氧化矽層140，即以矽酸四乙酯（TE0S)當先驅物 (Precursor*)進行電漿力D強型化學氣相沈積步驟，由於 PECVD-TEOS之溝塡能力（Gap-filing Ability)極佳’可以很 5 (請先閲讀背面之注意事¥ 穿-- Jc寫本頁) 、言 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X297公釐） 525258 4047twf.doc/006 經濟部中央標準局員工消費合作社印製 4047twf.doc/006 A 7 _B7 _ 五、發明説明（仁） 容易在被暴露出之孔洞105中塡入二氧化砂材質。因此在 後續製程中，比如後續進行化學機械硏磨’以獲得全面性 平坦化時，可避免孔洞105之暴露。 完成介電層之製作後，二氧化矽層110於金屬線102a、 102b之盟保留苴丑一洞104。由於間距較小之兩相鄰金屬線 102a、102b間的介電層爲孔洞1〇〇與二氧化矽層丨丨0所構 成。而二氧化矽的介電係數爲4.0-4.9，空氣的介電係數爲 1.00059，使得金屬線l〇2a、102間所形成之介電層的等效 介電係數會較二氧化矽低，甚至低於一般低介電係數材 質。一般而言，間距愈短的金屬線間，寄生電容及RC延 遲的現象尤其明顯。藉由降低金屬線l〇2a、l〇2b間介電層 的介電係數，可避免間距較小的金屬線l〇2a與金屬線102b 間產生寄生電容，並降低RC時間延遲，因此能增進元件 的操作速度。 由上述本發明較佳實施例可知，應用本發明至少具有 下述優點： 1. 由於此具孔洞之二氧化矽層由二氧化矽與孔洞所構 成，使間距較小的金屬線間的介電層具有極低的介電係 數。可避免間距較小的金屬線間產生寄生電容，降低RC 時間延遲，增進元件的操作速度。 2. 由於本發明之介電層結構使得高介電係數之材質， 可具有低介電係數之等效效果，因此可取代低介電係數材 質，免除低介電係數材質之金屬毒化現象。 雖然本發明已以一較佳實施例揭露如上，然其並非用 (請先閱讀背面之注意事1·^填寫本頁) 裝· 訂 線 本紙張又度適用中國國家標準（CNS ) A4規格（21〇X 297公釐） 525258 4047twf.doc/006 A7 B7 五、發明説明（乡） 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 請 先 閲 讀 背 面 意 -裝-- 「填寫本頁) 線 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）Dielectrics (IMD) dielectric constant (Dielectric Constant) is also more and more important. The larger the dielectric constant of the dielectric layer, the more easily the parasitic capacitance is generated, resulting in a more severe RC time delay (RC delay), which reduces the circuit transmission speed. Therefore, by reducing the dielectric constant of the dielectric layer, the RC time delay can be reduced and the operation speed of the device can be improved. However, when using a low dielectric constant dielectric layer, it is often impossible to reduce the parasitic capacitance between metal lines because the dielectric constant is not low enough. Or in the subsequent metallization process, because the low-k dielectric material has water absorption, and due to the moisture contained in the low-k dielectric layer, the formed metal plug has a phenomenon of poisoning (Poison). . Therefore, the object of the present invention is to provide a method for manufacturing a low-dielectric-constant dielectric layer, which can reduce the RC time delay on a circuit by forming a low-dielectric-constant dielectric layer, thereby increasing the speed of components, improving product quality, and avoiding Metal poisoning. In order to achieve the purpose of the present invention, a method for manufacturing a low-dielectric-constant dielectric layer is proposed. A metal line is formed on a substrate of a completed semiconductor element, and then a first dielectric layer is formed on the substrate. There are holes between the metal lines, and a second dielectric layer is formed on the first dielectric layer. 3 This paper size applies Chinese National Standard (CNS) A4 specification (21 OX297 mm) (please read the note on the back pif first and fill out this page), printed by the Central Consumers Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperatives 525258 4047twf.doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (2) Because the formed dielectric layer has holes between the metal wires, the dielectric constant will be lower than that of a dielectric layer without holes, which can be reduced The generation of parasitic capacitance between metal lines reduces the RC time delay and improves the operating speed of the device. And because it is not necessary to use a low dielectric constant dielectric material, metal poisoning can be avoided. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below, and the following detailed description is given in conjunction with the accompanying drawings. = Brief description of the drawings: Figure 1A Figure 1D is a schematic cross-sectional view of a method for manufacturing a low-k dielectric layer according to a preferred embodiment of the present invention. Description of the drawing marks: 100: substrates 102, 102a, 102b: metal wires 104, 105: holes 110, 140: silicon dioxide layer embodiments. FIGS. 1A to 1D show a diagram according to a preferred embodiment of the present invention. A cross-sectional view of a method for manufacturing a low-dielectric-constant dielectric layer is ffl. Referring to FIG. 1A, a completed semiconductor device substrate 100 is provided. For example, a metal oxide semiconductor device (not shown) has been formed on the substrate 100, and a patterned metal layer 102 and a metal layer 1 are formed on the substrate 100. 2 includes metal lines 102a, 102b, and 102c ′, and a method for forming the metal lines 102a, 102b, and 102c is performed by, for example, depositing a layer of metal material first, and then performing a lithography etching process. ~ 4 This paper size applies to China National Standard (CNS) A4 specification (21〇7mm) " " (Please read the notes on the back first and fill in this page)-Binding · Thread 525258 4047twf.doc / 006 A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (;) Please refer to Figure 1B to form a silicon dioxide layer 110 as an inner metal dielectric layer on the substrate 100 and the metal wires 102a, 102b, 102c. For example, Plasma Enhanced Chemical Vapor Deposition (PECVD) is used for rapid deposition to control the degree of step coverage, and holes (V〇1d) are generated between the metal wires 102a, 102b, and 102c. 4, 105, and the height of the holes 104 and 105 from the surface of the substrate 100 is related to the distance between the metal lines 102a, 102b, and 102c. Between the metal wires 102a and 102b with a small distance, holes 104 are formed closer to the surface of the substrate 100. Between the metal lines 102b and 102c having a larger distance, holes 105 are formed farther from the surface of the substrate 100. Please refer to FIG. 1C to perform etch back (for example, dry etching) until holes 105 higher than the metal lines 102a, 102b, and 102c are exposed, and holes between the metal lines 102a and 102b are exposed. 104, it will not be exposed. And through the etch-back step, a flatter surface can be obtained. Since the present invention replaces chemical mechanical honing with etchback, the quality of the semiconductor element or the inner metal dielectric layer will not be affected because the slurry enters the exposed hole 105. In addition, this step of uranium return makes the hole 104 smoother, so that during subsequent chemical mechanical honing in other processes, the hole 104 will not break, and the dielectric layer structure can be maintained stable and the resulting low Dielectric coefficient. Please refer to FIG. 1D to perform PECVD-TEOS deposition to form a silicon dioxide layer 140, that is, to use plasma tetraethyl silicate (TE0S) as a precursor (Precursor *) for plasma strength D strong chemical vapor deposition Steps, because of the excellent Gap-filing Ability of PECVD-TEOS, it can be 5 (please read the notes on the back first ¥ Wear-Jc write this page), the paper size is applicable to Chinese national standards (CNS ) A4 specification (21 × 297 mm) 525258 4047twf.doc / 006 Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 4047twf.doc / 006 A 7 _B7 _ V. Description of the invention (ren) It is easy to expose the hole 105 The middle is filled with sand dioxide material. Therefore, in subsequent processes, such as subsequent chemical mechanical honing, to achieve comprehensive planarization, the exposure of the holes 105 can be avoided. After the fabrication of the dielectric layer, the silicon dioxide layer 110 retains a hole 104 in the alliance of the metal lines 102a and 102b. Because the dielectric layer between two adjacent metal lines 102a and 102b with a small distance is formed by a hole 100 and a silicon dioxide layer 丨 0. The dielectric coefficient of silicon dioxide is 4.0-4.9, and the dielectric coefficient of air is 1.00059, so that the equivalent dielectric coefficient of the dielectric layer formed between the metal lines 102a and 102 will be lower than that of silicon dioxide, or even Lower than normal low dielectric constant materials. In general, the phenomenon of parasitic capacitance and RC delay between metal lines with shorter pitches is particularly obvious. By reducing the dielectric coefficient of the dielectric layer between the metal lines 102a and 102b, it is possible to avoid parasitic capacitance between the metal lines 102a and 102b with a small pitch, and to reduce the RC time delay, thereby improving the Element operating speed. It can be known from the above-mentioned preferred embodiments of the present invention that the application of the present invention has at least the following advantages: 1. Since the silicon dioxide layer with holes is composed of silicon dioxide and holes, the dielectric between the metal wires with a small distance is made. The layer has an extremely low dielectric constant. It can avoid the parasitic capacitance between the metal wires with a small pitch, reduce the RC time delay, and improve the operation speed of the component. 2. Due to the structure of the dielectric layer of the present invention, a material with a high dielectric constant can have the equivalent effect of a material with a low dielectric constant, so it can replace a material with a low dielectric constant and avoid the phenomenon of metal poisoning of the material with a low dielectric constant. Although the present invention has been disclosed as above with a preferred embodiment, it is not used (please read the notes on the back 1 · ^ to fill out this page). The binding and binding paper is also applicable to the Chinese National Standard (CNS) A4 specification ( 21〇X 297 mm) 525258 4047twf.doc / 006 A7 B7 V. Description of the invention (township) To limit the invention, anyone skilled in the art can make various changes without departing from the spirit and scope of the invention. And retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. Please read the back of the book-Installation-"Fill this page" line Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy