經濟部智驽財產局員工消費合作，社印製 Λ26939 4867twf.docO06 A 7 五、發明說明（/) 本發明是有關於一種內金屬介電層（Inter_meulConsumption Cooperation by Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the agency Λ26939 4867twf.docO06 A 7 V. Description of the Invention (/) The present invention relates to an internal metal dielectric layer (Inter_meul
Dielectric)的製造方法，且特別是有關於—種降低元件 之電阻-電容時間延遲（RC Tlme Delay)的內金屬介電層 之製造方法。 在超大型積體電路（ULSI)的製程上’可以在丨〜2平 方公分面積的矽表面上配置數量多達數十萬的電晶體。並 且，爲了增加積體電路的積集度，將提高連接各個電晶體 或是其他元件的金屬線之密度。所以，以往單一金屬層的 設計，將無法完成整個積體電路的連線工作’兩層以上的 金屬層設計，便逐漸的成爲許多積體電路所必需採用的方 式二因此在金屬層之間須以內金屬介電層加以隔離，以避 免元件之間產生非預期性的導通，並在內金屬介電層中形 成介層窗，接著覆蓋導電材料以形成導線，在半導體工業 上稱之爲插塞（Plug)，用來連接上下兩層金屬層。 然而’隨者兀件尺寸的縮小，相鄰之導線的間距亦隨 之縮小，右做爲導線間之電性隔離的內金屬介電層之介電 常數無法有效降低，導線間之電阻-電容時間延遲(SRcTime Delay)的增加會降低資料傳輸的速度’使其成爲元件的 丨'生能限制因素。 因此，本發明fen供一種具有低介電常數的內金屬介電 層的製造方法’且其介電常數可以藉由製程加以調整，藉 以降低內連線電阻-電容時間延遲的問題^ ’fe上所述，本發明提供一種內金屬介電層的製造方 法’包括：於所提供的基底上形成導線，導線間有開口， 3 ^ ___ — ,, 、足通用中闼囤家標準〗规格(21ϋχ297公釐) --------—II^--------訂·-----I--線' (請先閱讀背面之注意事項再填寫本頁) .doc/006 .doc/006 經濟部智慧財產局員工消費合作社印製 五、發明說明（2) 之後，於開口中塡入具有一厚度的流動性介電材質層，並 且使其上表面低於導線的上表面，再於流動性介電材質層 上導線的側壁形成間隙壁。接著將流動性介電材質層予以 剝除，以暴露出間隙壁的底部，且其底部與基底的表面相 隔一距離，續利用一側向溝塡能力不佳的非等向性沈積方 式，於導線上沈積一層介電層，而在間隙壁底部下方和基 底之間形成一孔洞。 依照本發明的一較佳實施例，其中於開口中塡入流動 性介電材質層前，更包括於導線和基底的表面形成一層襯 層。至於流動性介電材質層的材質，包括旋塗式聚合物、 有機的旋塗式玻璃或其他類似此性質的聚合物。而此側向 溝塡能力不佳的非等向性沈積方式包括濺鍍法。 由於內金屬介電層在導線間會形成孔洞，此孔洞的介 電常數爲1，可藉以降低內金屬介電層整體的介電常數。 因此可以降低導線間之電阻-電容時間延遲的問題，並因 此改善元件的效能。再者，孔洞之大小可以根據元件的需 要而加以調整，其調整的方式係藉由控制相鄰導線間之具 流動性的介電材質層的厚度，以及控制間隙壁底部的寬度 而得。使得內金屬介電層的介電常數之大小，可藉由改變 孔洞的大小來加以控制。 · 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 4 ------------裝--------訂---------線. (請先閱讀背面之注意事項再填寫本頁) 本紙張&度洎用中國國家標準（CNS)A_1規格（2Ιϋ X 297公釐） 經濟部智慧財產局員工消費合作社印裝 42693 9 五、發明說明（彡） 第1A圖至第1D圖係繪示根據本發明一較佳實施例之 一種內金屬介電層的製造流程剖面圖。 其中，各圖標號與構件名稱之關係如下： 100 :基底 102 :導線 104 :襯層 106 :具流動性的介電材質層 108 :間隙壁 110 :介電層 112 :孔洞 120 :開□ 實施例 第1A圖至第1D圖所示，爲根據本發明一較佳實施例 之一種內金屬介電層的製造流程剖面圖。 首先請參照第U圖，提供基底100，比如是半導體砂 基底，此基底100中至少包括金氧半電晶體元件’然爲方 便圖示，並未將基底丨〇〇中所包含的元件繪出。接著’在 基底100上形成一已定義的導線102，其方法比如是於基 底100上形成一層金屬層，其中金屬層的材質比如是鋁或 i呂合金等，再利用傳統的微影蝕刻製程，以形成如圖所不 之導線102 1導線102間有開口 120。 之後，於導線102與基底100所暴露出的表面形成一 層共形的襯層，襯層104的材質係爲介電材質，其材 質比如是富含矽氧化物，其厚度比如約介於200埃至300 本紙張尺度適用中國國家標準（C'NSW.1规格（210 x 297公髮） ------------ 裝--------訂---------， - (請先閱讀背面之注意事項再填寫本頁) . 經濟部智慧財產局員工消費合作社印製 /12693 9 4867twf.doc 006 五、發明說明（γ) 埃之間。襯層104直接覆蓋於導線102的表面，其目的是 爲了避免後續所沈積之流動性介電材質直接接觸導線102 而影響到導線102的品質。接著，於開口 120中塡入具流 動性的介電材質層106,其材質較佳的是旋塗式聚合物 (Spin On Polymer)、有機的旋塗式玻璃（Organic SOG ) 或者是其他類似此性質的聚合物。此具流動性介電材質層 106的上表面較導線102的上表面爲低，意即此具流動性 的介電材質層106的厚度小於導線102的厚度，其厚度較 佳的是約介於2000埃至3000埃之間。 接著請參照第1B圖，於導線102側壁的襯層104外 形成間隙壁108，間隙壁108的材質係爲介電材質，其材 質比如是氧化矽。間隙壁108的形成方法比如是於襯層104 和具流動性的介電材質層106上形成一層共形的介電層， 之後進行非等向性回蝕刻製程，直至暴露出具流動性的介 電材質層106爲止，以形成此間隙壁108。此外，間隙壁 108的底面（與具流動性的介電材質層106接觸的面）之 寬度，與之後欲形成之內金屬介電層的介電常數有關，而 間隙壁108的底面之寬度的控制則可藉由控制其共形的介 電層所沈積之厚度。 接著請參照第1C圖，剝除具流動性的介電材質層 106，直至暴露出襯層104。其剝除的方式比如是選用對具 流動性的介電材質層106和間隙壁108具有高選擇比的蝕 刻劑，且其與襯層104亦有高選擇比的蝕刻劑，進行濕式 蝕刻。 6 ------------^---ί I---訂---------線 — (請先開讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標牟彳蜆格（210 X 297公釐） 42693 9 4867lvvt.doc 006 五、發明說明（j:) 接著請參照第1D圖’利用側向溝塡能力不佳的非等 向性沈積方式，比如濺鍍法，於襯層104和間隙壁108上 覆蓋一層經平坦化的介電層110 ’其中介電層11 〇的材質 比如是氧化矽，而平坦化的方法比如是化學機械硏磨法。 因此，經由上述的沈積步驟後’在間隙壁1 〇 8下方會形成 孔洞112，而此孔洞112的大小可以根據元件的需要而加 以調整，其調整的方式係藉由控制具流動性的介電材質層 106的厚度和間隙壁108底部的寬度而得。 由於孔洞112中的空氣之介電常數爲1.0，比氧化矽 的介電常數低，因此可降低包括孔洞112和介電層110的 內金屬介電層之介電常數，故可以有效降低其電阻-電容 時間延遲。換言之，內金屬介電層的介電常數之大小，可 藉由改變孔洞112的大小來加以控制。若愈提高內金屬介 電層整體的介電常數，則可藉由加寬間隙壁108底部的寬 度，或加厚具流動性的介電材質層106之厚度；反之亦然。 本發明的特徵如下： 1. 本發明之內金屬介電層在導線間會形成孔洞，此 孔洞的介電常數爲1，藉以降低內金屬介電層的介電常 數。因此可以降低導線間之電阻-電容時間延遲的問題， 並因此改善元件的效能。 - 2. 在導線兩側之間隙壁下方所形成的孔洞之大小可 以根據元件的需要而加以調整，其調整的方式係藉由控制 相鄰導線間之具流動性的介電材質層的厚度，以及控制位 於具流動性介電材質層上方導線側壁之間隙壁底部的寬 7 (請先閱讀背面之注意事項再填寫本頁) 展---- 訂---------線- 經濟部智慧財產局員工消f合作社印製 本紙張尺度適用中國囤家標半-(α\Ή.)Λ1規格（210 X 297公复） A： B7 4 2-B 9 3 9 4867twt.doc/〇06 五、發明說明（6) 度而得。使得內金屬介電層的介電常數之大小，可藉由改 變孔洞的大小來加以控制。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 ------------ 牧--------訂·-------- t 4 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 8 本紙張尺度通用中國國家標準規格（ΙΟχ 297公釐）Dielectric) manufacturing method, and in particular, a manufacturing method of an inner metal dielectric layer that reduces the resistance-capacitance time delay (RC Tlme Delay) of a device. In the ultra-large integrated circuit (ULSI) manufacturing process, a number of hundreds of thousands of transistors can be arranged on a silicon surface with an area of 2 square centimeters. In addition, in order to increase the integration degree of the integrated circuit, the density of metal wires connecting various transistors or other components will be increased. Therefore, in the past, the design of a single metal layer could not complete the wiring work of the integrated circuit. The design of two or more metal layers has gradually become the necessary method for many integrated circuits. Isolate the inner metal dielectric layer to avoid unintended conduction between the components, and form a dielectric window in the inner metal dielectric layer, and then cover the conductive material to form a wire, which is called a plug in the semiconductor industry (Plug), used to connect the upper and lower metal layers. However, as the size of the accompanying pieces decreases, the distance between adjacent wires also decreases. The dielectric constant of the inner metal dielectric layer, which is electrically isolated between the wires, cannot be effectively reduced, and the resistance-capacitance between the wires cannot be effectively reduced. The increase of the time delay (SRcTime Delay) will reduce the speed of data transmission, making it a limiting factor for the energy of the component. Therefore, the present invention provides a method for manufacturing an inner metal dielectric layer having a low dielectric constant, and its dielectric constant can be adjusted by a manufacturing process, thereby reducing the problem of the resistance-capacitance time delay of the interconnect ^ 'fe on As mentioned above, the present invention provides a method for manufacturing an inner metal dielectric layer, which includes: forming wires on the provided substrate, with openings between the wires, 3 ^ ___ — ,, which meets the general standard of China ’s standard ϋ (21ϋχ297) (Mm) ---------- II ^ -------- Order · ----- I--Line '(Please read the notes on the back before filling this page) .doc / 006 .doc / 006 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (2), insert a layer of fluid dielectric material with a thickness in the opening, and make its upper surface lower than that of the wire On the surface, a gap is formed on the side wall of the wire on the fluid dielectric material layer. Next, the fluid dielectric material layer is stripped to expose the bottom of the barrier wall, and its bottom is separated from the surface of the substrate by a non-isotropic deposition method with poor lateral gully capacity. A dielectric layer is deposited on the wire, and a hole is formed between the bottom of the spacer and the substrate. According to a preferred embodiment of the present invention, the method further comprises forming a liner layer on the surface of the conductive wire and the substrate before the fluid dielectric material layer is inserted into the opening. As for the material of the fluid dielectric material layer, it includes spin-on polymers, organic spin-on glass, or other polymers with similar properties. The non-isotropic deposition method with poor lateral gully ability includes sputtering. Since the inner metal dielectric layer has holes formed between the wires, the dielectric constant of the hole is 1, which can reduce the overall dielectric constant of the inner metal dielectric layer. Therefore, the problem of resistance-capacitance time delay between wires can be reduced, and thus the performance of the device can be improved. In addition, the size of the holes can be adjusted according to the needs of the component. The adjustment method is obtained by controlling the thickness of the fluid dielectric material layer between adjacent wires and controlling the width of the bottom of the spacer. The size of the dielectric constant of the inner metal dielectric layer can be controlled by changing the size of the holes. · In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: Brief description of the drawings: 4- ---------- Installation -------- Order --------- line. (Please read the notes on the back before filling this page) This paper & degree 洎Printed in accordance with the Chinese National Standard (CNS) A_1 specification (2 1ϋ X 297 mm), printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, 42693 9 V. Description of the invention (彡) Figures 1A to 1D show a comparison according to the present invention. A cross-sectional view of a manufacturing process of a preferred embodiment of an inner metal dielectric layer. Among them, the relationship between each icon number and the component name is as follows: 100: substrate 102: wire 104: liner 106: fluid dielectric material layer 108: spacer 110: dielectric layer 112: hole 120: open 1A to 1D are cross-sectional views of a manufacturing process of an inner metal dielectric layer according to a preferred embodiment of the present invention. First, please refer to the U figure, and provide a substrate 100, such as a semiconductor sand substrate. This substrate 100 includes at least a metal-oxide semiconductor element. For convenience, the components included in the substrate are not drawn. . Next, a defined wire 102 is formed on the substrate 100. The method is, for example, forming a metal layer on the substrate 100, and the material of the metal layer is aluminum or aluminum alloy, and then the traditional lithography etching process is used. In order to form the leads 102 shown in the figure, there are openings 120 between the leads 102. Then, a conformal underlayer is formed on the exposed surface of the conductive line 102 and the substrate 100. The material of the underlayer 104 is a dielectric material, for example, the material is rich in silicon oxide, and the thickness is, for example, about 200 angstroms. Up to 300 paper sizes are applicable to Chinese national standards (C'NSW.1 specifications (210 x 297)) ------------ installed -------- order ----- ----,-(Please read the notes on the back before filling out this page). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs / 12693 9 4867twf.doc 006 V. Description of the Invention (γ) Between Angstroms. Lining 104 directly covers the surface of the conductive wire 102, the purpose of which is to avoid the subsequent deposition of the fluid dielectric material directly contacting the conductive wire 102 and affecting the quality of the conductive wire 102. Then, a fluid dielectric material is inserted into the opening 120. The layer 106 is preferably made of spin-on polymer, organic SOG, or other polymers with similar properties. The flowable dielectric material layer 106 The upper surface is lower than the upper surface of the wire 102, which means that the thickness of the fluid dielectric material layer 106 is less than The thickness of the conductive wire 102 is preferably between about 2000 angstroms and 3000 angstroms. Next, referring to FIG. 1B, a gap wall 108 is formed outside the liner 104 on the side wall of the wire 102. The material of the gap wall 108 is The dielectric material, such as silicon oxide. The method of forming the spacer 108 is, for example, forming a conformal dielectric layer on the liner layer 104 and the fluid dielectric material layer 106, and then performing anisotropic return The etching process is performed until the flowing dielectric material layer 106 is exposed to form the spacer 108. In addition, the width of the bottom surface of the spacer 108 (the surface in contact with the flowing dielectric material layer 106) and The dielectric constant of the metal dielectric layer to be formed is related, and the width of the bottom surface of the spacer 108 can be controlled by controlling the thickness of the conformal dielectric layer. Next, please refer to FIG. 1C to strip. The flowable dielectric material layer 106 is until the liner 104 is exposed. For example, the stripping method is to select an etchant that has a high selectivity to the flowable dielectric material layer 106 and the spacer 108, and the Liner 104 also has a high selection ratio Etchant for wet etching. 6 ------------ ^ --- ί I --- Order --------- line— (Please read the note on the back first Please fill in this page again on this page) This paper size is applicable to the national standard of China (210 X 297 mm) 42693 9 4867lvvt.doc 006 V. Description of the invention (j :) Then please refer to Figure 1D 'Using lateral gully capacity A good anisotropic deposition method, such as sputtering, covers the liner 104 and the spacer 108 with a planarized dielectric layer 110 ′, wherein the material of the dielectric layer 11 〇 is silicon oxide, and the planarization is performed. The method is, for example, chemical mechanical honing. Therefore, after the above-mentioned deposition step, a hole 112 will be formed under the spacer 108, and the size of this hole 112 can be adjusted according to the needs of the component. The adjustment method is controlled by controlling the dielectric with fluidity. The thickness of the material layer 106 and the width of the bottom of the partition wall 108 are obtained. Since the dielectric constant of the air in the hole 112 is 1.0, which is lower than that of silicon oxide, the dielectric constant of the inner metal dielectric layer including the hole 112 and the dielectric layer 110 can be reduced, so the resistance can be effectively reduced. -Capacitor time delay. In other words, the dielectric constant of the inner metal dielectric layer can be controlled by changing the size of the holes 112. If the overall dielectric constant of the inner metal dielectric layer is further increased, the width of the bottom of the spacer 108 can be widened, or the thickness of the fluid material layer 106 can be increased; and vice versa. The features of the present invention are as follows: 1. The inner metal dielectric layer of the present invention will form a hole between the wires. The dielectric constant of the hole is 1, thereby reducing the dielectric constant of the inner metal dielectric layer. Therefore, the problem of resistance-capacitance time delay between wires can be reduced, and thus the performance of the device can be improved. -2. The size of the hole formed under the gap on both sides of the wire can be adjusted according to the needs of the component. The adjustment method is by controlling the thickness of the fluid dielectric material layer between adjacent wires. And control the width of the bottom of the gap wall located on the side wall of the wire above the layer of fluid dielectric material (please read the precautions on the back before filling this page). The paper printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs and the cooperative is printed on paper. The standard of the paper is applicable to the Chinese storehouse standard of half- (α \ Ή.) Λ1 (210 X 297). 〇06 V. Invention description (6) The size of the dielectric constant of the inner metal dielectric layer can be controlled by changing the size of the holes. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. ------------ Pastoral -------- Order · -------- t 4 (Please read the notes on the back before filling in this page) Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives 8 paper sizes in accordance with Chinese National Standards (ΙΟχ 297 mm)