CN105489549B - A kind of copper interconnection structure and its manufacturing method, electronic device - Google Patents
A kind of copper interconnection structure and its manufacturing method, electronic device Download PDFInfo
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- CN105489549B CN105489549B CN201410538609.4A CN201410538609A CN105489549B CN 105489549 B CN105489549 B CN 105489549B CN 201410538609 A CN201410538609 A CN 201410538609A CN 105489549 B CN105489549 B CN 105489549B
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Abstract
The present invention provides a kind of copper interconnection structure and its manufacturing method, electronic device.The method includes：a)：Semiconductor substrate is provided；b)：Interlayer dielectric layer, etching barrier layer and hard mask layer are sequentially formed on the semiconductor substrate；c)：The hard mask layer, the etching barrier layer and the interlayer dielectric layer are etched, to form groove in the interlayer dielectric layer；d)：In the trench with the layers of copper of depositing flowable on the hard mask layer；And e)：Flowable layers of copper described in etch-back, to form copper interconnecting line.The manufacturing method of the copper interconnection structure provided according to the present invention, CMP process is replaced using etch back process, the height change of the copper interconnecting line on semiconductor product caused by CMP process can be reduced, and due to also smaller to the damage of interlayer dielectric layer caused by moisture absorption.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of copper interconnection structure and its manufacturing method, electronics
Device.
Background technique
In semiconductor integrated circuit, the signal transmission between semiconductor devices needs highdensity metal interconnecting wires.It passes
The metal interconnection of system is to make to realize by aluminium, but with the continuous diminution of device feature size in IC chip,
Current density in metal connecting line constantly increases, and the response time constantly shortens, and traditional aluminum interconnecting has reached technological limits.Work as work
Skill size is less than after 130nm, and traditional aluminum interconnecting technology is gradually replaced copper interconnecting line technology.With aluminum metallic matrix
Than the resistivity of copper metal is lower, electromigration lifetime is longer, can reduce interconnection line using process for copper production metal interconnecting wires
Integrity problem caused by RC retardation ratio, improvement electromigration etc..
Fig. 1 a-1d shows semiconductor device obtained in a kind of committed step of the manufacturing method of existing copper interconnection structure
The diagrammatic cross-section of part.Referring initially to Fig. 1 a, semiconductor substrate 101 is provided.Can have in the semiconductor substrate 101 several
Semiconductor subassembly.Interlayer dielectric layer 102 is formed in the semiconductor substrate 101 later.With reference to Fig. 1 b, existed using etching technics
Groove 103, and the deposit diffusion barriers on the inner wall of groove 103 and interlayer dielectric layer 102 are formed in interlayer dielectric layer 102
104, such as titanium nitride (TiN) or tantalum nitride (TaN), to prevent oxidation and diffusion and the adhesive force for improving copper metal of copper.?
Form copper seed crystal layer 105 in the groove of diffusion barrier layer 104.With reference to Fig. 1 c, using galvanoplastic in copper seed layer 105 shape
At copper interconnection layer 106.Fig. 1 d is turned finally to, extra copper interconnection layer is removed using chemically mechanical polishing (CMP) technique, forms copper
Interconnection line 107.
Extra copper interconnection layer is removed using CMP process, and there are some defects.For example, there are metals on interlayer dielectric layer
Residue will lead to electrical short.This metal residue is mainly due to caused by the uneven surface of interlayer dielectric layer.CMP
It is also possible to lead to the dish-shaped defect of metal area and the erosion of dielectric area.In addition, what is do not washed near medium/metal interface grinds
The chemical substances such as grinding fluid may corrode copper metal.
Summary of the invention
According to an aspect of the invention, there is provided a kind of manufacturing method of copper interconnection structure, including：a)：Offer is partly led
Body substrate；b)：Interlayer dielectric layer, etching barrier layer and hard mask layer are sequentially formed on the semiconductor substrate；c)：Etching institute
Hard mask layer, the etching barrier layer and the interlayer dielectric layer are stated, to form groove in the interlayer dielectric layer；d)：?
The groove neutralizes the layers of copper of depositing flowable on the hard mask layer；And e)：Flowable layers of copper described in etch-back, with shape
At copper interconnecting line.
Optionally, the etching gas that the etch-back uses includes H2。
Optionally, after step e), the method further includes：Etching removes the hard mask layer.
Optionally, the hard mask layer is titanium nitride layer.
Optionally, the etching gas that the step of etching removes the hard mask layer uses includes Cl2、CH4, Ar and
NF3。
Optionally, after the step of etching barrier layer is high-k dielectric material, and the etching removes the hard mask layer
Further include the steps that using etch stopper layer surface described in He gas treatment.
Optionally, between in step c) and d), the method further includes：In the trench with the hard mask layer
Upper formation diffusion barrier layer.
Optionally, the flowable layers of copper is deposited using flowability copper deposition process.
Optionally, the flowable layers of copper is copper nitride layer.
According to another aspect of the present invention, a kind of copper interconnection structure manufactured according to the above method is provided.
According to another aspect of the invention, a kind of electronic device is provided, the copper including manufacturing according to the above method is mutual
Link structure.
The manufacturing method of the copper interconnection structure provided according to the present invention is replaced CMP process using etch back process, can be subtracted
The height change of copper interconnecting line on semiconductor product caused by few CMP process, and due to being situated between caused by moisture absorption to interlayer
The damage of electric layer is also smaller.
In order to be clearer and more comprehensible objects, features and advantages of the present invention, spy lifts preferred embodiment, and in conjunction with attached drawing, does
Detailed description are as follows.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.In the accompanying drawings：
Fig. 1 a to Fig. 1 d shows and partly leads obtained in a kind of committed step of the manufacturing method of existing copper interconnection structure
The diagrammatic cross-section of body device；
Fig. 2 a to Fig. 2 e shows in the committed step of the manufacturing method of copper interconnection structure according to an embodiment of the present invention and is obtained
The diagrammatic cross-section of the semiconductor devices obtained；And
Fig. 3 shows the flow chart of the manufacturing method of copper interconnection structure according to an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
Copper interconnection structure manufacturing method.Obviously, the technical staff that execution of the invention is not limited to semiconductor field is familiar with
Specific details.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can be with
With other embodiments.
It should be understood that when the term " comprising " and/or " including " is used in this specification, indicating described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or their combination.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.
Embodiment one
In the following, describing the detailed step of the manufacturing method of copper interconnection structure proposed by the present invention referring to Fig. 2 a- Fig. 2 e and Fig. 3
Suddenly.Fig. 2 a-2e shows and partly leads obtained in the committed step of the manufacturing method of copper interconnection structure according to an embodiment of the present invention
The diagrammatic cross-section of body device.
Firstly, in step a), providing semiconductor substrate 201 with reference to Fig. 2 a.The composition material of the semiconductor substrate 201
Material can be using undoped monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI) etc..It is served as a contrast in the semiconductor
It could be formed with isolation channel, buried layer, various traps (well) structure or lower part interconnection structure in bottom 201, to put it more simply, in diagram
It is omitted.
With continued reference to Fig. 2 a, in step b), interlayer dielectric layer 202 is sequentially formed in the semiconductor substrate 201, is carved
Lose barrier layer 203 and hard mask layer 204.The interlayer dielectric layer 202 can be low k or ultra-low-k dielectric layer, and material can be
Such as silicon oxide carbide (SiOC).The etching barrier layer 203 can be high k dielectric layer, and material may include hafnium oxide, hafnium oxide
Silicon, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia
Titanium, aluminium oxide etc..The material of the hard mask layer 204 can be nitride either other composite layers with laminated construction,
Preferably titanium nitride (TiN).
With reference to Fig. 2 b, in step c), etches the hard mask layer 204, the etching barrier layer 203 and the interlayer and be situated between
Electric layer 202, to form groove 205 in the interlayer dielectric layer 202.The groove 205 defines the position of copper metal interconnection line
It sets.It will be understood by those skilled in the art that before or after etching groove 205, it can also be in the interlayer dielectric layer
Through-hole (not shown) is formed in 202, to be connected with lower part interconnection structure.
With reference to Fig. 2 c, in step d), the copper of depositing flowable in the groove 205 and on the hard mask layer 204
Layer 206.The flowable layers of copper 206 can be copper nitride layer, and thermal stability is poor, can divide at such as 200 DEG C or more
Xie Chengtong.According to one embodiment of present invention, the flowable layers of copper can be deposited using flowability copper deposition process
206.It can specifically be realized using Amber metal deposition technique.It is by the physical vaporous deposition of selectivity come deposited metal
Layer, so that the metal thicker than at the top of it in the bottom deposit of groove and/or through-hole.This can be to avoid groove and/or through-hole
Top is blocked by metal during the deposition process, causes to leave cavity below groove and/or through-hole.Later in the process of reflux
In, since capillary effect fills metal from the bottom of groove and/or through-hole to top-direction, may be implemented intact
It falls into, the filling without cavity.The vertical wide ratio of groove and/or through-hole is bigger, and filling effect is better.Therefore, the Amber metal deposit
Technology can adapt to the vertical wide ratio of smaller and smaller dimensions of semiconductor devices and interconnection line increasing therewith.
With reference to Fig. 2 d, in step e), flowable layers of copper 206 described in etch-back, to form copper interconnecting line 207.For example,
It can be using flowable layers of copper 206 described in reactive ion etching process etch-back.According to one embodiment of present invention, it uses
H2As the etching gas in etch-back step.Using H2As etching gas, the surfacing light of obtained copper interconnecting line
It is sliding, there is lower resistivity.
In one embodiment, after step e), the method may further include etching and remove the hard exposure mask
Layer 204.According to one embodiment of present invention, etching remove the step of hard mask layer 204 etching gas for using can be with
Including Cl2、CH4, Ar and NF3Deng.
In one embodiment, the etching barrier layer 203 can be high-k dielectric material, and the etching removal is described hard
Further include the steps that after the step of mask layer 204 using 203 surface of etching barrier layer described in He gas treatment.Using He gas
Handle can make the surface of the etching barrier layer 203 after etching finer and close, this can enhance half to a certain extent
Time breakdown (TDDB) characteristic of conductor device.
In one embodiment, between in step c) and d), the method be may further include：In the groove 205
Neutralize formation diffusion barrier layer (not shown) on the hard mask layer 204.It will be understood by those skilled in the art that the diffusion resistance
The effect of barrier is to prevent the diffusion and oxidation of fine copper metal, and improve the adhesive force of fine copper metal.The diffusion barrier layer can
To be titanium nitride (TiN) or tantalum nitride (TaN), the preferably such as double-layer structure of tantalum nitride (TaN) and tantalum (Ta), due to tantalum nitride
It is good to the blocking effect of fine copper metal diffusion, but binding force is poor, therefore one layer of tantalum, shape are deposited between fine copper metal and tantalum nitride
At dielectric materials-tantalum nitride-tantalum-fine copper metal structure.
The manufacturing method of the copper interconnection structure provided according to the present invention is replaced CMP process using etch back process, can be subtracted
The height change of copper interconnecting line on semiconductor product caused by few CMP process, and due to being situated between caused by moisture absorption to interlayer
The damage of electric layer is also smaller.
Fig. 3 shows the flow chart of the manufacturing method 300 of copper interconnection structure according to an embodiment of the present invention.Method 300 includes
Following steps：
Step S301：Semiconductor substrate is provided.
Step S302：Interlayer dielectric layer, etching barrier layer and hard mask layer are sequentially formed on the semiconductor substrate.
Step S303：The hard mask layer, the etching barrier layer and the interlayer dielectric layer are etched, in the interlayer
Groove is formed in dielectric layer.
Step S304：In the trench with the layers of copper of depositing flowable on the hard mask layer.
Step S305：Flowable layers of copper described in etch-back, to form copper interconnecting line.
Embodiment two
The present invention also provides a kind of copper interconnection structure, the copper interconnection structure selects method system described in above-described embodiment
It makes.The copper interconnection structure provided according to the present invention replaces CMP process using etch back process, it is possible to reduce caused by CMP process
The height change of copper interconnecting line on semiconductor product, and due to caused by moisture absorption to the damage of interlayer dielectric layer also compared with
It is small.
Embodiment three
The present invention also provides a kind of electronic devices, including copper interconnection structure described in embodiment two.Wherein, copper-connection knot
Structure is copper interconnection structure described in embodiment two, or the copper interconnection structure that the manufacturing method according to embodiment one obtains.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the copper interconnection structure.The electronic device of the embodiment of the present invention, due to having used above-mentioned copper mutual
Link structure, thus there is better performance.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (11)
1. a kind of manufacturing method of copper interconnection structure, including：
a)：Semiconductor substrate is provided；
b)：Interlayer dielectric layer, etching barrier layer and hard mask layer are sequentially formed on the semiconductor substrate；
c)：The hard mask layer, the etching barrier layer and the interlayer dielectric layer are etched, with the shape in the interlayer dielectric layer
At groove；
d)：In the trench with the layers of copper of depositing flowable on the hard mask layer；
e)：Flowable layers of copper described in etch-back, to form copper interconnecting line, the smooth surface of obtained copper interconnecting line.
2. the method according to claim 1, wherein the etching gas that the etch-back uses includes H2.
3. the method according to claim 1, wherein after step e), the method further includes：Etching
Remove the hard mask layer.
4. according to the method described in claim 3, it is characterized in that, the hard mask layer is titanium nitride layer.
5. according to the method described in claim 3, it is characterized in that, what the etching used the step of removing the hard mask layer
Etching gas includes Cl2、CH4, Ar and NF3。
6. according to the method described in claim 3, it is characterized in that, the etching barrier layer is high-k dielectric material, the etching
Further include the steps that after the step of removing the hard mask layer using etch stopper layer surface described in He gas treatment.
7. the method according to claim 1, wherein between in step c) and d), the method further includes：
Diffusion barrier layer is formed on the hard mask layer in the trench.
8. the method according to claim 1, wherein being sunk in step d) using flowability copper deposition process
The product flowable layers of copper.
9. the method according to claim 1, wherein the flowable layers of copper is copper nitride layer.
10. a kind of copper interconnection structure of the manufacture of manufacturing method described in one of -9 according to claim 1.
11. a kind of electronic device, including copper interconnection structure described in any one of claim 10.
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| US10867805B2 (en) * | 2018-06-29 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Selective removal of an etching stop layer for improving overlay shift tolerance |
| CN113403597A (en) * | 2021-06-16 | 2021-09-17 | 西安交通大学 | Zr-B-O-N film, Cu interconnection structure and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6103455A (en) * | 1998-05-07 | 2000-08-15 | Taiwan Semiconductor Manufacturing Company | Method to form a recess free deep contact |
| CN103165513A (en) * | 2011-12-08 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of interconnected structure |
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| KR20040060563A (en) * | 2002-12-30 | 2004-07-06 | 동부전자 주식회사 | Manufacture method and structure of semiconductor element |
| US20050130407A1 (en) * | 2003-12-12 | 2005-06-16 | Jui-Neng Tu | Dual damascene process for forming a multi-layer low-k dielectric interconnect |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6103455A (en) * | 1998-05-07 | 2000-08-15 | Taiwan Semiconductor Manufacturing Company | Method to form a recess free deep contact |
| CN103165513A (en) * | 2011-12-08 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of interconnected structure |
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