TW434783B - Process for integrating the copper wire and capacitor device - Google Patents

Abstract

The present invention provides a process for integrating the copper wire and capacitor device, which comprises the steps of: first providing a semiconductor substrate, the surface of the substrate having a first copper block of the lower electrode of the device used as capacitor, and a second copper block which functions as the copper conducting wire; then forming an insulating layer on top of said semiconductor substrate globally; then, selectively etching said insulating layer to form an opening for exposing said first copper block; next, forming a dielectric layer on said bottom and sidewall on said opening; selectively etching said insulating layer to form a dual damascene structure which exposes said second copper block followed by filling metal copper into said dual damascene structure and said opening at the same time, so as to form the upper electrode of the copper conducting wire and the capacitor device respectively. The process can be simplified based on the present invention without introducing the step of aluminum and copper alloy into the copper process, and thus it can form the upper electrode with a very high thickness to enhance the performance of device.

Description

434783 V. Description of the invention (1) The present invention relates to a process technology of integrated circuits (ICs), and in particular to a process of integrating a copper interconnect (Cu interconnect) and a capacitor (capacitor) process. Capacitor elements in the form of copper wires and metal insulators-metal (MIΜ). Please refer to Figure 1 to Figure 1C for a schematic cross-sectional view of the process of integrating copper conductors and capacitor elements in the conventional technology. First, please refer to FIG. 1A. Symbol 10 indicates a semiconductor substrate on which several integrated circuits have been formed. Symbols 11a and lib indicate copper blocks used as copper wires and electrodes under the capacitor element, respectively. Symbol 12 indicates formed on the semiconductor. The insulating layer on the surface of the substrate 10, and the symbol 20 represents a metal layer made of, for example, an aluminum-copper alloy. Next, referring to FIG. 1B, a lithography process and a conventional etching step are used to selectively etch the above-mentioned metal layer 20 to form Capacitance element upper electrode 20a, and then "please refer to Fig. 1C" to continue the copper process to form an intermetal dielectric layer composed of, for example, silicon dioxide. 30. Then, the above intermetal dielectric layer 30 is selectively etched to form a dual damascene structure DD with contact holes and trenches, and then copper metal is filled into the dual damascene structure DD to form a copper wire 32. Of course, Before the intermetal dielectric layer 30, a silicon nitride layer (not shown) for protecting copper metal must be formed. In addition, an interlayer dielectric layer 30 includes an etch stop layer not shown in the figure. However, 'The above-mentioned conventional technology introduces the deposition of aluminum-copper alloy, lithographic process, etching steps, etc. in the copper wire process, and then continues to return to the copper wire manufacturing process. ΊΗ ΊΗ 434783 5. Description of the invention (2) Explanation' Inconvenience and increase complexity of the process In addition, in the conventional technology, if a capacitor with a sufficient thickness is used as an electrode on the capacitor, it must take a long time to bond. In view of this, the object of the present invention is to provide a method that can be successfully performed without the need to introduce aluminum-copper alloy deposition and etching steps. Integrating the manufacturing process of the copper wire and the capacitor element can simplify the manufacturing process and reduce the cost. Furthermore, another object of the present invention is to provide an integrated copper conductor. The manufacturing process of the wire and the capacitor element can form a capacitor electrode with a very high thickness, which improves the performance of the element. According to the above purpose, the present invention provides a process of integrating a copper wire and a capacitor element, including the following steps: (a) providing a A semiconductor substrate having a first copper block serving as an electrode under the capacitor element and a second copper block serving as a copper wire on the surface of the substrate; (b) forming an insulating layer over the semiconductor substrate in a comprehensive manner (C) selectively etching the insulating layer to form an opening exposing the first copper block; (d) forming a dielectric layer on the bottom and side walls of the opening; (e) selectively etching the insulating layer, To form a dual damascene structure exposing the second copper block; and (f) simultaneously filling the dual damascene structure and the opening with steel metal to form copper wires and electrodes on the capacitor element, respectively. The invention provides a process for integrating a copper wire and a capacitor element, wherein the step of forming a copper metal protective layer is further included before forming the above-mentioned insulating layer. The copper metal protective layer is, for example, a silicon nitride layer or a silicon oxynitride layer β. In addition, in the process for integrating a copper wire and a capacitor element provided by the present invention, the above-mentioned insulating layer is formed of, for example, a first insulating layer and silicon nitride. Etching

5. Description of the invention (3) The stop layer and the second insulating layer are composed. Furthermore, in the process for integrating copper wires and capacitor elements provided by the present invention, the dielectric layer is a silicon dioxide layer or a fluorinated glass layer, and before forming the dielectric layer, it further includes forming a silicon nitride. After the step of forming the buffer layer, the step of forming the dielectric layer further includes a step of forming a tantalum nitride buffer layer to prevent copper metal from directly contacting the insulating layer such as silicon dioxide. Moreover, in the manufacturing process for integrating copper wires and capacitor elements provided in the present invention, the method of filling copper metal in step (f) is formed by, for example, the following steps: forming a copper metal layer comprehensively by an electrochemical deposition method; and then using chemical machinery The polishing method planarizes the copper metal layer to form the copper wire and the electrode on the capacitor element. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to describe in detail as follows: Brief description of the drawings: Section IA-C The figure is a schematic cross-sectional view of a conventional process for integrating copper wires and capacitor elements. Figures 2A ~ 2 £ are schematic cross-sectional views of the manufacturing process of integrated copper wires and capacitors according to an embodiment of the present invention. Explanation of symbols 100-Semiconductor substrate. 110 b to the first copper block (the electrode under the capacitive element). 110a ~ 2nd copper block (copper wire) β 120 ~ protective layer of steel metal (silicon nitride layer 130 ~ 1st insulation layer. 140 ~ etch stop

Page 7 434783 V. Description of the invention (4) layer. 150-second insulation layer. IL ~ S marginal layer. 160 ~ opening. 170 ~ 11 Fossil evening buffer layer. 180 ~ dielectric layer. 190 ~ Gasification chain buffer layer. 200a ~ copper wire. 200b ~ The electrode above the capacitor. Embodiments The cross-sectional schematic diagrams of the integrated copper wire and the capacitor element shown in Figs. 2A to 2E are used to illustrate the preferred embodiment of the present invention. First, please refer to FIG. 2A, which shows a process starting substrate for integrating a copper wire and a capacitor element according to the present invention, where the symbol 100 represents a semiconductor substrate made of, for example, single crystal silicon, and the semiconductor substrate has copper blocks formed on its surface. 110a, 110b, the above-mentioned copper block 110a is used as a copper wire, and the above-mentioned copper block 110b is used as a lower electrode of a capacitor element, which is also called a capacitor bottom metal (CBM). The symbol 120 is a copper metal protective layer composed of silicon nitride, and is used as an anti-corrosion protective layer for the lower electrode of the copper material, while the symbols 130, 140, and 150 respectively represent the first insulating layer, the etch stop layer, and the two insulating layers. The first and second insulating layers 1 30 and I 50 are made of, for example, silicon dioxide or a fluorinated glass material, and the etch stop layer 140 is made of silicon nitride or a silicon oxynitride material. Next, referring to FIG. 2B, the second insulating layer 150, the etching stop layer 14o, and the first insulating layer 130 are selectively etched to form an opening above the relative position of the copper block IIob. Until the surface of the silicon nitride buffer layer 120 is exposed, then 'Please refer to FIG. 2C, remove the protective layer 120 in the opening 160 area' to expose the surface of the copper block, and then use a low-pressure chemical gas.

Page 8 43478 3 V. Description of the invention (5) The phase deposition method sequentially forms, for example, a buffer layer 1 70 made of silicon nitride, a dielectric layer 180 made of silicon dioxide, and a buffer layer 190 made of nitride. The dielectric layer 180 may also be replaced by a silicon dioxide (Ta205) or silicon-rich silicon dioxide material. Next, referring to FIG. 2D, a conventional damascene etching step is used to form a dual damascene structure DD including a contact hole 192 and a trench 194. Finally, referring to FIG. 2E, a copper metal layer filled with the dual damascene structure DD and the trench 194 is formed by an electrochemical deposition method, and then the chemical metal polishing (CMP) is used to planarize the copper metal. Layers to form copper wires 200a and capacitor electrodes 200b respectively. At this time, not only two layers of copper wires 110a and 200a are formed, but also a capacitor element composed of copper metal-insulating layer-copper metal (Metal-Insulator-Metal) is formed. The above-mentioned capacitor element upper electrode 200b is a so-called capacitor element top metal (CTM). Features and Effects of the Invention The present invention provides a copper wire that can be successfully integrated without the need to introduce aluminum-copper alloy deposition and etching steps. And capacitor element manufacturing process, which can simplify the process and reduce costs. Furthermore, the process of integrating the copper wire and the capacitor element provided by the present invention,

Capacitor elements with extremely high thickness can be formed, thereby reducing resistance and improving element performance. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can make changes and decorations without departing from the spirit and scope of the present invention. protected range

V. Description of the invention (6) It shall be subject to the definition in the scope of the attached patent application.

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II

Claims (1)

434783 VI. Application for Patent Scope 1. A process for integrating copper wires and capacitive elements, including the following steps: (a) Provide a semiconductor substrate with a first copper block on the surface of the substrate as an electrode under the capacitive element. Used as the second copper block of the copper wire; (b) forming an insulating layer over the semiconductor substrate comprehensively; (c) selectively etching the insulating layer to form an opening exposing the first copper block; (d) ) Forming a dielectric layer on the bottom and side walls of the opening; (e) selectively etching the insulating layer to form a dual damascene structure exposing the second copper block; and (0) simultaneously on the dual damascene structure and Copper metal is filled in the above openings to form copper wires and electrodes on the capacitor element respectively. 2. The process of integrating the copper wire and the capacitor element as described in item 1 of the scope of patent application, wherein the formation of the above-mentioned insulating layer further includes forming A copper metal protective layer. 3. The process of integrating a copper wire and a capacitor element as described in item 2 of the scope of the patent application, wherein the copper metal protective layer is a silicon nitride layer. 4 · The process of integrating the copper wire and the capacitor element as described in item 2 of the scope of the patent application, in which the above-mentioned copper metal protective layer is a silicon oxynitride layer. 5. The integrated copper wire and capacitor as described in the scope of the patent application Device manufacturing process, in which the above-mentioned insulating layer is composed of a first insulating layer, an etch stop layer, and a second insulating layer. 6. The process of integrating a copper wire and a capacitor element as described in item 5 of the scope of patent application, wherein Article 〖2, the insulating layer is a fluorinated glass layer, and the above 434783 The etch stop layer is a silicon nitride layer. The 7 system of the case = = :: 1: The integrated steel wire and capacitor element described in the provisional item 6. The dielectric layer on the τ is a silicon dioxide layer. The integrated steel wire and capacitor element process described in item 8 of the eighth method of the present invention includes a step of siliconizing a buffer layer before forming the above-mentioned dielectric layer. For nitrogen attack 9, the process of integrating a sodium wire and a capacitor element as described in item 8 of the scope of the patent application, wherein after forming the dielectric layer described above, a step of forming a nitride group buffer layer is further included. 10. The process for integrating a copper wire and a capacitor element as described in item 丨 of the patent application scope, wherein the method for filling copper metal in step (f) further includes the following steps: forming a copper metal layer comprehensively by an electrochemical deposition method ; Planarizing the copper metal layer by a chemical mechanical polishing method to form the copper wire and the electrode on the capacitor element.