TWI550713B - Method for manufacturing damascene structure - Google Patents

Description

Mosaic structure

The invention relates to a manufacturing method with a mosaic structure, in particular to a method for manufacturing a mosaic structure which can improve the result of a chemical mechanical polishing (hereinafter referred to as CMP) process.

In the current semiconductor industry, damascene technology has become the main technology for multi-level interconnects in semiconductor integrated circuits. The damascene technique can be briefly described as first etching a circuit pattern in a dielectric material layer, then filling a conductive material such as copper into the circuit pattern, and removing excess conductive material by a comprehensive planarization polishing process such as CMP. And then complete the production of metal interconnects.

It is well known to those of ordinary skill in the art that the surface shape of the abrasive film layer and the pattern density of the surface of the abrasive film layer have a significant effect on the results of the CMP process. For example, when the pattern density on the surface of the abrasive film layer is not uniform, the polishing rate of the CMP process may vary depending on the pattern density, resulting in uniformity of the uniformity of the surface of the abrasive film layer, or even dishing. Effects and other issues.

However, since the CMP process has long been the main way to achieve comprehensive flattening in the semiconductor industry, how to improve the above-mentioned uniformity and shallow disc caused by different pattern densities is an important issue in the semiconductor process.

Accordingly, it is an object of the present invention to provide a method of fabricating a damascene structure that can effectively improve the results of a CMP process.

The invention provides a method for fabricating a damascene structure. The fabrication method first provides a substrate, and a dielectric layer is formed on the substrate. Forming at least one trench, at least one via, and at least one dummy via in the dielectric layer, and then forming a first conductive layer on the substrate, and the The first conductive layer fills the trench, the via hole, and the dummy via hole. After forming the first conductive layer, a chemical mechanical polishing process is performed to form the damascene structure while removing the dummy via holes.

According to the method for fabricating a mosaic structure provided by the present invention, a plurality of dummy via holes are formed on a substrate to improve pattern uniformity of the surface of the substrate, thereby improving the result of the CMP process and avoiding the problem of the shallow dish. A surface of the substrate having good flatness is obtained. When the damascene structure is formed by the CMP process, the dummy via holes are completely removed to avoid the influence of the dummy via holes in the subsequent process. More importantly, the dummy via hole provided by the present invention can be disposed in a dummy-blocking region where the dummy via hole is prohibited from being disposed, and due to the dummy via hole Can be removed by the CMP process, so after the CMP process, the dummy component barrier region still meets the process or product requirements without any dummy via holes. In other words, the method for fabricating the damascene structure provided by the present invention can effectively improve the result of the CMP process without obtaining the requirements of the product, and obtain the surface of the substrate having excellent flatness.

Please refer to FIG. 1 to FIG. 5 . FIG. 1 to FIG. 5 are schematic diagrams showing a first preferred embodiment of a method for fabricating a mosaic structure according to the present invention. As shown in FIG. 1, the preferred embodiment first provides a substrate 100, such as a germanium substrate, a germanium-containing substrate, or a silicon-on-insulator (SOI) substrate. It should be noted that the dummy substrate blocking region 110 and the general component region 112 are defined on the substrate 100 in the preferred embodiment. The dummy element barrier region 110 is within the product, such as within a Micro Electro Mechanical Systems (MEMS) device, specifically defined as an area that does not allow for any dummy component placement. The substrate 100 includes a conductive layer 102 therein, and the substrate 100 further includes a bottom layer 104 covering the conductive layer 102. In the preferred embodiment, the conductive layer 102 comprises a conductive member of a metal material or a doped semiconductor material, a doped region, a gate, etc., and the bottom layer 104 comprises nitrogen-doped tantalum carbide ( Dielectric materials such as nitrogen-doped silicon carbide (NDC). In addition, the substrate 100 further includes an inter-metal dielectric (IMD) layer 106 or an inter-layer dielectric (ILD) layer (not shown), and as shown in FIG. The IMD layer 106 covers the bottom layer 104. The IMD layer 106 may comprise a low dielectric constant (low-k) material (dielectric constant value less than 3.9) and an ultra low-k (ULK) material (dielectric constant value less than 2.6). Or a porous ultra low dielectric constant (porous ULK) material. Since the low dielectric constant material, the ULK material and the porous ULK material are both less dense and less structurally strong, the preferred embodiment selectively forms a composite film layer 108 on the surface of the IMD layer 106. The composite film layer 108 includes at least a metal hard mask 108a. Further, the composite film layer 108 may further comprise a silicon oxynitride (SiON) layer 108b and silicon monoxide (silicon oxide) as shown in FIG. Oxide, SiO) layer 108c. The metal hard mask 108a may be a single layer structure or a composite film layer structure, and is selected from titanium (titanium, Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride. Group of (tantalum nitride, TaN). For example, the metal hard mask 108a provided in the preferred embodiment may include a composite film layer of Ti/TiN or Ta/TaN, but is not limited thereto. It is also worth noting that since the metal hard mask 108a has a stress with respect to the IMD layer 106, in the preferred embodiment, the ruthenium oxide layer 108c in the composite film layer 108 can be used as the metal hard mask 108a and the IMD layer. The buffer layer between 106 prevents the IMD layer 106 from being directly affected by the stress of the metal hard mask 108a. In addition, the preferred embodiment may also form an anti-reflective coating (ARC) (not shown) on the metal hard mask 108a, which may include a dielectric material such as SiON or TEOS, but is not limited thereto. .

Please continue to see Figure 1. Next, a patterned photoresist 120 is formed on the composite film layer 108. The patterned photoresist 120 includes a plurality of openings for defining a trench pattern of the embedded wires. After the patterned photoresist 120 is formed, an etching process 122 is performed, and the patterned photoresist 120 is used as an etch mask, and the composite film layer 108 and the portion of the IMD layer 106 are etched downward through the opening of the patterned photoresist 120. A trench 126 is formed in the upper half of the IMD layer 106 in the general component region 223.

Please refer to Figure 2. After the trench 126 is formed, the patterned photoresist 120 can be removed by means of oxygen plasma or the like. Next, a patterned photoresist 130 is formed on the substrate 100. The patterned photoresist 130 includes a plurality of openings 132a, 132b. The openings 132a are formed in the general component region 112 on the substrate 100, especially the trench. Within 126, a via pattern for defining the inlaid wires. It should be noted that the patterned photoresist 130 in the preferred embodiment further defines a plurality of dummy via patterns in the dummy element blocking region 110 by using the opening 132b. After forming the patterned photoresist 130, an etching process 134 is performed, and the patterned photoresist 130 is used as an etch mask, and the dummy element blocking region 110 is etched downward through the openings 132a and 132b of the patterned photoresist 130. The composite film layer 108 and a portion of the IMD layer 106 and the IMD layer 106 at the bottom of the trench 126.

Please refer to Figure 3. After the etching process 134, the preferred embodiment forms a via 136 in the IMD layer 106 at the bottom of each trench 126, and stops at the surface of the bottom layer 104, while the IMD layer 106 in the dummy element barrier region 110. The upper half forms a dummy via 138. Finally, the patterned photoresist 130 can be removed by means of oxygen plasma or the like. It is worth noting that the via 136 at the bottom of the trench 126 has a depth D; and the dummy via 138 in the dummy barrier region 110 has a depth D', since the via 136 is directly The etched IMD layer 106 is obtained, and the dummy via 138 is first etched and the IMD layer 106 is etched, so that the dummy via depth D' is less than or equal to the via depth D. Additionally, as shown in FIG. 3, the dummy via 138 and the via 136 are not coplanar.

Please refer to Figure 4. After the fabrication of the trench 126 and the via 136 is completed, the bottom layer 104 at the bottom of the via 136 can be removed by a suitable etching process, and the conductive layer 102 is exposed at the bottom of the via 136. Subsequently, a barrier layer (not shown) and a conductive layer 140 filling the trench 126, the via 136, and the dummy via 138 are formed in the trench 126 and the via 136.

Please refer to Figures 4 and 5. After forming the conductive layer 140, a CMP process 150 is performed. The CMP process 150 first removes the excess conductive layer 140 on the substrate 100 and then continues to remove the conductive layer 140 and the composite film layer 108. For example, the conductive layer 140 removed by the CMP process 150 and the composite film layer 108 have a polishing height H ₁ . It should be noted that the CMP process 150 provided in the preferred embodiment further removes the portion of the conductive layer 140 and the portion of the IMD layer 106 after removing the composite film layer 108 to expose the IMD layer 106 until it is dummy. The dummy vias 138 in the element barrier region 110 are all removed as shown in FIG. In detail, the portion of the conductive layer 140 removed by the CMP process 150 and the portion of the IMD layer 106 have a buffer height H ₂ , and to ensure that the dummy via 138 is completely removed, the buffer height H ₂ is greater than the dummy dielectric. Hole depth D'. While the dummy via 138 is removed, the preferred embodiment forms a damascene conductor 160 in the general component region 112.

According to the method for fabricating the inlaid wire provided by the preferred embodiment, a trench first process is employed. When the via hole 136 is formed, a plurality of dummy via holes 138 are simultaneously formed in the dummy device barrier region 110. Therefore, when the damascene wire 160 is formed in the CMP process 150, the dummy via hole 138 can be used to improve the IMD layer. 106 The problem of uneven surface pattern density, and thereby improving the result of the CMP process 150, to avoid the occurrence of the problem of the shallow dish, especially to avoid the problem of the occurrence of the shallow dish in the dummy element blocking region 110, thereby obtaining a good flatness. The surface of the substrate.

Please refer to FIG. 6 to FIG. 10 . FIG. 6 to FIG. 10 are schematic diagrams showing a second preferred embodiment of a method for fabricating a semiconductor integrated circuit according to the present invention. It should be noted that the same components of the second preferred embodiment as those of the first preferred embodiment may be the same materials, and therefore will not be further described below. As shown in FIG. 6, the preferred embodiment first provides a substrate 200, and a dummy element blocking region 210 and a general device region 212 are defined on the substrate 200. The substrate 200 includes a conductive layer 202 therein, and the substrate 200 includes a bottom layer 204 and an IMD layer 206 in sequence. The preferred embodiment can also form a composite film layer 208 on the surface of the IMD layer 206. The composite film layer 208 includes at least one metal hard mask 208a. Further, the composite film layer 208 further includes a ruthenium oxynitride layer 208b and a ruthenium oxide 208c as shown in FIG. Since the metal hard mask 208a has a stress with respect to the IMD layer 206, in the preferred embodiment, the ruthenium oxide layer 208c in the composite film layer 208 can serve as a buffer layer between the metal hard mask 208a and the IMD layer 206. The IMD layer 206 is prevented from being directly affected by the stress of the metal hard mask 208a. In addition, the preferred embodiment can also form an anti-reflection layer (not shown) on the metal hard mask 208a.

Please continue to see Figure 6. Next, a patterned photoresist 220 is formed on the composite film layer 208, and the patterned photoresist 220 includes a plurality of openings. It should be noted that the openings in the general device region 212 are used to define the via pattern of the embedded wires; and the preferred embodiment further defines a plurality of dummy via patterns in the openings in the dummy barrier region 210. . After forming the patterned photoresist 220, an etching process 222 is performed, and the patterned photoresist 42 is used as an etch mask, and the composite film layer 208 and the portion of the IMD layer 206 are etched downward through the opening of the patterned photoresist 220. A via opening 226a is formed in the upper half of the IMD layer 206 in the general device region 212, and a dummy via hole 228 is formed in the upper half of the IMD layer 206 in the dummy device blocking region 210. It should be noted that the via opening 226a in the preferred embodiment has a depth D"; and the dummy via 228 in the dummy barrier region 210 has a depth D' and a dummy via The hole depth D' is equal to the opening depth D" of the via hole. In addition, as shown in FIG. 6, the dummy via hole 228 is coplanar with the via hole opening 226a.

Please refer to Figure 7. After the via opening 226a and the dummy via 228 are formed, the patterned photoresist 220 is removed by means of oxygen plasma or the like. Next, a patterned photoresist 230 is formed on the substrate 200. The patterned photoresist 230 includes a plurality of openings 232 for defining a trench pattern of the embedded wires in the general device region 212. It is worth noting that the patterned photoresist 230 covers the dummy element barrier region 210, and in particular fills the dummy via hole 228. After forming the patterned photoresist 230, an etching process 234 is performed, and the patterned photoresist is used as an etch mask to etch the composite film layer in the general device region 212 through the opening 232 of the patterned photoresist 230. 208 is exposed to a portion of the IMD layer 206 within the via opening 226a.

Please refer to Figure 7 and Figure 8. After the etching process 234, the preferred embodiment forms a trench 236 as shown in FIG. 8 in the IMD layer 206 in the general component region 212, which corresponds to the opening 232, respectively. In addition, the etching process 234 transfers the via opening 226a to the lower half of the IMD layer 206, thereby forming a via 226 as shown in FIG. 7 at the bottom of the trench 236. It should be noted that when the etching process 234 is performed, the dummy via holes 228 in the dummy element blocking region 210 are covered and protected by the patterned photoresist 230, and thus are not affected. Finally, the patterned photoresist 230 can be removed by means of oxygen plasma or the like. As shown in FIG. 8, the dummy via hole 228 in the dummy element barrier region 210 has a depth D', and the via hole 226 in the general device region 212 obtains a depth D and a dummy via hole. The depth D' is less than or equal to the depth D of the via. In addition, as shown in FIG. 8, the dummy via 228 and the via 226 are not coplanar.

Please refer to Figure 9. After the fabrication of the trench 236 and the via 226 is completed, the conductive layer 202 can be exposed by removing the underlayer 204 at the bottom of the via 226 by a suitable etching process. Subsequently, a barrier layer (not shown) and a conductive layer 240 filling the trench 236, the via 226, and the dummy via 228 are formed in the trench 236 and the via 226.

Please refer to Figure 9 and Figure 10. After forming the conductive layer 240, a CMP process 250 is performed. The CMP process 250 first removes the excess conductive layer 240 on the substrate 200 and then continues to remove the conductive layer 240 and the composite film layer 208. For example, the conductive layer 240 removed from the CMP process 250 and the composite film layer 208 have a polishing height H ₁ . It should be noted that the CMP process 250 provided in the preferred embodiment further removes the portion of the conductive layer 240 and the portion of the IMD layer 206 after removing the composite film layer 208 to expose the IMD layer 206 until the dummy layer is removed. The dummy via holes 228 in the element barrier region 210 are all removed as shown in FIG. In detail, the portion of the conductive layer 240 removed from the CMP process 250 and the portion of the IMD layer 206 have a buffer height H ₂ , and to ensure that the dummy via hole 228 is completely removed, the buffer height H ₂ is greater than the dummy dielectric. Hole depth D'. While the dummy via 228 is removed, the preferred embodiment further forms a damascene conductor 260 in the general component region 212.

According to the method for fabricating the inlaid wire provided by the preferred embodiment, a partial-via first process is employed. When the via hole opening 226a is formed, a plurality of dummy via holes 228 are simultaneously formed in the dummy device blocking region 110. Therefore, when the damascene wire 260 is formed in the CMP process 250, the dummy via hole 228 can be used to improve the IMD. The problem that the surface pattern density of the layer 206 is uneven, and the result of the CMP process 250 is improved, so as to avoid the problem of the shallow dish, especially the problem of the occurrence of the shallow dish in the dummy element blocking region 110, thereby obtaining a good flatness. The surface of the substrate.

In addition, it should be noted that although the present invention only discloses the trench priority process and the via hole priority process, those skilled in the art should be aware of other processes commonly used in the damascene process, such as via-first process and self-management. The self-aligned process, etc., may also employ the steps disclosed above to improve the CMP process results.

According to the method for fabricating the mosaic structure provided by the present invention, a plurality of dummy via holes are formed on the substrate on the substrate, so as to improve the pattern uniformity of the surface of the substrate, thereby improving the large area of the space. The area is the result of the CMP process, as well as avoiding the occurrence of shallow dish problems and obtaining a substrate surface with good flatness. While forming the damascene structure by using the CMP process, the dummy via holes are removed to avoid the influence of the dummy via holes in the subsequent process. More importantly, the dummy via hole provided by the present invention can be disposed in a dummy element blocking region where the dummy via hole is prohibited from being disposed, for example, a dummy defined on a wafer including a microelectromechanical system (MEMS). The component is in the barrier region, and since the dummy via holes can be removed by the CMP process, after the CMP process, the dummy component barrier region still meets the process or product requirements without including any dummy vias. hole. In other words, the method for fabricating the damascene structure provided by the present invention can effectively improve the result of the CMP process without obtaining the requirements of the product, and obtain the surface of the substrate having excellent flatness.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Base

102. . . Conductive layer

104. . . Bottom layer

106. . . Metal interlayer dielectric layer

108. . . Composite film

108a. . . Metal hard mask

108b. . . Niobium oxynitride layer

108c. . . Cerium oxide layer

110. . . Virtual component barrier

112. . . General component area

120. . . Patterned photoresist

122. . . Etching process

126. . . ditch

130. . . Patterned photoresist

132a. . . Opening

132b. . . Opening

134. . . Etching process

136. . . Via hole

138. . . Virtual interlayer hole

140. . . Conductive layer

150. . . Chemical mechanical polishing process

160. . . Mosaic wire

200. . . Base

202. . . Conductive layer

204. . . Bottom layer

206. . . Metal interlayer dielectric layer

208. . . Composite film

208a. . . Metal hard mask

208b. . . Niobium oxynitride layer

208c. . . Cerium oxide layer

210. . . Virtual component barrier

212. . . General component area

220. . . Patterned photoresist

222. . . Etching process

226. . . Via hole

226a. . . Interlayer opening

228. . . Virtual interlayer hole

230. . . Patterned photoresist

232. . . Opening

234. . . Etching process

236. . . ditch

240. . . Conductive layer

250. . . Chemical mechanical polishing process

260. . . Mosaic wire

D. . . Via depth

D’. . . Virtual interlayer depth

D"...interlayer opening depth

H ₁ . . . Grinding height

H ₂ . . . Buffer height

1 to 5 are schematic views showing a first preferred embodiment of a method of fabricating a semiconductor integrated circuit provided by the present invention.

6 to 10 are schematic views showing a second preferred embodiment of a method of fabricating a semiconductor integrated circuit provided by the present invention.

100. . . Base

102. . . Conductive layer

104. . . Bottom layer

106. . . Metal interlayer dielectric layer

108. . . Composite film

108a. . . Metal hard mask

108b. . . Niobium oxynitride layer

108c. . . Cerium oxide layer

110. . . Virtual component barrier

112. . . General component area

126. . . ditch

136. . . Via hole

138. . . Virtual interlayer hole

140. . . Conductive layer

150. . . Chemical mechanical polishing process

D. . . Via depth

D’. . . Virtual interlayer depth

H ₁ . . . Grinding height

H ₂ . . . Buffer height

Claims (13)

A method for fabricating a damascene structure, comprising: providing a substrate, wherein a dielectric layer is formed on the substrate; forming a first patterned photoresist on the substrate for defining at least one via and at least one dummy a dummy via; performing a first etching process to form at least one via opening and the dummy via in the dielectric layer; after the first etching process, in the dielectric layer Forming the via hole and the at least one trench; forming a first conductive layer on the substrate, and the first conductive layer fills the trench, the via hole, and the dummy via hole; A chemical mechanical polishing process is used to form the damascene structure while removing the dummy via holes. The manufacturing method of claim 1, wherein the substrate further comprises a second conductive layer. The manufacturing method of claim 2, wherein the second conductive layer is exposed to the bottom of the via hole. The manufacturing method of claim 1, wherein the via opening is coplanar with the dummy via. The manufacturing method of claim 1, wherein the step of forming the trench further comprises: forming a second patterned photoresist on the substrate to define the trench; and performing a second etching process to The trench is formed in the dielectric layer, and the via opening is transferred into the dielectric layer at the bottom of the trench to form the via. The manufacturing method of claim 5, wherein the second patterned photoresist fills the dummy via hole. The manufacturing method of claim 1, further comprising the step of forming a composite film layer on the surface of the dielectric layer, before forming the via hole opening and the dummy via hole. The manufacturing method of claim 7, wherein the composite film layer comprises at least one metal hard mask. The manufacturing method of claim 1, wherein the via hole is formed to be not coplanar with the dummy via hole. The manufacturing method of claim 1, wherein the depth of the dummy via hole is less than or equal to the depth of the via hole. The manufacturing method of claim 10, wherein the CMP process further removes a portion of the first conductive layer and a portion of the dielectric layer, and the removed portions of the first conductive layer and a portion of the dielectric layer The electrical layer has a buffer height. The manufacturing method of claim 11, wherein the buffer height is greater than the depth of the dummy via hole. The manufacturing method of claim 1, wherein the substrate defines a dummy-blocking region, and the dummy via hole is formed in the dummy element blocking region.