TW436996B - Method for decreasing the damage of the damascene copper interconnect - Google Patents

Abstract

The present invention discloses a method for decreasing the damage of the damascene copper interconnect. After forming a first copper layer by the conventional method, a second copper layer is formed by using electroplating method with ionized metal plasma to fill the recess or crack in the first copper layer, thereby easing the subsequent chemical mechanical polishing process. Therefore, the polished surface is more planar and has less defect and damage. As a result, the quality of the damascene copper interconnect is enhanced and the performance of the device is increased.

Description

436 9 9 6 V. Description of the invention (1) The present invention relates to a semiconductor process technology, and in particular to a method for reducing damage to a damascene copper interconnect in a chemical mechanical polishing process "in recent years In order to match the development of component size reduction and the need to increase the speed of component operation, "copper metal with low resistance constant and high electron migration resistance" has been gradually used as the material of metal interconnects, replacing the previous Ming metal process. technology. Copper metal's mosaic (also dual-mosaic) interconnect technology can not only reduce the interconnect size and reduce the Rc time delay, but also solve the problem of difficult copper metal etching, so it has become the current multiple interconnects. Major development trends. The feature of this process is that a dielectric layer is formed on a semiconductor substrate, and the damascene structure is defined by this process. Next, the metal copper layer is covered on the dielectric layer, and the damascene structure is filled. After that, the CMP method is used to grind and remove the excess copper layer on the dielectric layer to complete a mosaic copper interconnect. Figures 1A to 1D are cross-sectional views showing the manufacturing process of a conventional inlay copper interconnect. First, please refer to Figure IX, which shows a component area 12 formed on a hair substrate 10 in order. And a dielectric layer 14, and a trench n is formed in the dielectric layer 14 through a lithography and etching process. Please refer to FIG. 16, forming a barrier layer 16 ′ on the surface of the dielectric layer 14 and covering the inner wall of the trench T1. It belongs to 2, see Figure 1C, it is formed on the surface of the barrier layer 16-gold = two; Ϊ groove T1. The point to note here is that metal copper produces ^ an ionized metal plasma (IMP) on the surface of the barrier layer 16 forms a seed layer (not shown in the figure);

Page 4 436 y 9 6 V. Description of the invention (2) The metal copper layer 18 formed on the surface of the seed layer by the plating method (ECP). However, the surface of the metal copper layer formed by this method is not flat (Planar), but instead has pinholes or even surface cracks, which affects the mosaic type formed by subsequent chemical mechanical polishing (CMP). The surface of the copper interconnecting wire 181 is broken or peeled, as shown in FIG. Ij). The occurrence of this situation seriously affects the quality of copper interconnects, and even affects the performance of the device. -Considering how this line is formed, the performance is impaired during the grinding process. The purpose of the present invention is to reduce the inlay and thereby improve the quality of the copper inner connection. The inlay copper is connected to the chemical mechanical research and to improve the components. In order to achieve the present invention, = ^ Available—A method for reducing inlaid steel interconnecting plates and buckling to the semiconductor substrate, which is applicable to a semiconductor substrate. The surface of the surface of the dielectric layer forms a dielectric layer with a trench. The first metal copper layer forms a barrier layer when it is dry, including the following steps: forming a second metal copper layer on the surface of the second barrier layer and filling the trench; forming a metal copper layer, and the first metal: metal copper The surface of the layer Φ; and, • Is the second to the exposure of the surface layer of the dielectric layer and the chemical mechanical polishing of the barrier layer? Among them, the second Jin Licheng has a cavity on the rear surface to make the layer system to fill in the first metal layer grinding. It uses the amount of j to reach the level of the surface to facilitate the formation of ions on the surface of the subsequent chemical mechanical metal copper layer. The metal plasma is electroplated on the first

.436996 V. Description of the invention (3) A metal plasma is used to form a seed layer on the surface of the barrier layer; a chemical metal chain method is used to form a first metal copper layer on the surface of the seed layer. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easy, only a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: Figures 1A-1D Is a sectional view showing the manufacturing process of a conventional inlaid copper interconnect; Figures 2A to 2E are sectional views showing the manufacturing process of a mosaic inlaid copper interconnect according to the present invention; and Figures 3A and 3B show the conventional and Pattern of a mosaic copper wire formed by the method of the present invention under a scanning electron microscope (SEM). Symbol descriptions 10, 20 ~ silicon substrate; 12, 22 ~ element area; 14, 24 ~ dielectric layer; 16, 26 ~ barrier layer; 18, 28 ~ ECP copper; 181, 28 inlaid copper interconnects; 29-IMP copper; Ti, T2 ~ trench. EXAMPLES FIGS. 2A to 2E are cross-sectional views showing a manufacturing process of a buried copper interconnect according to the present invention. Please note here that the manufacture of such copper interconnects can also be applied to dual damascene copper processes, but in this embodiment, the damascene process is used as an example, but this does not affect its scope limit.

Page 6 4 '436 9 9 6 V. Description of the Invention (4) --------- First, please refer to FIG. 2A, which is shown on a semiconductor substrate 20, such as a silicon substrate, The element region 22 and a dielectric layer are sequentially formed. The components in the component area can be formed as required, so they are not drawn in detail in the figure. The material of the electrical layer 24 may be silicon oxide, silicon nitride, borophosphosilicate glass, or tetraethoxysilicate, such as a silicon oxide layer formed by plasma enhanced chemical vapor deposition (PECVD). 'Its thickness is generally between 4k lka. After lithography and etching processes, a trench T2 is formed in the dielectric layer 24. Next, refer to FIG. 2B, which is formed on the surface of the dielectric layer 24—a metal that can help subsequent formation. The attached barrier layer 26 covers the inner wall of the trench T2. For example, a magnetron DC sputtering method is used to 'deposit a titanium metal layer (not shown) on the surface of the silicon oxide layer 24, and then place it in an environment containing nitrogen (NO or ammonia (NH3)). After the high-temperature nitridation of the titanium nitride layer 26, the first step is to form a first metal copper layer on the surface of the barrier layer 26 and fill the trench T2; for example, an ionized metal plasma (IMP ) A seed layer (not shown in the figure) is formed on the surface of the titanium nitride layer 26; and then a chemical plating method (ECP) is used to form a seed layer on the surface of the seed layer with a thickness of approximately 6k ~ L0k A. A metal copper layer 28 (hereinafter referred to as ECP copper for short) has a plurality of recesses on its surface, and its condition is shown in FIG. 2C. Next, what is to be performed is a key step of the present invention, that is, forming a The second metal copper layer is on the surface of the first metal copper layer 28; for example, 'Please refer to FIG. 2D, using an ionized metal plasma (IMP) to form a first metal copper layer 28 by electroplating. Bimetallic copper layer 29 (IMP copper

· '43699 6 V. Description of the invention ⑸' Call it), and its thickness is generally between lk ~ 2k A, to fill the cavity generated by the process on the surface of the Ecp copper metal layer 28 to facilitate subsequent flatness The step of forming is used to form metal copper interconnects of good quality, thereby improving device performance. After that, “δcyan see FIG. 2E” is a conventional planarization step, which is to perform chemical mechanical polishing (CMP) of the second metal copper layer 29, the first metal copper layer 28, and the barrier layer 26 until the surface is exposed. A structure of a mosaic copper interconnect 281 is formed up to the surface of the dielectric layer 24. Next, please refer to FIG. 3A and FIG. 3B, which show the SEM patterns of the inlaid copper wires formed by the conventional method and the method according to the present invention; The copper wire is not flat and has multiple recesses; and the copper wire shown in Figure 3B can be used because there is still an Imp metal copper layer formed after the conventional metal copper layer is formed. In order to fill the depressions on the surface of the conventional metal copper layer, the surface of the formed metal copper wire is relatively flat. Next, please refer to the data listed in Table 1 and Table 2, which respectively show the surface roughness (roughness) and film roughness of the ECP copper and IMP copper (excluding ECP copper) produced according to different processes before and after cleaning. The RMS value of the vertical height difference is a flat surface distribution observed under an atomic force microscope (AFM). From these data, we can know that the surface roughness of ECP copper is more serious than that of IMP copper, and the values are more than ten times different. The difference in height of IMP copper is also much better than ECP copper. In addition, the cleaning step is also a significant factor affecting the flatness of the surface.

Page 8 r 436996 ______________________ 5. Description of the invention (6) The surface is damaged, so the difference between the roughness and vertical height of ECP copper or IMP copper before cleaning is better than that after cleaning. Table 1 Thickness of thin film cleaning step (magic straight height difference (A) ECP Copper No. 4 97 525.18 ECP ^ Yes 132.39 1092 Table 2 Thin film type cleaning step Roughness (again) Straight height difference (A ) Industrial MP shot 8.65 3 8.05 Industrial MP steel is 9.59 —_ 4 1.85 Method 2 Please refer to Table 3, which shows the surface roughness and perpendicularity of the bond film formed according to the conventional and the solution of the present invention ^ CP ^ , 10kA,, IMP,: No, the method according to the present invention has a lower degree of expression than the conventional method, and the roughness of the U-line vertical connection is much lower than the conventional difference. ; According to :: the difference in hair J's inlaid copper internal connection surface is relatively flat: the method formed by the method is better. Standing is better than the conventional method 1 436 9 9 6 ^, V. Description of the invention (7 ) Table 3 Film Type Roughness (A) Silk Straight Height Difference (A) ECP Copper (¾ Known) 76.77 755.22 ECP 婀 + IMP Copper (Invention) _ 70.45 85.73 Although the present invention has been disclosed as above with preferred embodiments, then It is not intended to limit the present invention > Anyone skilled in the art ' does not depart from the spirit and scope of the present invention When alterations and modifications may be made 'and the scope of the present invention shall be defined depending on when the norm patent, whichever solid.

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Claims (1)

ί 436996 "-Six 'Application Patent Scope 1-A method for reducing damage to the mosaic copper interconnects, applicable to a semiconductor substrate' and forming a dielectric layer with a trench on the surface of the semiconductor substrate 'the Forming a barrier layer on the surface of the dielectric layer includes the following steps: forming a first metal copper layer on the surface of the barrier layer and filling the trench; forming a second metal copper layer on the first metal copper The surface of the layer; and chemically and mechanically polishing the second metal copper layer, the first metal copper layer, and the barrier layer until the surface of the dielectric layer is exposed. 2. The method according to item 1 of the patent application park, wherein the second metal copper layer meter is formed on the surface of the first metal copper layer by electroplating using an ionized metal plasma, and the thickness is approximately lk ~ Between 2k A. 3. The method according to item 2 of the scope of patent application, wherein the method for forming the first metal copper layer further includes the following steps: using an ionized metal plasma to form a thickness of approximately 1 k on the surface of the barrier layer. A seed layer between ~ 2 k A; and forming a first metal copper layer with a thickness of approximately 6 k ~ 2O k A on the surface of the seed layer by a chemical plating method. 4. The method as described in item 3 of the scope of patent application, wherein the structure of the copper interconnect is suitable for a pair of inlay ring copper processes. 5. The method according to item 4 of the scope of patent application, wherein the material of the barrier layer can be a button, silver nitride, or titanium nitride, and the thickness is generally between 200 and 500 A. 6. The method according to item 5 of the scope of patent application, wherein the material of the dielectric layer can be oxidized shard, silicon nitride, borophosphosilicate glass, or Article 11 ^ 36 9 9 6 6. Scope of Patent Application Ethoxy silicate, and its thickness is generally between 4k ~ 10k Α. 7. The method according to item 6 of the scope of patent application, wherein the semiconductor substrate is a substrate. 8. — A method for reducing the damage of the mosaic copper interconnects, applicable to a semiconductor substrate, and a dielectric layer having a trench is formed on the surface of the semiconductor substrate, and a resistance is formed on the surface of the dielectric layer. The barrier layer includes the following steps: forming a seed layer on the surface of the barrier layer by using an ionized metal plasma; forming a first metal copper layer on the surface of the seed layer by using a chemical plating method; using an ionized metal electrode Forming a second metal copper layer on the surface of the first metal copper layer by electroplating; and performing chemical mechanical polishing on the second metal copper layer, the first metal copper layer, and the barrier layer to expose the dielectric layer So far. 9. The method according to item 8 of the scope of patent application, wherein the thickness of the second metal copper layer is generally between lk and 2k A. 10. The method according to item 9 of the scope of patent application, wherein the thickness of the seed layer is generally between lk and 2k A. Π. The method according to item 10 of the scope of patent application, wherein the thickness of the first metal copper layer is generally between 6k and 20k A. 1 2. The method according to item 11 of the scope of patent application, wherein the structure of the copper interconnects is suitable for a double inlay copper process. 13. The method according to item 12 of the scope of patent application, wherein: Page 12 Λ36996 6. Scope of patent application The material of the barrier layer can be tantalum, tantalum nitride, or titanium nitride, and its thickness is generally between 200 and 500 A. 14. The method according to item 13 of the scope of patent application, wherein the material of the dielectric layer may be silicon oxide, silicon nitride, borophosphosilicate glass, or tetraethoxysilicate, and The thickness is generally between 4k ~ 10k A. 15. The method according to item 14 of the scope of patent application, wherein the semiconductor substrate is a substrate. Page 13