TW469591B - Fabrication method of dual damascene - Google Patents

Abstract

The present invention provides a fabrication method of dual damascene with low-k dielectric layer, which comprises the following steps: forming an adhesive layer and a first low-k dielectric layer on the upper surface of conducting plugs on a semiconductor substrate in sequence, remove part of the first low-k dielectric layer to form a dielectric hole, form a second low-k dielectric layer on the first low-k dielectric layer and fill the dielectric hole, remove part of the second low-k dielectric layer and the adhesive layer to form a trench, and expose part of the upper surface of the conducting plugs, and finally form a barrier layer, seeding layer, and metal thin film on the second low-k dielectric layer, and fills the trench.

Description

469591 V. Description of the invention (1) Field of the invention: Off, manufacturing process The present invention and a method for forming a dual damascene in a semiconductor process are particularly related to a dual damascene with a low dielectric constant dielectric layer. Background: The operating speed of semiconductor devices and the reliability of semiconductor devices are improved. The aluminum metal or aluminum alloy (such as silicon copper alloy or aluminum steel alloy) used in the connection structure of traditional semiconductor processes has gradually become more conductive and resistive. It is replaced by copper metal with lower rate and lower electromobility. In the copper process technology, 'the steel cannot be etched with gas like aluminum alloy', so the industry has developed a damascene process. The current damascene process method includes a single damascene process or a dual damascene process. The technology of the dual damascene structure can be used to synchronize the trench connection on the semiconductor substrate and the conductive plug connected to the semiconductor substrate. Mosaic process technology can refer to "Method for manufacturing a low dielectric constant inter-level integrated circuit structure" disclosed by Motorol a Company, Boeck; Bruce Alle et al. In U.S. Patent No. 58800 1 8.

Page 4 469591 V. Description of the invention (2) In addition, in the C MOS process with a thickness of 0.18 microns or less, the interlayer dielectric layer can usually be used with a low dielectric constant (10wk). The material replaces the original silicon oxide to reduce the coupling capacitance between the metal interconnects, thereby reducing the resistance-capacitance hysteresis. The dielectric constant (K value) of the low dielectric constant (l0w-k) material selected here is less than about 3, which includes FSG,

Si LK, FLARE, etc. In addition, when an organic low-k material is used as the inner metal dielectric layer (Inter ~ Mediate Die 1 ec 1; rics' IMD), a silicon carbide (S i C) or Nitride (S i M) to enhance the adhesion of the inner metal dielectric layer. Take the first picture to the second picture as examples to illustrate the manufacturing method of the traditional dual copper damascene structure using low-k material as the interlayer dielectric layer. Please refer to the first picture A dielectric layer 1 2 ′ is formed on the semiconductor substrate 10 after the previous process is completed to generate an insulating effect. Then, a contact hole (or trench, contact hole, via / trench, contact / via hole) can be defined on the dielectric layer 12 by conventional lithography and etching techniques, and by using a chemical vapor phase A deposition method, or a physical vapor deposition or electroplating method such as a sputtering process, is used to form a conductive plug 14 in a contact hole. ^ ^ Subsequently, a first silicon nitride layer 16 and a first low dielectric constant are sequentially formed. Eight electrical layers 18, a second gasification fragmentation layer 20, and a second low dielectric constant dielectric wide

419591 V. Description of the invention (3) The opening 23 shown in the first figure is formed by two successive lithography and etching techniques. Next, please refer to the second figure to form a copper thin film by physical vapor deposition (PVD), chemical vapor deposition (CVD), or electric money method, and then use chemical mechanical polishing method. (Chemical Mechanical Polishing; CMP) grinding the copper thin film to form a copper wire 24 »Because the above-mentioned low dielectric constant (l0w_k) material used as the interlayer dielectric layer is formed by a spin coating method, as for Its K value is less than about 2.7, so the texture is softer. 'When using a chemical mechanical polishing reaction, the upper surface of the copper connection between the defined interlayers' is often eroded by the chemical materials used, resulting in microscratch ) Phenomenon "And, if a hard dielectric layer is covered on the above-mentioned low-k dielectric interlayer dielectric layer with a value of less than about 2 · 7 to enhance its hardness to avoid chemical mechanical grinding. Microscratch phenomenon ', when trench trenching is performed, it is usually necessary to place between a low-k dielectric layer with a dielectric constant of about 2.7 and a harder dielectric layer. One Money cuts into layers, which will increase production costs. Therefore, how to solve the above problems has become an urgent problem for the industry.

4 6 9 5 9 1 V. Description of the invention (4) Purpose and summary of the invention: The purpose of the present invention is to use a material with a higher dielectric constant (dielectric constant about 2. 9 ~ 3.1) (for example: FSG). The first low dielectric constant dielectric layer compensates for the lack of hardness of the second low dielectric constant dielectric layer of a lower dielectric constant (dielectric constant about 2.6 to 2.7), such as SiLK, By enhancing the hardness, it is possible to avoid edge peeling, film delamination or microscratch during chemical-mechanical grinding. Good choice of surnames 9 7 2 2 i Use 6 to choose about 2. The number is borrowed from the regular number of the regular number C, a number, the other, the number of the C, and the number of the low, the first, the second, the second, and the province. Electricity, dielectric layer} Electricity 11 • Intervening layer placement, dielectric layer number, electrical constant dielectric number, low dielectric constant, low dielectric constant, low dielectric constant, low dielectric constant, high dielectric constant, low dielectric constant, high dielectric constant, low dielectric constant At the moment, the dielectric constant of the first layer of the shoe is often -π rpir lower than the first. The headquarters of this department went to 0 provinces, but sometimes because of one-PJ, the proposed method of the present invention includes the following steps: (1) forming an adhesive layer on the upper surface of a conductive plug, wherein The conductive plug is located in a dielectric layer of a semiconductor substrate. (2) A first low-dielectric constant dielectric layer having a dielectric constant of about 2, 9 to 3.1 is formed on the upper surface of the adhesive layer. (3) Using a lithographic etching technique, a part of the first low-k dielectric layer directly above the conductive plug is removed to form a dielectric hole. (4) Forming the second low dielectric constant dielectric

469591 V. Description of the invention (5) The layer is on the first low dielectric constant dielectric layer and filled in the hole of the dielectric layer, wherein the dielectric constant of the second low dielectric constant dielectric layer is smaller than the first low dielectric constant The dielectric constant of the constant dielectric layer, and the dielectric constant of the second low dielectric constant dielectric layer is preferably about 2.6 to 2.7. (5) Using a lithographic etching technique, removing a portion of the second low-k dielectric layer and the adhesive layer to form a trench and expose a portion of the upper surface of the conductive plug. (6) A metal thin film is formed on the second low-k dielectric layer and filled in the trench. After forming the metal thin film, the method further includes polishing the metal thin film by chemical mechanical polishing (CMP) to form a metal wire. Before forming the metal thin film, a barrier layer is formed in the trench to prevent the metal thin film from diffusing with the dielectric layer and the semiconductor substrate, thereby generating a spiking effect. In addition, after forming the barrier layer, it further includes forming a seed layer (s e d i n g 1 ayer) on the upper surface of the barrier layer to strengthen the adhesion of subsequent plating. The material of the above barrier layer may be selected from one of the following clusters: Ta, TaN, Ti N, Ti W, Ti, or any combination thereof. The material of the seed layer includes the same material as the metal thin film. The material of the metal film includes copper. In addition, the formation method of the adhesive layer includes a plasma enhanced chemical vapor deposition method (PECVD), which is made of silicon nitride or silicon carbide, and has a thickness of about 200 to 100 angstroms. The method for forming the first low-k dielectric layer includes chemical vapor deposition (CVD), and the material can be selected from one of the following clusters: FSG, SiOxCy, and black diamond

469591 V. Description of the invention (6) Black diamond or any combination thereof, and the thickness is about 20000 ~ 10000 Angstroms. The method for forming the second low-k dielectric layer includes a sp-on method, and the material can be selected from one of the following clusters: SiLK, FLARE, or any combination thereof, and the thickness is about 2 0 0 0 ~ 1 0 0 0 0 Angstroms. The material of the dielectric layer may be selected from one of the following clusters: SiLK, FLARE, or any combination thereof. Here, the reason why an etch stop layer is not required between the first low-k dielectric layer and the second low-k dielectric layer is because the first low-k dielectric layer and the second low-k dielectric layer Both of the dielectric constant dielectric layers have good etching selectivity. By selecting the etchant, it is possible to etch away only a small part of the first low dielectric while etching the second low dielectric constant dielectric layer. The dielectric constant layer saves production costs. For example: (1) If Si LK or FLARE material is used as the second low dielectric constant dielectric layer, and black diamond material is used as the first low dielectric constant dielectric layer, then by etching The choice of the agent, the etching selection ratio of the second low-k dielectric layer and the first low-k dielectric layer is greater than about 20, preferably about 30: 1. (2) If SiLK or FLARE material is used as the second low dielectric constant dielectric layer, and FSG material is used as the first low dielectric constant dielectric layer, then the second low dielectric material is selected by the choice of an etchant. The etching selection ratio of the constant dielectric layer to the first low dielectric constant dielectric layer is greater than about 20, and a preferred value is about 30: 1. Detailed description of the invention:

4 6 9 5 9 1 V. Description of the invention (7) The present invention provides a method for forming a common dielectric material having a low dielectric constant. This detailed description is as follows: Please refer to the third figure for the dual suppression of the dielectric layer, and first provide a half conductance. The bulk substrate 30 may be a < 1〇〇 > or < ιπ > & 30 'Among them are semiconducting semiconductor materials, such as GaAs, Ga or other kinds of 乂 〇 〇 〇—〇Γ, S〇i), etc., and the semiconductor substrate 30 has been fabricated on the integrated circuit required Various active components, passive components, and surrounding circuits. A dielectric layer 32 is then formed on the semiconductor substrate 30 'to produce an insulating effect. Then, contact holes (or trenches, contact holes, and trench holes (trench, contacyv / a hole)) can be formed on the dielectric layer 32 by conventional lithography and etching techniques to expose the semiconductor substrate 3o. On the surface. By using a chemical vapor deposition method or a physical vapor deposition method, a conductive plug 34 is formed in the contact hole β. Generally, a photoresist can be formed on the dielectric layer 32 to define a contact hole pattern. A lithography and etching process is performed to form a contact hole in the dielectric layer 32. Subsequently, the adhesive layer 36 and the first low-k dielectric layer 38 are sequentially formed on the upper surface of the dielectric layer 32 and the conductive plug 34. After the first low-k dielectric layer 38 is formed, a first -A photoresist layer 40 is defined thereon to define a via hole pattern (ν iah〇e e) 41.

Page 10 469591 Five 'invention description (8) ~-Next, please refer to the fourth figure, using the first photoresist layer 40 as an etching mask to remove a portion of the first low dielectric layer directly above the conductive plug 34 The constant dielectric layer 38 'until it reaches the adhesive layer 36 to form a dielectric hole. After the residual first photoresist layer 40 is removed, a second low-k dielectric layer 42 is formed on the first low-k dielectric layer 38 and filled in the hole of the dielectric layer. Next, 'form a second photoresist layer 44 thereon to define a trench pattern 45. Then please refer to the fifth figure,' use the second photoresist layer 44 as a button mask power 'to remove part of the second low The dielectric constant dielectric layer 42 and the adhesive layer 36 form a trench and expose a part of the upper surface of the conductive plug 34. After removing the remaining second photoresist layer 44 'by using a chemical vapor deposition method, or a physical vapor deposition method such as a sputtering process' or an electroplating method, a metal (eg, copper) film is formed on the second The metal film is formed on the low-k dielectric layer 42 and filled in the trench, and then the metal thin film is polished by chemical mechanical polishing (CMP) to form metal wires 46. Before forming the metal thin film, a barrier layer may be formed in the trench to prevent the metal thin film from spreading with the dielectric layer 32 and the semiconductor substrate 30, thereby generating a spiking effect. After the barrier layer is formed, a seeding layer can also be formed on the upper surface of the barrier layer to enhance the adhesion of subsequent electrical bonds. Among them, obstacles

Chapter 1 4 69 59 1 V. Description of the invention (9) The substance can be selected from one of the following clusters: Ta, TaN, TiN, Tiff, price or any combination thereof, and the preferred thickness of the barrier layer is approximately 1 50 to 4 50 Angstroms. In addition, the material of the seed layer may be copper or a copper alloy, which may be formed using a similar process such as physical vapor deposition (Phys i ca 1 vapor deposition; PVD), sputtering, and the like, and has about 6 0 0 To a thickness of 2 400 Angstroms. Of course, the above steps of forming the barrier layer and the seed layer may not be performed, or only the step of forming the seed layer may be performed. In addition, if the above-mentioned metal thin film is a copper thin film, its formation can be formed by immersing the semiconductor substrate 30 in a sulfuric acid steel solution to perform an Electrochemical Chemical Plating (ECP) reaction. In general, 'the copper ion in the sulfuric acid steel solution' can be reduced and deposited on the surface of the seed layer by electrically connecting the seed layer to the cathode of a power source. That is, copper atoms can be deposited on the surface of the seed layer by performing a plating process, and a desired copper layer can be formed. The above-mentioned adhesive layer 36 is used to strengthen the adhesive force between the first low-k dielectric layer 38 and the conductive plug 34, and its material includes silicon nitride and carbonized carbide, where the thickness of the adhesive layer 36 is approximately It is 2000 to 100 Angstroms. If the material of the adhesive layer 36 is silicon nitride, it can be formed by SiH and a reaction gas, called plasma enhanced chemical vapor deposition (PEC VD), under N 妁 environment. If the material of the adhesive layer 36 is silicon carbide, it can be formed by using plasma enhanced chemical vapor deposition (PECVD) (CH 4 (called 4MS in the industry) and carbon dioxide as the reaction gas.

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469591

V. Description of the Invention (ίο) The dielectric constant of the first low-k dielectric layer 38 is preferably about 2.9 ~ 3,1, and the thickness is about 2000 ~ 1 ~ 00. Angstrom, which is used as a `` dielectric layer between dielectric layers '' and the material can be selected from the group consisting of: FSG, Si OxCy, black diamond, or any combination thereof. The method for forming the first low-k dielectric layer 38 can be deposited by a chemical vapor phase deposition method (CVD). Nine, the dielectric constant of the second low dielectric constant dielectric layer 42 is preferably about 2. 6 ~ 2.7 7 'and its thickness is about 2000 ~ 1000 0 Angstroms, which is used as an inner metal The dielectric layer (IMD) can be selected from one of the following clusters: Si LK, FLARE, or any combination thereof. The second low-k dielectric layer 42 may be formed by a spin on method. The above-mentioned second low-k dielectric layer 42 has a low dielectric constant, mainly to achieve the effect of reducing the resistance-capacitance hysteresis. The first low dielectric constant dielectric layer 38 has a higher dielectric constant. The main reason is to make up for the lack of hardness of the second low dielectric constant dielectric layer 42. By strengthening the hardness to avoid f chemical mechanical polishing Edge peeling (edge peei ing), film ^ skinning (f il [n delaminati〇n) or fine seam (micr〇scratch)

469591 V. Description of the invention (11) Both the low dielectric constant dielectric layer 3 8 and the second low dielectric constant dielectric layer 4 2 have good etching selectivity, and can be etched away by the choice of an etchant. At the same time as the second low-k dielectric layer 42, only a very small portion of the first low-k dielectric layer 38 is etched, thereby saving production costs. For example: (1) If Si LK or FLARE material is used as the second low dielectric constant dielectric layer 42 and black diamond material is used as the first low dielectric constant dielectric layer 38, then borrow Based on the choice of the etchant, the second low-k dielectric layer 42 and the first low-k dielectric layer 38 have a selection ratio of about 30: 1. (2) If Si LK or FLARE material is used as the second low dielectric constant dielectric layer 4 2, and F SG material is used as the first low dielectric constant dielectric layer 3 8, then the choice of the etchant is adopted. The etching selection ratio of the second low-k dielectric layer 42 to the first low-k dielectric layer 38 is greater than about 20, and a preferred value is about 30: L. The material of the dielectric layer 32 includes the same material as that of the second low-k dielectric layer 42, and the formation method thereof is the same as that of the second low-k dielectric layer 42, and its thickness is about It is 2000 ~ 6000 Angstroms. In summary, the advantages of the present invention are as follows: (1) the first low dielectric constant dielectric material by using a higher dielectric constant (dielectric constant is about 2. 9 ~ 3. 1) material (for example: FSG) Layer 38 to compensate for the lack of hardness of the second low dielectric constant dielectric layer 42 of a material with a lower dielectric constant (dielectric constant about 2.6-2.7) (eg, SiLK). Edge peeling occurs during mechanical grinding 'film de 1 am i na ti on' or mi cr oscra 1; ch phenomenon 0 (2) due to

Page 14 469591 V. Description of the invention ¢ 12) The first selected low dielectric constant (dielectric constant is about 2. 9 ~ 3.1) dielectric layer 38 and the second low dielectric constant (dielectric constant is about 2 6 ~ 2. 7) The dielectric layer 42 has a good etching selectivity, so there is no need between the first low dielectric constant dielectric layer 38 and the second low dielectric constant dielectric layer 42. By placing an etch stop layer, the second low dielectric constant dielectric layer 42 can be etched by the choice of an etchant, while only a small part of the first low dielectric constant dielectric layer 38 is etched. In order to save production costs and produce a lower effective dielectric constant value. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; any equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be considered as The protection scope of the present invention. The scope of patent protection of the present invention depends on the scope of patent application and its equivalent fields.

Page 15 469591 Simple description of the formula Using the following description and the combination of the following drawings, you can understand the content and advantages of the present invention more clearly, where: The first figure is a cross-sectional view of a semiconductor wafer, showing the semiconductor substrate according to traditional technology A conductive plug, a first silicon nitride layer, a first low dielectric constant dielectric layer, a second silicon nitride layer, and a second low dielectric constant dielectric layer are sequentially formed on the top, and two successive lithography and The step of forming an opening by etching technology; the second figure is a cross-sectional view of a semiconductor wafer, showing the formation of a copper thin film according to the conventional technology, and then polishing the copper thin film by chemical mechanical polishing (C hemica 1 Mechanical Polishing; CMP), The third step is to form a copper wire. The third figure is a cross-sectional view of a semiconductor wafer, showing a conductive plug, an adhesive layer, a first low-k dielectric layer, a first A photoresist layer step; the fourth figure is a cross-sectional view of a semiconductor wafer, showing the use of the first photoresist layer as a mask according to an embodiment of the present invention, removing part of the first A step of forming a low dielectric constant dielectric layer, and then forming a second low dielectric constant dielectric layer and a second photoresist layer; and the fifth figure is a cross-sectional view of a semiconductor wafer, showing the use of the second The photoresist layer is a mask, and a part of the second low-k dielectric layer and the adhesive layer are removed to form a trench, and then a metal film is formed and polished to form a metal wire. Drawing number part:

Page 16 469 59 1 Schematic illustration of semiconductor substrate 10; dielectric layer 12; conductive plug 14; first silicon nitride layer 16; first low dielectric constant dielectric layer 18; second nitride Silicon layer 20; second low-k dielectric layer 22; opening 2 3; copper wire 24, semiconductor substrate 30; dielectric layer 3 2; conductive plug 34; adhesive layer 3 6; first low dielectric Constant dielectric layer 38; first photoresist layer 40; dielectric hole pattern 41; second low dielectric constant dielectric layer 42; second photoresist layer 44; trench pattern 45; metal wire 46.

Page 17

Claims (1)

469591 VI. Scope of patent application 1. A method for forming a dual damascene with a low dielectric constant dielectric layer, the method includes at least the following steps: forming an adhesive layer on a surface of a conductive plug, wherein the conductive plug is located on a surface In the dielectric layer of the semiconductor substrate; forming a first low-dielectric constant dielectric layer having a dielectric constant of about 2.9 to 3.1 on the upper surface of the adhesive layer; using a lithographic etching technique to remove the positive electrode located on the conductive plug The upper part of the first low-k dielectric layer to form a dielectric hole; forming a second low-k dielectric layer on the first low-k dielectric layer and filling the dielectric In the layer hole, the dielectric constant of the second low-dielectric constant dielectric layer is smaller than that of the first low-dielectric constant dielectric layer; a portion of the second low-dielectric is removed using a lithographic etching technique A constant dielectric layer and the adhesive layer to form a trench and expose a portion of the upper surface of the conductive plug; and a metal film is formed on the second low-k dielectric layer and filled in the trench In the ditch. 2. The method according to item 1 of the scope of patent application, wherein the material of the above dielectric layer may be selected from one of the following clusters: Si LK, FLARE, or any combination thereof. 3. The method according to item 1 of the patent application range, wherein the material of the adhesive layer includes silicon nitride or silicon carbide. Page 18 469591 6. Scope of patent application 4. For the method of the first scope of patent application, the thickness of the above-mentioned adhesive layer is about 200-100 Angstroms. 5. The method of applying for the first item of the patent scope, wherein the method for forming the above-mentioned adhesive layer includes plasma enhanced chemical vapor deposition (PECVD). 6. The method according to item 1 of the scope of patent application, wherein the thickness of the first low-k dielectric layer is about 2000 to 1000 angstroms. 7. The method according to item 丨 of the patent application, wherein the material of the first low-k dielectric layer may be selected from one of the following clusters: FSG, SiOxCy, black diamond, or any combination thereof. 8. The method of claim 1, wherein the method for forming the first low-k dielectric layer includes chemical vapor deposition (CVD). 9. The method according to item 1 of the scope of patent application, wherein the thickness of the above-mentioned second low-k dielectric layer is about 2000 to 1000 Angstroms. 10. The method according to item 1 of the scope of patent application, wherein the material of the second low-k dielectric layer can be selected from one of the following clusters: SiLK, FLARE, or any combination thereof. 1 1 · The method according to item 1 of the patent application scope, wherein the second lowest Page 19 f positive · 4 6 9 5 9 1 VI. Method of forming a dielectric constant dielectric layer in the scope of patent application Supplementary spin / 垔 Γ spin on: 1 2. If the method in the first scope of the patent application, 6〜2. 7。 Wherein the dielectric constant of the second low dielectric constant dielectric layer is about 2. 6 ~ 2. 7. 1 3. The method according to item 1 of the scope of patent application, wherein the etching selection ratio of the second low-k dielectric layer and the first low-k dielectric layer is greater than 20. 1 4. The method according to item 1 of the scope of patent application, wherein the material of the above metal film includes copper. 15. The method according to item 1 of the patent application scope, further comprising forming a barrier layer in the trench before forming the metal thin film. 16. The method according to item 15 of the scope of patent application, wherein the material of the barrier layer can be selected from one of the following clusters: Ta, TaN, TiN, TiW, Ti or any combination thereof. 17. The method according to item 15 of the scope of patent application, wherein after forming the barrier layer, it further comprises forming a seed layer (s e e d i n g 1 a y e r) on the upper surface of the barrier layer. 18. The method according to item 17 of the scope of patent application, wherein the seed layer described above Page 20 469591 VI. The materials covered by the patent include the same material method as the metal thin film. 19. The square is formed on top of the half of the layer forming the adhesive utilization layer, the dielectric utilization and The method for forming a low-dielectric second low-dielectric second conductive adhesive layer and filling a constant lithographic double-damascene with a low-dielectric and low-constant dielectric layer includes a step of forming a layer: a layer on a conductive plug The surface is in the conductive plug electric layer; the dielectric constant of the first low dielectric constant dielectric layer substrate of 2.9 ~ 3, 1 is about the upper surface; the low dielectric constant of the dielectric constant of the etching technology often enters the dielectric layer Smaller than the first worm-etched technical layer in a shape to remove a portion of the electrical layer directly above the conductive plug to form a dielectric hole; a plurality of dielectric layers in the first low-dielectric constant dielectric hole, wherein the The dielectric constant of the second low dielectric constant dielectric and a low dielectric constant dielectric layer; removing a part of the second low dielectric constant dielectric into a trench and exposing a part of the surface of the conductive plug; forming a resistance Layer on the second low-k dielectric layer and filling in the trench; forming a seed layer (seeding 1 ayer) on the upper surface of the barrier layer; and forming a metal film on the seed layer 2 0, as in the method of claim 19, wherein the above-mentioned adhesive layer Page 21 469591 VI. Patent application materials include silicon nitride or silicon carbide. 2 1. The method according to item 19 of the scope of patent application, wherein the thickness of the above-mentioned adhesive layer is about 2000 to 100 angstroms. 22. The method according to item 19 of the scope of patent application, wherein the method for forming the above-mentioned adhesive layer includes plasma enhanced chemical vapor deposition (PECVD). 2 3. The method according to item 19 of the scope of patent application, wherein the thickness of the first low-k dielectric layer is about 2000 to 1000 angstroms. 24. The method according to item 19 of the scope of patent application, wherein the material of the first low-k dielectric layer can be selected from one of the following clusters: FSG'Si0XCy, black diamond (b 1 a ck di am ο nd) or any combination thereof. 25. The method according to item 19 of the scope of patent application, wherein the method for forming the first low-k dielectric layer includes a chemical vapor deposition method (CVD 26. The method according to item 19 of the scope of patent application, The thickness of the second low-k dielectric layer is about 2000 to 1000 angstroms. 2 7. The method according to item 19 of the patent application, wherein the material of the second low-k dielectric layer can be selected from One of the following clusters: Page 22 Amendments and Supplements 469591 6. Scope of Patent Application Si LK, FLARE or any combination thereof. 2 8. The method according to item 19 of the scope of patent application, wherein the method for forming the second low-k dielectric layer includes a spin coating method (s p i η ◦ η). 29. The method according to item 19 of the scope of patent application, wherein the dielectric constant of the second low-dielectric constant dielectric layer is about 2.6 ~ 2.7. 30. The method according to item 19 of the scope of patent application, wherein the etching selection ratio of the second low-k dielectric layer and the first low-k dielectric layer is greater than 2 0 α 3 1. The method of scope item 19, wherein the material of the above barrier layer may be selected from one of the following clusters: Ta, TaN, TiN, TiW, Ti, or any combination thereof. 32. The method according to item 19 of the scope of patent application, wherein the material of the seed layer includes copper or a copper alloy. 33. The method according to item 19 of the scope of patent application, wherein the material of the metal thin film includes copper. Page 23