TW434917B - Light emitting diode array - Google Patents

Abstract

The present invention proposes a light emitting diode array which comprises the first electrode; a substrate with the first conducting type formed on the first electrode; the first conductive semiconductor layer with the first conductive type formed on the substrate; an active layer formed on the first conductive semiconductor layer; the second conductive semiconductor layer with the second conductive type formed on the active layer; a plurality of contact layers with the second conductive type formed on the second conductive semiconductor layer; a plurality of transparent and conductive oxide layers formed on a plurality of the contact layers, each transparent and conductive oxide layer forms an ohmic contact with the corresponding contact layer; and a plurality of the second electrodes formed on transparent and conductive oxide layer; the region covered by each of the second electrode is not overlapped with the corresponding contact region.

Description

4 3 491 7 V. Description of the invention (1) [Field of invention] _ The present invention relates to a light-emitting diode array, and more particularly to a conductive light-transmitting oxide layer, so that the light emitted by the light-emitting diode is not blocked by the electrode. Light emitting diode array. [Description of Conventional Technology]-Light-emitting diode arrays are used in scanners, printers, or printers, for example, to scan or print documents. Among them, the light emitting quality of the light emitting diode array is directly related to the quality of the document printing. FIG. 8 is a schematic diagram showing a conventional light emitting diode array. Referring to FIG. 8, a conventional light emitting diode array includes: a first electrode 1; a first conductive type semiconductor substrate 2 formed on the first electrode 1; a plurality of pn′-junction light emitting stacks 3, formed on the first conductive type semiconductor substrate 2; a plurality of second electrodes 4, connected to each of the pn junction light emitting stacks 3; and an insulating region 5, surrounding the pn junction light emitting stacks 3, around. The above-mentioned conventional light-emitting diode has a fundamental problem in the structure, that is, the second electrode 4 is used to supply the driving current required for the p-η junction light-emitting stack 3 to emit light, and the light-emitting stack is corresponding to the corresponding ρ-η junction. On the layer 3, there is a contact area, so that the second electrode 4 will cover the light emitted from the ρ-η junction light-emitting stack 3, thus greatly reducing the use efficiency of the driving current of the light-emitting diode array. In addition, since this contact area mostly corresponds to the position of the center of the ρ-η junction light-emitting stack 3, in order to facilitate the current to spread to the entire pn junction light-emitting stack 3, when the pn junction light-emitting stack 3 emits light, the second The electrode 4 will shield the light in the center of the light-emitting area. Therefore, if the light-emitting diode density of the light-emitting diode array is increased, a problem of identifying the exact position of the light-emitting will occur.

Page 4 4349 17 V. Description of the invention ¢ 2) However, if the contact area of the second electrode 4 is reduced, the contact resistance between the second electrode 4 and the p-η junction light-emitting stack 3 will increase, increasing driving Current consumption in light emitting diode array. In addition, due to the current crowding effect of the p-η junction light emitting stack 3, when the contact area between the second electrode 4 and the pn junction light emitting stack 3 is reduced, the ρ-η junction light emitting stack-- The light emission level of the layer 3 will be uneven, that is, the region where the ρ-η junction light-emitting stack 3 is closer to the second electrode 4 will have a stronger luminous brightness, and the region farther from the second electrode 4 'will have a weaker luminous brightness. A problem may arise in that the light emitting position is recognized incorrectly. [Summary of the Invention] An object of the present invention is to provide a light emitting diode array, in which the light emitting layer at the ρ-η junction is uniform in light emission, and the light emitting position is easy to identify. Another object of the present invention is to provide a light-emitting diode array, in which the second electrode does not shield the emitted light to the light-emitting layer on the ρ-η junction, thereby improving the efficiency of using the driving current during the operation of the light-emitting diode array. . To achieve the above object, the light-emitting diode array of the present invention includes: a first electrode; a substrate formed on the first electrode and having a 'first conductivity type; a first conductive semiconductor layer formed on the substrate, Has a first conductive type; an active layer formed on the first conductive semiconductor body layer, has an upper surface and a lower surface, the lower surface is in contact with the first conductive semiconductor layer; γ a second conductive semiconductor layer, formed On the upper surface of the active layer, having a second conductivity type;

5. Description of the invention (3) A plurality of contact layers are formed on the second conductive semiconductor layer and have a second conductivity type; a plurality of conductive light-transmitting oxide layers are formed on the plurality of contact layers, and each of the conductive light-transmitting oxide layers Forming an ohmic contact with the corresponding contact layer; and '

A plurality of second electrodes are formed on the plurality of conductive light-transmitting oxide layers, and an area covered by each second electrode does not overlap with a corresponding contact layer area. Because the conductive light-transmitting oxide layer is used, the second electrode will not shield the emitted light from the active layer, which can save the light-emitting diode arrays during operation ...

Drive current to improve luminous efficiency D η_ In addition, because the conductive light-transmitting oxide layer has good current spreading characteristics, it will not cause the phenomenon of non-uniform luminescence, and it will not have the problem of difficult identification of the luminous position. [Simplified description of the diagram]

1 (A) to (C) are schematic diagrams showing a light emitting diode array according to a first embodiment of the present invention, wherein FIG. 1 (A) is a plan view thereof, and FIG. 1 (B) is a view along FIG. 1 (A) A cross-sectional view taken along the line B-B '. FIG. 1 (C) is a cross-sectional view taken along the line C-C' in FIG. 1 (A). FIG. 2 is a schematic diagram showing a light emitting diode array according to a second embodiment of the present invention. 3 (A) to (B) are schematic diagrams showing a light emitting diode array according to a third embodiment of the present invention, in which FIG. 3 (A) is a structure without a Bragg reflection layer, and FIG. 3 (B) is Structure of the Bragg reflector.

5. Description of the invention (4) Figures 4 (A) to (D) are schematic diagrams showing a light emitting diode array according to the fourth embodiment of the present invention, in which Figures 4 (A) and (B) are The structure of the Bragg reflection layer is added. Figures 4 (C) and (D) show the structure of the Bragg reflection layer. 5 (A) to (B) are schematic diagrams showing a light emitting diode array according to a fifth embodiment of the present invention, in which FIG. 5 (B) is a side view of FIG. 5 (A). 6 (A) to (B) are schematic diagrams showing a light emitting diode array according to a sixth embodiment of the present invention, in which FIG. 6 (A) is a structure without a buffer layer, and FIG. 6 (B) is a structure with a buffer added Layer structure. 7 (A) to (C) are schematic diagrams showing a light emitting diode array according to a seventh embodiment of the present invention. 7 (A) is a top view of a light emitting diode array according to a seventh embodiment of the present invention, and FIG. 7 (B) is a cross-sectional view taken along the line BB ′ in FIG. 7 (A). FIG. 7 (C) It is a sectional view taken along the line C-C 'in FIG. 7 (A). FIG. 8 is a schematic diagram showing a conventional light emitting diode array. [Illustration of Symbols] 1 to 1st electrode 2-substrate 3 to p-n junction light-emitting stack 4 to 2nd electrode 5 to insulation region 1 1 to 1st electrode 1 2 to substrate

Page 7 434917 V. Description of the invention (5) 13 to the first conductive semiconductor layer 1 3 1 to the lower binding layer 1 3 2 to the Bragg reflective layer 1 4 to the active layer _ 1 5 to the second conductive semiconductor layer 1 5 1 to Upper tie layer 1 5 2 ~ Upper tie layer 1 53 ~ Window layer 1 5 4 ~ Asymmetric upper tie layer 1 5 5 ~ Buffer layer p 1 5 6 ~ High resistance upper tie layer 1 5 7 ~ High resistance layer 1 6 ~ Contact layer _ 17 ~ Conductive transparent oxide layer 1 8 ~ Second electrode 19 ~ Isolation area 5 0 ~ Insulation layer 5 9 ~ Isolation trench [Detailed description of the embodiment] The embodiment of the present invention will be compared with the related figure The way to explain it. 1 (A) to (C) are schematic diagrams showing a light emitting diode array according to a first embodiment of the present invention, wherein FIG. 1 (A) is a top view of a light emitting diode array according to a first embodiment of the present invention. Fig. 1 (B) is a sectional view taken along the line B-B 'in Fig. 1 (A), and Fig. Γ (C) is taken along the line OC' in Fig. 1 (A)

Page 8 4349 1 7 V. Sectional view of invention description (6). Referring to FIG. 1, a light emitting diode array according to a first embodiment of the present invention includes: a first electrode 1 1; a substrate 12 formed on the first electrode 11 and having a first conductive type; a first conductive semiconductor A layer 13 is formed on the substrate 12 and has a first conductivity type; an active layer 14 is formed on the first conductive semiconductor layer 13; a second conductive semiconductor layer 15 is formed on the active layer 14 and has a first Two conductive types: a plurality of contact layers 16 are formed on the second conductive semiconductor layer 15 and have a second conductive type; a plurality of conductive light-transmitting oxide layers 17 are formed on the plurality of contact layers 16 and each The conductive light-transmitting oxide layer 17 is electrically connected to a corresponding contact layer 16 respectively; a plurality of second electrodes 18 are formed on the plurality of conductive light-transmitting oxide layers 17, and each second electrode 18 is respectively corresponding to a corresponding conductive light-transmitting oxide Layer 17 is electrically connected, and the area covered by each second electrode 18 does not overlap with the area of its corresponding contact layer 17; and an isolation region 19 is formed in the second conductive semiconductor layer and surrounds a plurality of the Contact layer around. In this embodiment, the first conductivity type is an n-type, and the second conductivity type is a p-type. However, if the first conductivity type is p-type, the second conductivity type is

Page 9 43491? 5. Description of the invention (7) ~ η type can also be applied to the present invention without violating the spirit of the present invention. 0 In this embodiment, the first conductive semiconductor layer 13 is under an η type. & the binding layer 131, the second conductive semiconductor layer 15 is a p-type upper binding layer 151, the aforementioned two layers and the active layer 14 constitute a conventional ρ-η junction light-emitting stack, a sister-structure, and a constituent material thereof, It can be a conventional light-emitting diode material, such as' AlGalnP. In this ρ-η junction light emitting stack, the active layer 14 is composed of the conventional multiple quantum well (MQW) structure technology or the conventional double heterostructure (amplification) technique, so that the crystal lattice The quality is improved, and the luminous efficiency of the light emitting diode is also increased. The contact layer 16 may be made of GaAsP, GaP, GaInP, or GaAs, and the thickness ρ is about 50 Angstroms. By controlling the carrier concentration of the contact layer 16 (about Is 5 X ^ 1 〇i8cnr3), which can form an ohmic contact with the conductive transparent oxide layer 17 so that current can pass through to the pn junction light-emitting stack. As shown in US Patent No. 5481122 According to the disclosure, the conductive light-transmissive oxide layer 17 may be made of copper tin oxide, oxide surface, tin oxide 'oxide or oxide town, and the thickness is about 0' 1 to 5 microns. For a wavelength of 5 5 5 nm (green light ) And 630nm (red light), the conductive light-transmitting oxide layer 17 has excellent light transmittance. The material properties of the conductive light-transmitting oxide layer 7 are similar to those of metals, so it becomes the binding layer 1 5 When the carrier concentration of 1 is small, the conductive light transmission cp Layer 17 and the upper bound by the interface layer 151 may be formed between a Schottky barrier (Shottky barrier) 'current is not light-transmissive conductive oxide layer from

4349 i 7 V. Description of the invention (8) Directly flowing to the upper binding layer 1 5 1 can only flow through the contact layer 16 forming an ohmic contact. In this way, the light emitting area of the p-η junction light emitting stack can be controlled. i In addition, the conductive light-transmitting oxide layer 1 7 has a low resistivity (3 X 1 _ 4 Ω -cm), so it has a good current spreading effect, so that the current can pass through the conductive light-transmitting oxide layer 1 7 Diffusion to the entire area where the p-η junction-light-emitting stack is intended to emit light, without current crowding. The formation area of each second electrode 18 will not cover the emitted light of the light emitting layer of the p-η junction in each light emitting diode unit, so that the light emitting position in the light emitting diode array can be easily identified, and the light emission can be improved. Diode Array / Efficiency of driving current during operation. 'The isolation area 19 is used to isolate the current of each light emitting diode unit in the light emitting diode array to ensure that each light emitting diode unit is independent of each other.

There is no case where an adjacent light-emitting diode unit generates erroneous light emission due to current diffusion. The depth of the isolation region 19 may theoretically reach the upper surface of the active layer 14, but the lowest point of the isolation region 19 generally exceeds the lower surface of the active layer 14 and reaches the first conductive semiconductor layer 13. To ensure its effect of isolating current. The isolation region 19 can be formed in a diffusion manner. If the second conductive semiconductor layer is P-type, the dopant of the isolation region 19 is Si, so that the isolation region 19 becomes n-type. If the second conductive semiconductor layer is n-type , The dopant is Z η or Mg, so that the isolation region 19 becomes p-type. The isolation region 19 can also be formed by ion implantation, and its dopant is H + or 0+. 1 FIG. 2 is a schematic diagram showing a light emitting diode array according to a second embodiment of the present invention. The structure of FIG. 2 is different from that of FIG. 1 in that the first conductive half

Page 11 434917 V. Description of the invention (9) The conductive layer 13 further includes a multilayer Bragg reflector (DBR) 132, which is usually formed of AlGalnP or AlGaAs. In this embodiment, the Bragg reflection layer 132 includes more than 20 layers. The Bragg reflection layer 1 3 2 is used to reduce the emitted light of the active layer 1 4 by the substrate 12 so as to improve the light extraction efficiency of the light emitting diode array.

3 (A) to (B) are schematic diagrams showing a light-emitting diode array according to a third embodiment of the present invention, wherein the second conductive semiconductor 5 includes the upper binding layer 152 and Window layer 153. The material of the upper tie layer 152 is AlGalnP. The material of the window layer 153 is usually a light transmitting material such as GaP, GaAsP, GalnP, AlGaInP, or AIGaAs.

Ik

The purpose is to increase the luminous efficiency of the light-emitting diode unit. In this embodiment, as shown in FIG. 3 (B), the Bragg reflective layer 32 described in the second embodiment may be further included in the first conductive semiconductor layer η to enhance the light-emitting diode array. Light extraction efficiency. X Figures 4 (A) to (D) are schematic diagrams showing a light-emitting diode array according to a fourth embodiment of the present invention, wherein each light-emitting diode unit is the same as that of US Patent No. 5 9 1 7 2 0 1 In the disclosed asymmetrical energy band structure, the asymmetric upper binding layer 1 5 4 was used to replace the original upper binding layer 丨 5}. In this embodiment, the material of the asymmetry upper tie layer 154 may be Gap, GaAsp, GaInp, UGalnp

Or A 1 GaAs. The structure of FIG. 4 (B) is to add a buffer layer 155 between the active layer 14 and the asymmetric upper restraint layer 154. The purpose of the buffer layer 155 is to ease the lattice constant and the asymmetry of the active layer 14. Lattice layer 丨 54

4349] 7 V. Description of the invention (10) Strain caused by different constants. In this embodiment, as shown in FIG. 4 (c), the first conductive semiconductors in FIGS. 4 (A) and (B), respectively, may further include the Bragg reflection layer 1 2 described in the second embodiment. 2 to improve the light extraction efficiency of the light-emitting diode array. &Amp; f L 2 2 to (B) is a schematic diagram showing a fifth embodiment of the present invention: seven isolated H 19-f body array. The isolation trench 5 9 takes 3 depths from the trench 59, theoretically reaching the K surface of the active layer 14 and 5: 的 The lowest point of the isolation trench 59 exceeds the active layer 14 so that: == a conductive semiconductor layer 13 for continued protection The isolation material ^ η In this embodiment, a layer can be filled in the isolation trench 5 9: a part of the dream can be converted into the active layer G m electro-transmissive oxide layer 17 inside the trench. In addition: it is also expected 50 may be oxidized or nitrogen 1-luxury 纮 λ ~ ~ J. In the first conductive abundance conductor layer 13, it further includes a matrix; the light is extracted from the ij Bragg reflector 132 to enhance the light emitting diode. Figure 6 (A) 5 / n \ vl _ Example of the light-emitting diodes 2) is shown as a diagram = \ Xingyou shows according to the sixth embodiment of the present invention 15 is-a high-resistance upper beam two-layer 156 Figure 6 丄 V // Second The conductive semiconductor layer isolates the trenches 59, but instead uses the isolation region 19 to flow in this embodiment. Stomach high-resistance restraint: the second layer of j5 6 to prevent the current from crossing the ^ this restraint layer 151 or asymmetric upper restraint layer 154 i resistive resistance layer 157 to prevent the current from flowing in the lateral direction, the high (^ 11 ^ or 六 11 ^. In this embodiment, the first conductive semiconductor layer 13 is further included as described in the second embodiment.

Page 13 4 3 4 ^ 1 V. The Bragg reflector 132 described in (11) of the invention to improve the light extraction efficiency of the light emitting diode array. 7 (A) to (C) are schematic diagrams showing a light emitting diode array according to a seventh embodiment of the present invention. 7 (A) is a top view of a light emitting diode array according to a seventh embodiment of the present invention. FIG. 7 (B) is a cross-sectional view taken along the line B-B 'in FIG. 7 (A), and FIG. 7 (C) is A cross-sectional view taken along the line C-C 'in FIG. 7 (A). In this embodiment, the coverage area of each conductive light-transmitting oxide layer 17 is only slightly larger than the coverage area of its corresponding contact layer 16, and each second electrode 18 extends to its corresponding conductive light-transmitting oxide layer 17. It is electrically connected to the conductive transparent oxide layer 17. The area covered by each second electrode 18 does not overlap the area of its corresponding contact layer 16. _ The above is only a preferred embodiment of the present invention and is not intended to limit the scope of patent application of the present invention. Other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the scope of patent application described below.

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Claims (1)

4 3 491 7 VI. Application for patent scope 1. A light emitting, dipole, and body unit, including: a first electrode; a pn junction light emitting stack formed on the first electrode and electrically connected to the first electrode Connected; a conductive light-transmitting oxide layer formed above the Pn junction light-emitting stack and electrically connected to the pn-interface light-emitting laminate; and a second electrode formed above the conductive light-transmitting oxide layer and electrically conductive The light-transmitting oxide layer is electrically connected, and the area covered by the second electrode does not overlap the light-emitting stack area of the pn junction. 2. The light-emitting diode unit according to item 1 of the scope of patent application, wherein: the conductive light-transmitting oxide layer includes one selected from the group consisting of indium tin oxide, indium oxide, tin oxide, zinc oxide, and magnesium oxide . 3. A light emitting diode array comprising: a first electrode; a substrate formed on the first electrode and having a first conductivity type; a first conductive semiconductor layer formed on the substrate and having the A first conductive type; an active layer formed on the first conductive semiconductor layer and having an upper surface and a lower surface, the lower surface being in contact with the first conductive semiconductor layer; a second conductive semiconductor layer formed on the first conductive semiconductor layer The upper surface of the active layer has the second conductivity type; a plurality of contact layers are formed on the second conductive semiconductor layer and have the second conductivity type; 苐 Page 15 4343 6. The scope of the patent application is formed of a plurality of conductive light-transmitting oxide layers formed on the plurality of contact layers. Each of the conductive light-transmitting oxide layers is electrically connected to a corresponding contact layer, and Forming an ohmic contact between the photo-oxidized layer and the corresponding contact layer; and A plurality of second electrodes are formed on the plurality of conductive light-transmitting oxide layers, each of the second electrodes is electrically connected to a corresponding conductive light-transmitting oxide layer, and an area covered by each of the second electrodes is not Overlap with the corresponding contact layer area. -4. The light-emitting diode array according to item 3 of the scope of patent application, wherein: the first conductivity type is η-type, and the second conductivity type is p-type. 5. The light emitting diode array according to item 3 of the scope of patent application, wherein: The first conductivity type is P-type, and the second conductivity type is η-type. 6. According to the light-emitting diode array of the third patent application scope, wherein: the substrate includes GaAs. 7. The light emitting diode array according to item 3 of the scope of patent application, wherein: the active layer comprises A 1 G a I η P. -.8. The light-emitting diode array according to item 7 of the scope of patent application, wherein: the active layer includes an A 1 G a I η P heterostructure (d 0 u b 1 e heterostructure) ° Page 16 43 49 1 / VI. Patent application scope 9. The light emitting diode array according to item 7 of the patent application scope, column, wherein: the active layer includes an AlGalnP multiple quantum well structure 0-10 . The light-emitting diode array according to item 3 of the patent application scope, wherein: the contact layer includes one selected from the group consisting of GaAsP, GaP, GaInP, and GaAs. 11. The light-emitting diode array according to item 3 of the patent application scope, wherein:. The conductive light-transmitting oxide layer includes one selected from the group consisting of indium tin oxide, indium oxide, tin oxide, zinc oxide, and magnesium oxide. material. 12. The light-emitting diode array according to item 3 of the scope of patent application, wherein: the first conductive semiconductor layer includes the following binding layer, and the material thereof includes A 1 G a I η P ° 13. According to item 3 of the scope of patent application The light emitting diode array, wherein the first conductive semiconductor layer includes: a distributed Bragg reflector formed on the substrate, and a lower restraint layer formed on the lower restraint layer. 14. The light-emitting diode array according to item 13 of the scope of patent application, wherein: the Bragg reflective layer includes a group consisting of AlGalnP and AlGaAs 4349 1 7 6. One of the materials selected for the scope of patent application. 15. The light-emitting diode array according to item 13 of the patent application scope, wherein: the lower binding layer comprises AlGalnP. 16. The light-emitting diode array according to item 3 of the scope of patent application, wherein: the second conductive semiconductor layer includes an upper binding layer, and a material thereof includes A 1 Ga I nP. 17. The light emitting diode array according to item 3 of the patent application scope, wherein the second conductive semiconductor layer includes: an upper tie layer formed on the active layer; and a window layer formed on the upper tie layer. 18. The light emitting diode array according to item 17 of the scope of patent application, wherein: the upper binding layer comprises AlGalnP. 19. The light-emitting diode array according to item 17 of the scope of patent application, wherein: the window layer includes one selected from the group consisting of GaP, GaAsP, GaInP 'AlGalnP, and A 1 G a A s. 20. The light-emitting diode array according to item 3 of the scope of patent application, wherein: the second conductive semiconductor layer includes an asymmetric upper binding layer, which is selected from the group consisting of GaP, AlGaP, GaAsP, and GalnP. One material. 434917 VI. Patent application Fanyuan a 2 1 The light emitting diode array according to item 3 of the patent application scope, wherein the second conductive semiconductor layer includes: a buffer layer 'formed on the active layer; and-asymmetrically bound Layer formed on the buffer layer. 2 2 _ The light emitting diode array according to item 21 of the patent application scope, wherein: the buffer layer includes AlGalnP. 2 3. The light-emitting diode array according to item 21 of the scope of patent application, wherein: the asymmetric upper bound layer comprises one selected from the group consisting of GaP, GaAsP, GaInP, AlGalnP, and AlGaAs. 24. The light-emitting diode array according to item 3 of the claim, wherein the second conductive semiconductor layer includes a high-resistance upper binding layer, and a material thereof includes A 1 G a I η P. '25. The light emitting diode array according to item 3 of the patent application scope, wherein the second conductive semiconductor layer includes: ^ an upper binding layer formed on the active layer; and a high resistance layer formed on the upper binding layer On the floor. 2 6. The light emitting diode array according to item 25 of the scope of patent application, wherein: the upper binding layer comprises A 1 Ga I ηP. 27. The light-emitting diode array according to item 25 of the scope of patent application, wherein: ′, the high-resistance layer includes a group selected from the group consisting of AlGalnP and AllnP & No. 9 page 43 48 1 VI. One of the scope of patent application. 28. The light emitting diode array according to item 3 of the patent application scope, further comprising: an isolation region formed in the second conductive semiconductor layer and surrounding the plurality of the contact layers. 2 9. The light-emitting diode array according to item 28 of the scope of patent application, wherein: the isolation region is formed in a diffusion manner, and when the second conductive semiconductor layer is p-type, the dopant of the isolation region is Si When the second conductive semiconductor layer is n-type, the dopant of the isolation region is selected from the group consisting of Zn and Mg. 30. The light emitting diode array according to item 28 of the patent application scope, wherein: the isolation region is formed by ion implantation, and its dopant is selected from the group consisting of H + and 0+. 31. The light emitting diode array according to item 28 of the scope of patent application, wherein: the lowest point of the isolation region reaches below the lower surface of the active layer. 32. The light emitting diode array according to item 28 of the scope of patent application, wherein: the lowest point of the isolation region substantially reaches the upper surface of the active layer. 33. The light emitting diode array according to item 3 of the patent application scope, further comprising: an isolation trench formed in the second conductive semiconductor layer and surrounding the plurality of the contact layers. Page 20