•r 〇471 五、發明說明（1) 本發明係有關於一種金屬矽化物製程，特別是有關於 種利用兩階段性形成金屬鈦以形成金屬石夕化鈦之製程。 為了提高半導體元件的操作速度與性能，一般常見的 M0S電晶體必須盡可能的降低複晶矽閘電極以及源極/汲極 的片阻值（sheet resistance)，和各電極接觸點間的電阻 值。由於矽材質的阻值較高，故利用耐熱金屬（例如鈦）與 石夕反應所形成具低電阻值的耐熱金屬矽化物便逐漸被應用 在半導體製程中’以提供較低阻值的材質，期使電晶體内 有較高的導通電流’進而提昇其運作時的效能。目前，利 用鈦金屬與矽進行自我對準矽化鈦（TiSix)製程是目前業 界廣泛適用的方法之一。 其中’兩階段石夕化金屬製程（cide process)由於 具有低接觸阻值以及片阻值的優點，i故廣泛被應用於CM〇s 元件之接觸内連線以及區域内連線製程中。接下來，為方 便起見，係以一MOS電晶體為例，以更確切地說明習知之 金屬矽化過程。 請參考第1 A圖’係於一矽基板1 〇上形成有淺溝槽隔離 區（shallow trench isolation)STI ，以定義出元件之主 動區。而在該淺溝槽隔離區STI間則形成有一閘極結構 1 2 ’其包括一閘氧化層1 2 1，及上方之複晶矽閘電極1 2 2， 且於此閘極結構1 2周圍則形成一絕緣間隙壁1 23，而在該 閘極結構1 2兩側之矽基板1 〇中則形成有一源/汲極1 4。 接下來，請參看第1 B圖，利用磁控直流濺鍍（D. C sputtering)的方式，濺鍍一層金屬鈦16於該矽基板10與• r 〇471 V. Description of the invention (1) The present invention relates to a metal silicide process, and particularly to a process for forming metal titanium by using two-stage formation of titanium metal. In order to improve the operating speed and performance of semiconductor devices, the common MOS transistor must reduce the sheet resistance of the polycrystalline silicon gate electrode and the source / drain as much as possible, and the resistance between the electrode contact points. . Due to the high resistance value of silicon material, the heat resistance metal silicide with low resistance value formed by the reaction of heat-resistant metal (such as titanium) with Shi Xi has gradually been used in semiconductor processes to provide materials with lower resistance value. It is expected that the transistor will have a higher on-current, thereby improving its operating efficiency. At present, the self-aligned titanium silicide (TiSix) process using titanium and silicon is one of the methods widely used in the industry. Among them, the two-stage cide process has the advantages of low contact resistance and sheet resistance, so it is widely used in contact interconnects and area interconnect processes of CMOS devices. Next, for the sake of convenience, a MOS transistor is taken as an example to explain the conventional metal silicidation process more accurately. Please refer to FIG. 1A. A shallow trench isolation region (STI) is formed on a silicon substrate 10 to define the active region of the device. A gate structure 1 2 ′ is formed between the shallow trench isolation regions STI, which includes a gate oxide layer 1 2 1 and a polycrystalline silicon gate electrode 1 2 2 above the gate structure 12 and surrounds the gate structure 12. An insulating spacer wall 123 is formed, and a source / drain electrode 14 is formed in the silicon substrate 10 on both sides of the gate structure 12. Next, referring to FIG. 1B, a method of magnetron DC sputtering (D. C sputtering) is used to sputter a layer of titanium 16 on the silicon substrate 10 and
第4頁 4347 1Page 4 4 1347
五、發明說明（2) 該閘極結構1 2之表面。之後，a 7lΛ 屬& >日& & 為了增加後續要形成矽化金 =曰曰核數目以避免因為元件線寬縮小而使其片阻值受 m於疋便以石夕雜質進行離子混合佈植，將之植入於 龙屬鈦中。 /下來，將所獲得之產物送入快速熱退火反應室中， ^第化#又的快速熱退火製程’以使金屬鈦與複晶石夕問 居極122及位於源/汲極14表面之矽基板反應，以形成一金 :石夕化欽層（未顯示）。之後，#除未參與反應之金屬欽 層i再進行第二階段的快速熱退火製程，使該矽化鈦層進 行阳相轉移反應，而形成一阻值較低之矽化鈦層1 6 〇 ,如 第1C圖所示。 然而，在進行離子混合伟植之步驟時，佈植於金屬鈦 中的矽是具有高能量的，因此擴散至矽基板内而產生暫態 加速擴散（transient enhance diffusion，TED)，而形成 插空隙型（interstitial type)缺陷（defeat)，更使得元 件之工作性能（performance)降低，如穿透 (punchthrough)、臨界電壓（threshold voltage)下降、 飽和或截止電流改變…等等。 有鑑於此，本發明之目的在於提供一種金屬矽化物， 其具有低片電阻值，且能夠避免在進行離子混合佈植之步 驟時’因高能量的矽雜質佈植而造成後續產生的元件缺 陷。 為了達到本發明的目的’係利用一種兩階段性形成金 屬鈦以形成金屬矽化物的製程，適用於一半導體矽基板，V. Description of the invention (2) The surface of the gate structure 12. After that, a 7lΛ belongs to & > Japan & & In order to increase the number of subsequent formation of silicon silicide = the number of nuclei to avoid the chip resistance value due to the reduction of the line width of the element, the ion will be ionized by impurities They were mixed and planted in dragon titanium. / Down, the obtained product is sent to the rapid thermal annealing reaction chamber, and the rapid thermal annealing process is performed to make the metal titanium and the polycrystalite interstitial electrode 122 and the source / drain electrode 14 surface The silicon substrate reacts to form a gold: Shi Xihua Chin layer (not shown). After that, the second step of the rapid thermal annealing process is performed to remove the metal Chin layer that has not participated in the reaction, so that the titanium silicide layer undergoes a positive phase transfer reaction, and a titanium silicide layer with a lower resistance value is formed. Shown in Figure 1C. However, during the ion mixing step, silicon implanted in metal titanium has high energy, so it diffuses into the silicon substrate to produce transient accelerated diffusion (TED), and forms interstitial spaces. Interstitial type defects further reduce the performance of the device, such as penetration (punchthrough), reduction of threshold voltage (threshold voltage), saturation or cut-off current changes, and so on. In view of this, the object of the present invention is to provide a metal silicide, which has a low sheet resistance value and can avoid the subsequent generation of element defects caused by the implantation of high-energy silicon impurities during the ion hybrid implantation step. . In order to achieve the object of the present invention, a two-stage process for forming metal titanium to form a metal silicide is applicable to a semiconductor silicon substrate.
第5頁 434? 1 1 、發明說明（3) ' 且於該半導體矽基板形成有一金氧半電晶體，包括一閘 極、一源極、與一汲極，包括下列步驟：形成一第一金 層於該半導體矽基板之表面；進行一離子混合佈植，將雜 質佈植至該第一金屬層與該半導體矽基板之介面間；形 一第二金屬層於該第一金屬層之表面；進行—熱退火製程 以於該閘極、該源極、與該汲極表面形成一金屬矽化物； 以及移除該第一、第二金屬層。 、其中’佈植至該第一金屬層中之雜質係為矽，且所彤 成之第一、第二金屬層係為鈦層。 夕 在此需注意的是，由於在所第一階段所形成之第—金 2鈦層厚度較薄，因此其後所佈植的雜質矽所需之佈植能 里相較於習知所需之佈植能量為低，因此所植入之矽晶^ 會停駐於第一金屬鈦層與半導體矽基板之介面間，而=免 了暫態加速擴散（TED)、及其所導致的元件缺陷的產生。 為讓本發明之上述目的、特徵、和優點能更明顯易 僅’下文特舉一較佳實施例，並配合所附圏式， 明如下： 叶、田說 圖式之簡單說明： 第1 A〜1 C圖係顯示習知之應用於MOS電晶體之兩階段性 的金屬石夕化過程之流程剖面圖；以及 第2A〜2D圖係顯示依據本發明之應用於㈣^電晶體之兩 階段性形成金屬鈦以形成金屬矽化物之流裎剖面圖。 實施例 接下來，請參看第2A至2D圖，以更清楚的瞭解本發明Page 5 434? 1 1 、 Explanation of the invention (3) '' and forming a gold-oxygen semi-electric crystal on the semiconductor silicon substrate, including a gate, a source, and a drain, including the following steps: forming a first A gold layer is disposed on the surface of the semiconductor silicon substrate; an ion-mixed implant is performed to implant impurities between the first metal layer and the interface of the semiconductor silicon substrate; a second metal layer is formed on the surface of the first metal layer Performing a thermal annealing process to form a metal silicide on the gate, the source, and the drain surface; and removing the first and second metal layers. The impurity implanted in the first metal layer is silicon, and the first and second metal layers formed are titanium layers. It should be noted here that, because the first-gold-titanium layer formed in the first stage is thinner, the implantation energy required for the subsequent implantation of the impurity silicon is more than that required by conventional knowledge. The implantation energy is low, so the implanted silicon crystal will stop between the first metal titanium layer and the interface of the semiconductor silicon substrate, and = the transient accelerated diffusion (TED) and its resulting components are avoided Generation of defects. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easy, only a preferred embodiment is given below, and in conjunction with the attached formula, the description is as follows: Ye, Tian said a brief description of the diagram: Section 1 A ~ 1C is a cross-sectional view showing a conventional two-stage metal petrification process applied to a MOS transistor; and Figures 2A to 2D show two-stage characteristics applied to a ㈣ transistor according to the present invention. A cross-sectional view of the flow where metal titanium is formed to form a metal silicide. Example Next, please refer to FIGS. 2A to 2D to understand the present invention more clearly.
五、發明說明（4) 之金屬石夕化物製程；首先，請參看第2A圖係於一半導 矽基板20上形成有複數個淺溝槽隔離區STI，用以定義出 π件之主動區。而在該淺溝槽隔離區ST ^間則形成有一 極結構22 ’纟包括一閘氧化層221，例如是二氧化矽層、 及其上方之閘電極222，例如是複晶矽閘電極、且於此閘 極結構22周圍則形成一絕緣間隙壁223。而在該閘極结構 22兩側之半導體矽基板2〇中則形成有一源/汲極24，其包 括離子之淡#雜區域241與濃摻雜區域242。 之後’要形成第一金屬層於此半導體矽基板的表面； 例如，請參看第2B圖’係以磁控直流濺鍍法濺鍍一第—金 屬鈇層261於此半導體矽基板20之表面，其厚度大體在 8 0〜2 0 0 A之間。再進行一離子混合佈植，以增加後續為 了要形成咬化金屬内之矽晶核數目以避免因為元件線寬縮 小而使其片阻值受到影響。例如，將能量為丨5〜4〇keV間之 石夕原子以5 X 1〇ΐ3〜1 x i〇i5at〇ms/cm2間之濃度佈植入該第一 金屬欽層261中’形成一摻有矽原子之第一金屬鈦層（未標 號）。 接下來’要形成第二金屬層於此第一金屬層的表面； 例如’請參看第2C圖，再次以磁控直流濺鍍法濺鍍—第二 金屬鈦層262於此第一金屬層262之表面，其厚度大體在 100~300A之間。至此，形成了本發明之未參與矽化反應 之鈦金屬層26。由於此金屬鈦層26中包括了矽原子，因此 增加了後續要形成矽化金屬内之晶核數目，故而能避免因 為元件線寬縮小而影響到其片阻值之效應。 13471 1__ 五、發明說明（5) 緊接著’要進行熱退火製程以於該閘極、源極、與汲 極之表面形成一金屬矽化物；為了形成具有低接觸阻值以 及片阻值之金屬石夕化物，因此於本實施例中所採用的係為 兩階段矽化金屬製程；例如，將於第2C圖中所獲得的產物 送入快速熱退火反應室中（未顯示），以6 5 0 ~ 7 5 0 °C之溫度 進行第一階段的快速熱退火製程，為時大體為2 〇 ~ 5 〇秒， 以使金屬鈦2 6與複晶矽閘電極2 2 2及位於源/汲極2 4表面之 矽基板反應，而於複晶矽閘電極22 2及源/汲極24表面形成 一金屬矽化鈦層（未顯示）。之後，再以8 5 0 ~ 9 5 0 °C間之溫 度’進行第二階段的快速熱退火製程，為時大體為15〜45 秒’以使該金屬矽化鈦層（未顯示）進行晶相轉移反應，而 形成一阻值較低之矽化鈦層。接著，移除先前未參與反應 之金屬鈦層’例如，以氟化碳為反應氣體，利用活性離子 餘刻法（RI E )，進行選擇性的姓刻步驟，以姓刻未參與反 應的金屬鈦層’而形成了如第2D圖所示之金屬矽化鈦層 28 = 於本發明中，由於將形成金屬鈦的步驟分成兩階段進 行，所以於各階段所形成的金屬鈦層厚度皆不若習知者 厚’因此，將破原子佈植入第一階段所形成的金屬鈦之能 量不需如習知所需佈植之能量高，故而不會產生暫態加速 擴散（T E D )，而形成插空隙型缺陷，元件之工作性能也不 會降低，亦即不會發生如穿透、臨界電壓下降、飽和或截 止電流改變…等等的問題，元件的良率（y i e 1 d)因此提 升0V. Description of the invention (4) The metal fossil process; first, referring to FIG. 2A, a plurality of shallow trench isolation regions STI are formed on a semi-conductive silicon substrate 20 to define an active region of a π component. A polar structure 22 ′ is formed between the shallow trench isolation regions ST ′, and includes a gate oxide layer 221, such as a silicon dioxide layer, and a gate electrode 222 thereon, such as a polycrystalline silicon gate electrode, and An insulating spacer 223 is formed around the gate structure 22. A source / drain 24 is formed in the semiconductor silicon substrate 20 on both sides of the gate structure 22, and includes a light-doped region 241 and a heavily-doped region 242. Afterwards, 'a first metal layer is to be formed on the surface of this semiconductor silicon substrate; for example, refer to FIG. 2B', a first-metal hafnium layer 261 is sputtered on the surface of this semiconductor silicon substrate 20 by magnetron DC sputtering. Its thickness is generally between 80 and 2 0 A. Another ion implantation was performed to increase the number of silicon nuclei in the subsequent formation of bite metal to prevent the chip resistance from being affected by the reduction of the line width of the device. For example, the first metal chin layer 261 is formed by implanting a stone Xi atom with an energy between 5 and 40 keV at a concentration between 5 X 10 and 3 x 1 at 5 ms / cm2 to form a doped The first metallic titanium layer (not labeled) of silicon atoms. Next, 'a second metal layer is to be formed on the surface of this first metal layer; for example,' please refer to FIG. 2C, and again use magnetron DC sputtering to sputter the second metal titanium layer 262 on this first metal layer 262. The thickness of the surface is between 100 ~ 300A. So far, the titanium metal layer 26 of the present invention which has not participated in the silicidation reaction is formed. Since the silicon titanium layer 26 includes silicon atoms, the number of crystal nuclei in the subsequent formation of silicided metal is increased, so that the effect of reducing the line width of the device to affect its sheet resistance can be avoided. 13471 1__ 5. Description of the invention (5) Immediately followed by a 'thermal annealing process to form a metal silicide on the surface of the gate, source, and drain; in order to form a metal with low contact resistance and sheet resistance Lithium oxide, so the system used in this embodiment is a two-stage silicidation metal process; for example, the product obtained in Figure 2C is sent to a rapid thermal annealing reaction chamber (not shown) at 6 5 0 The first stage of the rapid thermal annealing process is performed at a temperature of ~ 750 ° C, which is generally 200 ~ 500 seconds, so that the metal titanium 26 and the polysilicon gate electrode 2 22 are located at the source / drain. The silicon substrate on the surface is reacted, and a titanium titanium silicide layer (not shown) is formed on the surface of the polycrystalline silicon gate electrode 22 2 and the source / drain electrode 24. Then, the second stage of the rapid thermal annealing process is performed at a temperature between 850 to 950 ° C, which is generally 15 to 45 seconds, so that the metal titanium silicide layer (not shown) undergoes a crystal phase. The transfer reaction forms a titanium silicide layer with lower resistance. Next, remove the previously unreacted metal titanium layer. For example, using carbon fluoride as the reaction gas, and using the reactive ion post-etching method (RI E), a selective surname engraving step is performed to nick the unreacted metal Titanium layer 'to form a metal titanium silicide layer as shown in FIG. 2D 28 = In the present invention, since the step of forming metal titanium is divided into two stages, the thickness of the metal titanium layer formed at each stage is not the same The learner is thick '. Therefore, the energy of implanting atomic cloth into the metal titanium formed in the first stage does not need to be as high as the energy required for conventional implantation, so it does not produce transient accelerated diffusion (TED). Inserting a gap-type defect will not reduce the working performance of the component, that is, no problems such as penetration, lowering of the threshold voltage, saturation or change of the cut-off current, etc., and the yield of the component (yie 1 d) is therefore improved. 0
43471 1 五、發明說明¢6) 此外，本發明之製程簡易，因而不會造成製造時之成 本及複雜度（complexity)增加。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍内，當可作更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。43471 1 V. Description of the invention ¢ 6) In addition, the process of the present invention is simple, so it will not increase the cost and complexity of the manufacturing process. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.