JP3528892B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a metal compound film is formed in a self-aligned manner on a surface portion of an impurity region by reacting with a metal.

[0002]

2. Description of the Related Art As one method for miniaturizing and speeding up a semiconductor device, a metal compound film is formed in a self-aligned manner on the surface of a diffusion layer or wiring. FIG. 5 shows L
CMO having a DD structure and having such a metal compound film
The conventional example of the manufacturing method of an S transistor is shown. In this conventional example, as shown in FIG.
A SiO ₂ film 12 is formed on the surface of the substrate by the LOCOS method to determine the element isolation region.

After that, an NMOS channel region 13 which is a P well and a PMOS channel region 14 which is an N well are formed, and a SiO ₂ film 15 as a gate oxide film is formed on the surface of the element active region. Then, the polycrystalline Si film 16
A gate electrode is formed by using the polycrystalline Si film 16 and SiO 2.
_{2 Using the} film 12 as a mask, the NMOS channel region 13
As and BF ₂ are ion-implanted into the PMOS channel region 14 and the PMOS channel region 14, respectively, to form a low-concentration diffusion layer 17 for the LDD structure,
18 is formed.

After that, a side wall oxide film of the gate electrode is formed by the SiO ₂ film 21, and the polycrystalline Si film 16 and the SiO ₂ film 1 are formed.
Using the masks 2 and 21, the NMOS channel region 13
And As and BF ₂ are ion-implanted into the PMOS channel region 14 and the PMOS channel region 14, respectively, with a dose amount of 1 × 10 ¹⁵ cm ⁻² or more. Then, the impurities are activated by rapid thermal processing to form the high-concentration diffusion layers 22 and 23 as the source / drain,
The Ti film 24 is deposited on the entire surface.

Then, the Si substrate 11, the polycrystalline Si film 16 and the Ti film 2 are subjected to a rapid heat treatment at 650 ° C. for 30 seconds.
The TiSi _x film is formed on the surface portions of the Si substrate 11 and the polycrystalline Si film 16 by reacting them at the contact portion with 4.
Then, the unreacted Ti remaining on the SiO ₂ films 12 and 21
The film 24 is removed with H ₂ SO ₄ / H ₂ O ₂ .

After that, high-speed heat treatment at 800 ° C. for 30 seconds is performed again, and as shown in FIG.
A low resistance TiSi _x film 25 is formed on the surface of the polycrystalline Si film 16 in a self-aligned manner. Then, a conventionally known process is further executed to perform the NMOS transistor 26 and PM
The CMOS transistor 28 including the OS transistor 27 is completed.

[0007] In the above such conventional example, dispersed expand the diffusion layer 22 is a source / drain of the NMOS transistor 26
Because they are formed by engaging the number of small As, the diffusion layer 22
It is possible to manufacture the fine CMOS transistor 28 by making the junction depth shallow and suppressing the short channel effect.

[0008]

By the way, FIG. 3 is formed from a polycrystalline Si film containing no impurities, a polycrystalline Si film in which As is ion-implanted, and a polycrystalline Si film in which BF ₂ is ion-implanted. The relationship between the width of the TiSi _x wiring and the sheet resistance thereof is shown. As is clear from FIG. 3, when As is used as an impurity, when the wiring width is narrowed, the thin line effect that the silicide reaction between Ti and Si is suppressed and the sheet resistance sharply increases appears.

Therefore, in the above-mentioned conventional example, the diffusion layer 22 as the source / drain of the NMOS transistor 26 is used.
Although the TiSi _x film 25 was formed on the surface of the device, the sheet resistance of the diffusion layer 22 was not sufficiently low, and it was difficult to manufacture the CMOS transistor 28 having a high operating speed.

[0010]

A method for manufacturing SUMMARY OF semiconductor device according to claim 1, to introduce the phosphorus ion implanted into the semiconductor region
By amorphizing the introduction part by
The phosphorus introduced into the semiconductor region is 550 ° C. or more and 600 ° C.
To and forming a metal compound film on the surface portion forming an impurity region by in activating the heat treatment temperature, by reacting with the metal surface portion of the impurity region below Is characterized by.

A method of manufacturing a semiconductor device according to claim 2 is the same as the method of manufacturing a semiconductor device according to claim 1, wherein 1 × 10 ¹⁵ cm
^-The above introduction is performed with a dose amount of not less than ^{2 and not} more than 5 × 10 ¹⁵ cm ^-2
Cormorant is characterized in that.

In the method of manufacturing a semiconductor device according to the first aspect, since the impurity region is formed of phosphorus, even if a metal compound film is formed on the surface of the impurity region, the thin line effect of the impurity region is suppressed and prevented. can do. Moreover, the semiconductor area
Temperature limit of heat treatment to activate phosphorus introduced into the zone
Although the temperature is relatively low at 550 ° C,
Since the introduction part is made amorphous with the introduction, this
Is activated at a high rate even by a relatively low temperature heat treatment such as
Can be made. Moreover, the upper limit temperature of the heat treatment is 600 ° C.
Since it is less than less, it suppresses the diffusion of phosphorus due to heat treatment.
You can

According to the method of manufacturing a semiconductor device of claim 2, 1
× 10 ¹⁵ cm ^-2 or more 5 × 10 ¹⁵ cm ^-2 or less of high dose
Since the introduction of phosphorus into the semiconductor region in an amount, extent 550 ° C.
This phosphorus can be activated at a high rate even by heat treatment at a relatively low temperature .

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION A CM having a dual gate structure will be described below.
An embodiment of the present invention applied to manufacturing an OS transistor will be described with reference to FIGS. In the present embodiment, as shown in FIG. 1A, S is formed on the surface of the Si substrate 31 by the LOCOS method of performing wet oxidation at 950 ° C.
An iO ₂ film 32 is formed to determine an element isolation region.

After that, a P well is formed in the formation region of the NMOS transistor, a buried layer (not shown) for preventing punch-through between the source / drain of the NMOS transistor is formed, and a threshold voltage of the NMOS transistor is formed. Impurities for adjusting the Si substrate 3
1 is selectively ion-implanted into the NMOS channel region 3
3 is formed.

Further, an N well is formed in the formation region of the PMOS transistor, a buried layer (not shown) for preventing punch-through between the source / drain of the PMOS transistor is formed, and a threshold voltage of the PMOS transistor is formed. Impurities for adjusting the Si substrate 31
Is selectively ion-implanted into the PMOS channel region 34
To form.

After that, by a pyrogenic oxidation at 850 ° C. using H ₂ / O ₂ , a SiO ₂ film 35 having a thickness of 8 nm is used as a gate oxide film on the surface of the element active region surrounded by the SiO ₂ film 32. Form. And SiH ₄
Is used as a source gas and a low-pressure CVD method at a deposition temperature of 620 ° C. is performed to deposit a polycrystalline Si film 36 having a thickness of 150 nm.

After that, a resist (not shown) is applied on the polycrystalline Si film 36, and this resist is processed into a pattern of the gate electrode by a lithography method. Then, the polycrystalline Si film 36 is subjected to anisotropic etching using the resist as a mask and Cl ₂ / O ₂ as an etching gas.

Next, as shown in FIG. 1B, polycrystalline Si
20 keV using the film 36 and the SiO ₂ film 32 as a mask
As ⁺ and a dose amount of 5 × 10 ¹³ / cm ² , As ⁺ is selectively ion-implanted into the NMOS channel region 33 to form a low-concentration diffusion layer 37 for the LDD structure.

Further, the polycrystalline Si film 36 and the SiO ₂ film 3
With 2 as a mask, acceleration energy of 20 keV and 2
PMOS channel region 3 with a dose of × 10 ¹³ / cm ²
4 is selectively ion-implanted with BF ₂ ⁺ to form a low-concentration diffusion layer 38 for the LDD structure. And the film thickness is 150
nm SiO ₂ film 41 is deposited by the low pressure CVD method, and
The O ₂ film 41 is anisotropically etched to form a side wall oxide film made of the SiO ₂ film 41 on the side surface of the polycrystalline Si film 36.

Next, as shown in FIG. 1C, a 10 nm-thickness SiO ₂ film 42 is deposited by a low pressure CVD method using TEOS as a source gas and a deposition temperature of 700 ° C. And an acceleration energy of 20 keV and 3 × 10 ¹⁵ / c
BF ₂ ⁺ is selectively ion-implanted into the PMOS channel region 34 with a dose amount of m ² , and B is activated by a rapid thermal treatment at 1000 ° C. for 10 seconds to form a high-concentration diffusion layer as a source / drain. 43 is formed.

The SiO ₂ film 42 suppresses channeling during BF ₂ ⁺ ion implantation. Also, BF
_{Since 2} ⁺ is also ion-implanted into the polycrystalline Si film 36 on the PMOS channel region 34, a P ⁺ type gate electrode is formed on the PMOS channel region 34.

Next, as shown in FIG. 2A, after removing the SiO ₂ film 42 with an HF solution, NMO is performed with an acceleration energy of 20 keV and a dose amount of 3 × 10 ¹⁵ / cm ^2.
Phos ⁺ is selectively ion-implanted into the S channel region 33. At this time, Si in the NMOS channel region 33
The surface of the substrate 31 and the surface of the polycrystalline Si film 36 are made amorphous.

Thereafter, a heat treatment is carried out in N ₂ at 650 ° C. for 1 hour to form Si which has been made amorphous.
The surface of the substrate 31 and the surface of the polycrystalline Si film 36 are recrystallized, and Phos is activated to form a high-concentration diffusion layer 44 as a source / drain.

Since Phos ⁺ is also ion-implanted into the polycrystalline Si film 36 on the NMOS channel region 33,
An N ⁺ type gate electrode is formed on the NMOS channel region 33. After that, the Ti film 45 is deposited on the entire surface by the sputtering method.

Next, the Si substrate 31, the polycrystalline Si film 36 and the Ti film 4 are subjected to a rapid heat treatment at 650 ° C. for 30 seconds.
The TiSi _x film is formed on the surface portions of the Si substrate 31 and the polycrystalline Si film 36 by reacting them at the contact portion with 5.
Then, the unreacted Ti remaining on the SiO ₂ films 32 and 41
The film 45 is removed with H ₂ SO ₄ / H ₂ O ₂ .

After that, high-speed heat treatment at 800 ° C. for 30 seconds is performed again, and as shown in FIG.
A low resistance TiSi _x film 46 is formed on the surface of the polycrystalline Si film 36 in a self-aligned manner.

Next, as shown in FIG. 2 (c), an interlayer insulating film 47, and a contact hole 48 for TiSi _x film 46 on the interlayer insulating film 47. And the Al wiring 5
No. 1 is formed, and a conventionally known process is performed to perform NMO.
A CMOS transistor 54 having an S transistor 52 and a PMOS transistor 53 is completed.

By the way, as shown in FIG. 4, 1 × 10 ¹⁵ /
When Phos is ion-implanted with a high dose amount of about cm ² or more, this Phos can be activated at a high rate even by heat treatment at a relatively low temperature of about 550 ° C. This is because the Si substrate 31 and the polycrystalline Si film 36 are efficiently amorphized by ion implantation with a high dose amount, and when these are recrystallized, Phos moves to the lattice point.

That is, since the recrystallization of the Si substrate 31 and the polycrystalline Si film 36 starts at a temperature of about 550 ° C. or higher and activation occurs, even if the heat treatment is performed at a relatively low temperature, the polycrystalline S
It is possible to reduce the resistance of the i film 36 and to form the diffusion layer 44 having a low resistance. In the above embodiment, TiS is formed on the surface portions of both the polycrystalline Si film 36 which is the gate electrode and the diffusion layers 43 and 44 which are the source / drain.
Although the i _x film 46 is formed, the TiSi _x film 46 may be formed only on one surface portion of these.

Further, although the present invention is applied to the manufacture of the dual-gate structure CMOS transistor in the above embodiments, the invention of the present application is also applied to the manufacture of a single-gate structure CMOS transistor or a semiconductor device other than the CMOS transistor. Can be applied.

[0032]

According to the method of manufacturing a semiconductor device of claims 1 and 2 , even if the metal compound film is formed on the surface of the impurity region,
Since the thin line effect in the impurity region can be suppressed or prevented, a fine semiconductor device having a high operation speed can be manufactured. Moreover, since the phosphorus introduced to form the impurity region can be activated at a high rate even by the heat treatment at a relatively low temperature, it is possible to suppress the diffusion of phosphorus accompanying the heat treatment, and to reduce the impurities with a shallow junction depth. The region can be formed, and a finer semiconductor device can be manufactured .

[Brief description of drawings]

FIG. 1 is a side sectional view showing a first half of an embodiment of the present invention in process order.

FIG. 2 is a side sectional view showing the latter half of one embodiment in process order.

FIG. 3 is a graph showing the relationship between the width of TiSi _x wiring and sheet resistance.

FIG. 4 is a graph showing the relationship between the heat treatment temperature and the activation rate of ion-implanted phosphorus.

FIG. 5 is a side sectional view showing a conventional example of the invention of the present application in the order of steps.

[Explanation of symbols]

11 Si substrate (semiconductor region) 36 polycrystalline Si film (semiconductor region, impurity regions) 44 diffusion layer (an impurity region) 45 Ti film (metal) 46 TiSi _x film (metal compound film)

─────────────────────────────────────────────────── --Continued from the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/28 301 H01L 21/3205 H01L 21/265 H01L 21/8238 H01L 27/092

Claims (2)

(57) [Claims] 1. Phosphorus is ion-implanted into a semiconductor region .
By amorphizing the introduced portion by heating the phosphorus introduced into the semiconductor region to 550 ° C. or higher 60
0 comprising the steps of forming an impurity region by in activating the heat treatment at temperatures below ° C., and forming a metal compound film on said surface portion and a surface portion and the metal are reacted in the impurity regions A method of manufacturing a semiconductor device, comprising: 2. 1 × 10 ¹⁵ cm ^-2 or more 5 × 10 ¹⁵ cm ^-2
The method for manufacturing a semiconductor device according to claim 1 , wherein the introduction is performed with the following dose amount .