JP2751895B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a CMOS structure which has a low-resistance silicide layer in a source / drain region and realizes miniaturization of a MOS transistor.

[0002]

2. Description of the Related Art With the recent miniaturization of semiconductor devices, the area of source / drain regions is reduced, and the electrical resistance of wiring connected thereto is increased. A semiconductor device having a MOS transistor in which a low-resistance high-melting-point metal silicide layer is formed in a drain region has been proposed. Such a semiconductor device is composed of a p-channel MOS transistor and an n-channel MOS transistor.
When applied to a semiconductor device having a CMOS structure including transistors, a process shown in FIG. 10 is conventionally employed.

First, as shown in FIG. 10A, an n-well 102 is formed on a p-type silicon substrate 101, and an element isolation insulating film 103, a gate insulating film 104, and a gate electrode 105 are formed on the surface thereof. In the above, p is
The p-type LDD 109 and the source / drain region 115 are formed by introducing a p-type impurity, and the n-type LDD 107 and the n-type source / drain 107 are introduced into the p-type silicon substrate 101 by introducing an n-type impurity.
A drain region 112 is formed. Then, a high-melting-point metal 116 such as titanium or cobalt is deposited on the entire surface, and further heat-treated to cause the high-melting-point metal 116 to react with silicon. Thereafter, the unreacted high-melting-point metal is removed by etching. As shown in FIG. 10B, a low-resistance silicide layer 117 is selectively formed in each of the source / drain regions 112 and 115.
Is formed.

[0004]

However, in this manufacturing method, as the width of the pattern becomes smaller, the silicide layer 1 formed in the n-type source / drain region 112 becomes smaller.
It was clarified that the layer resistance of No. 17 increased. That is, if the arsenic or phosphorus impurities forming the n-type source / drain regions 112 are present at a high concentration on the silicon surface, the reaction between the refractory metal and the silicon is hindered, thereby lowering the resistance.

Further, in the conventional semiconductor device having a CMOS structure, there is a problem that it is difficult to miniaturize a p-type MOS transistor. That is, when the source / drain regions 115 of the p-type MOS transistor are formed, a p-type impurity such as boron or BF ₂ is ion-implanted to 1 ×.
About 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² needs to be introduced into the n-well 102 and activated. At this time, it is necessary to lower the energy of the ion implantation to reduce the junction depth of the impurity layer with the miniaturization of the p-type MOS transistor, but the current ion implantation technology has a limit of about 10 KeV.
In addition, when the voltage is 30 KeV or less, the injection current is reduced, so that the injection time is significantly increased, so that the manufacturing time of the semiconductor device is increased and the cost is increased.

In order to deal with such a problem, the former increase in the resistance value of the silicide layer 117 in the n-type source / drain region 112 is, for example, described in the 1994 IEDM.
One solution is proposed in Technical Digest pages 687-690. As shown in FIG. 11, after an n-type source / drain region 112 is formed, silicon is epitaxially grown in this region to form a silicon layer 113 containing no impurities, and then a high melting point metal is deposited on the entire surface. And forming a silicide layer by reacting the refractory metal with a silicon layer containing no impurities by heat treatment.
In this manufacturing method, it is possible to suppress the increase in the resistance of the silicide layer in the n-type source / drain regions, but it is difficult to satisfy the latter requirement of rapidly forming the p-type source / drain regions having a shallow junction. .

An object of the present invention is to reduce the resistance of a silicide layer in an n-type source / drain region, and to quickly form a p-type source / drain region having a shallow junction depth, thereby miniaturizing the structure. It is an object of the present invention to provide a method of manufacturing a semiconductor device having a CMOS structure capable of operating at high speed.

[0008]

According to a manufacturing method of the present invention, after forming a gate insulating film and a gate electrode of a pMOS transistor and an nMOS transistor on a silicon substrate, an impurity is introduced into the nMOS transistor to form a source / source transistor.
Forming a drain region, forming a silicon layer on each source / drain region of the nMOS transistor and the pMOS transistor, and ion-implanting the source / drain into the pMOS transistor through the silicon layer.
The method includes a step of forming a drain region and a step of depositing a refractory metal on the entire surface and reacting the refractory metal with the silicon layer to form a refractory metal silicide layer.

[0009]

Next, an embodiment of the present invention will be described with reference to the drawings. 1 to 5 show the first embodiment of the present invention.
FIG. 4 is a cross-sectional view showing the embodiment in the order of manufacturing steps. First, as shown in FIG. 1A, an n-well 102 is formed on a p-type silicon substrate 101, and an element isolation insulating film 103, a gate insulating film 104, and a gate electrode 10 are formed on the surface of the substrate 101.
5 is formed. In this embodiment, a single polysilicon layer is used for the gate electrode 105, but a stacked structure of silicide / polysilicon may be used. Next, as shown in FIG. 1B, the pMOS transistor region is
06, and implanted 2 × 10 ¹³ / cm ² ions of an n-type impurity into the nMOS transistor region at 30 KeV to form a low-concentration source / drain region, that is, an n-type LDD.
A region 107 is formed. Next, as shown in FIG. 2A, the nMOS transistor region is
Then, a p-type LDD region 109 is formed by implanting 2 × 10 ¹³ ions / cm ² of p-type impurities into the pMOS transistor region at 10 KeV. And 1000
Each of the LDD regions 107 and 109 is heat-treated at 10 ° C. for 10 seconds.
Activate.

Next, as shown in FIG. 2B, a silicon oxide film is deposited on the entire surface and is anisotropically etched to form a side wall 11 on the side of the gate electrode 105.
0 is formed. Then, as shown in FIG.
After covering the transistor region with a photoresist 111, an n-type impurity such as arsenic is added to the source / drain formation region of the nMOS transistor at 30 KeV at 3 × 10 ¹⁵ / c.
m ² ions are implanted and then activated by a heat treatment at 1000 ° C. for 10 seconds to form a high concentration n-type source / drain region 112.

[0011] Then, as shown in FIG. 3 (b), Si ₂
10 ⁻³ Pa (Pascal) in the atmosphere of H ₆ , 600 to 70
Under a condition of 0 ° C., a silicon layer 113 is selectively epitaxially grown in a region where silicon is exposed. As the selective epitaxial growth method, 1995 Sympo
SIUM ON VLSI TECHNOLOGY21
The technology on page 22 is employed. Next, as shown in FIG. 4A, an nMOS transistor region is
And then, for example, B
3 × 10 ¹⁵ / cm 3 at 30 KeV for p-type impurities such as F ₂
² ions are implanted to form a high-concentration p-type source / drain region 115 of the pMOS transistor.
Activated by heat treatment for seconds. As a result, the junction depth below the surface of the substrate 101 before the epitaxial growth becomes smaller by the thickness of the epitaxial silicon layer 113 than in the case where the source / drain regions 115 to be formed are ion-implanted without epitaxial growth. For example, when the thickness of the silicon layer 113 is 30 nm, the channel length is about 0.1 compared with the case where ion implantation is performed without epitaxial growth.
μm is improved.

Next, as shown in FIG. 4B, for example, titanium 116 is deposited on the entire surface to a thickness of 30 nm and heat-treated at 640 ° C. for 20 seconds in a nitrogen atmosphere. In a pMOS transistor, the silicon layer 113 and titanium 116 and the epitaxial silicon layer 113 containing BF ₂ and titanium 116 undergo silicide reactions, and as shown in FIG. 5A, a silicon layer 113 having a thickness of about 30 nm is formed on the surface of the silicon layer 113. A titanium silicide layer 117 is formed, and a titanium nitride 118 is formed on the surface of titanium silicide layer 117. Further, a titanium silicide layer is not formed on the sidewalls 110, but is entirely made of titanium nitride 118. However, the titanium silicide layer 117 formed here is C
High-resistance titanium silicide called 49 structure.

When titanium nitride 118 is selectively removed with a mixed solution of ammonia and hydrogen peroxide, titanium silicide layer 117 is selectively left on source / drain regions 112 and 115 and gate electrode 105.
Next, when heat treatment is performed at 850 ° C. for 10 seconds in a nitrogen atmosphere, the titanium silicide layer having a high resistance C49 structure is phase-converted to a low resistance C56 structure, and the titanium silicide layer 117 is formed.
Has a layer resistance of about 7Ω / □. Next, an interlayer insulating film 119 and a metal wiring 120 are formed by a known method, and FIG.
As described above, a semiconductor device having a CMOS structure is completed.

Therefore, in this embodiment, the nMOS
In the transistor, the source / drain region 112
Epitaxial silicon layer 113 containing no impurity thereon
Is formed, and then the silicide layer 117 of the refractory metal is formed, so that the resistance of the n-type source / drain 113 can be reduced. When the source / drain regions 115 of the pMOS transistor are formed, ions are implanted through the epitaxially grown epitaxial silicon layer 113.
5 can be formed shallow. As a result, it is not necessary to lower the energy of ion implantation, and it is possible to prevent an increase in implantation time and to manufacture the semiconductor device quickly and at low cost.

FIGS. 6 to 8 show a second embodiment of the present invention. In the first embodiment, the p-type LDD 109 of the pMOS transistor is formed. However, if the width of the sidewall 110 is small, it is not necessary to form the LDD. In FIG. 6A, after the n-type LDD 107 of the nMOS transistor is formed, as shown in FIG.
The sidewall 110 is formed without forming the p-type LDD of the OS transistor. Then, as shown in FIG.
MOS transistor n-type source / drain region 112
Is formed, and then the silicon layer 113 is formed as shown in FIG.
Is selectively epitaxially grown to form p-type source / drain regions 115 of the pMOS transistor of FIG.
At this time, if the width of the sidewall 110 is about 50 nm, the junction of the p-type source / drain region 115 of the pMOS transistor reaches the end of the gate electrode.
No DD is required. Subsequent steps are the same as those in FIG.

FIG. 9 shows a third embodiment of the present invention. In the first embodiment, the silicon layer is formed also on the gate electrode 105 by performing silicon selective epitaxial growth. However, the impurity ion implantation of the source / drain region 115 of the pMOS transistor is performed by forming the silicon layer 113 by selective epitaxial growth. Since this is performed later, it is not always necessary to form a silicon layer on the gate electrode 105. For example, as shown in FIG. 9A, when the gate electrode 105 is formed, an insulating film 121 such as silicon oxide is formed on the gate electrode 105 to a thickness of about 100 nm. As in FIG.
(B) As shown in FIG.
07, when the p-type LDD 109 of the pMOS transistor is formed and the sidewall 110 is formed, the silicon substrate 101 is exposed only in the source / drain regions. After that, it is the same as FIG.

In the above description, an example in which titanium is used as the high melting point metal is shown. However, the present invention can be similarly applied to other high melting point metals such as cobalt and molybdenum.

[0018]

As described above, the present invention provides an nMOS
In the transistor, since a silicide layer of a high melting point metal is formed after forming a silicon layer containing no impurities on the source / drain regions, the resistance of the n-type source / drain can be reduced. Similarly, a high-melting-point metal silicide layer can be formed in the source / drain region of the pMOS transistor, and when the source / drain region is formed, ions are implanted through the silicon layer. It can be formed to be shallow. As a result, the source / drain regions of the shallow pMOS transistor can be formed without having to lower the energy of ion implantation, and an increase in implantation time can be prevented, thereby enabling rapid and low-cost manufacturing.

[Brief description of the drawings]

FIG. 1 is a first sectional view showing the manufacturing method of the first embodiment in the order of the manufacturing steps.

FIG. 2 is a second sectional view illustrating the manufacturing method of the first embodiment in the order of the manufacturing steps.

FIG. 3 is a third sectional view showing the manufacturing method of the first embodiment in the order of the manufacturing steps;

FIG. 4 is a fourth sectional view showing the manufacturing method of the first embodiment in the order of the manufacturing steps;

FIG. 5 is a fifth sectional view showing the manufacturing method of the first embodiment in the order of the manufacturing steps.

FIG. 6 is a first sectional view showing the manufacturing method of the second embodiment in the order of the manufacturing steps;

FIG. 7 is a second sectional view illustrating the manufacturing method of the second embodiment in the order of the manufacturing steps.

FIG. 8 is a third sectional view showing the manufacturing method of the second embodiment in the order of the manufacturing steps.

FIG. 9 is a cross-sectional view illustrating the manufacturing method of the third embodiment in the order of manufacturing steps.

FIG. 10 is a sectional view showing an example of a conventional manufacturing method in the order of steps.

FIG. 11 is a cross-sectional view showing another example of a conventional manufacturing method.

[Explanation of symbols]

 Reference Signs List 101 silicon substrate 103 element isolation insulating film 105 gate electrode 107 n-type LDD 109 p-type LDD 110 sidewall 112 n-type source / drain region 113 epitaxial silicon layer 115 p-type source / drain region 116 titanium 117 titanium silicide layer 118 titanium nitride 119 Interlayer insulating film 120 Metal wiring

Claims (6)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a pMOS transistor and an nMOS transistor, wherein a refractory metal silicide layer is formed at least in a source / drain region of each transistor. Forming a source / drain region by introducing impurities into the nMOS transistor after forming the gate insulating film and the gate electrode;
A step of forming a silicon layer on each source / drain region of the S transistor and the pMOS transistor; a step of forming a source / drain region by ion-implanting the pMOS transistor through the silicon layer; A method for manufacturing a semiconductor device, comprising: depositing a metal and reacting the metal with the silicon layer to form a refractory metal silicide layer. 2. A method of manufacturing a semiconductor device having a pMOS transistor and an nMOS transistor, wherein a refractory metal silicide layer is formed at least in a source / drain region of each transistor. After forming the gate insulating film and the gate electrode, a step of introducing n-type impurities into both MOS transistors to form low-concentration source / drain regions, and forming sidewalls on the side walls of the gate electrode of each MOS transistor Forming a high-concentration source / drain region by ion-implanting impurities into the nMOS transistor;
Forming an epitaxial silicon layer on each source / drain region of the MOS transistor by a selective epitaxial method, and pMO
Forming a high-concentration source / drain region by ion-implanting p-type impurities into the S transistor; depositing a high-melting-point metal on the entire surface; and reacting with the silicon layer to form a high-melting-point metal silicide layer And a step of removing a high-melting-point metal that is not silicided. 3. The method of manufacturing a semiconductor device according to claim 2, wherein a step of forming a low concentration source / drain region is not included in the source / drain region of the pMOS transistor. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the silicon layer formed on the source / drain regions is silicon containing no impurities. 5. The high melting point metal is any one of titanium, cobalt, and molybdenum, and the high melting point silicide layer is any one of a titanium silicide layer, a cobalt silicide layer, and a molybdenum silicide layer. A method for manufacturing such a semiconductor device. 6. The method according to claim 1, wherein the thickness of the silicon layer formed in the source / drain region is at least 30 nm.