CN103871967A - Forming method of CMOS (complementary metal oxide semiconductor) transistor - Google Patents
Forming method of CMOS (complementary metal oxide semiconductor) transistor Download PDFInfo
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- CN103871967A CN103871967A CN201210553012.8A CN201210553012A CN103871967A CN 103871967 A CN103871967 A CN 103871967A CN 201210553012 A CN201210553012 A CN 201210553012A CN 103871967 A CN103871967 A CN 103871967A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
Abstract
The invention provides a forming method of a CMOS (complementary metal oxide semiconductor) transistor. The method comprises the following steps that a semiconductor substrate comprising a first region and a second region is provided; a first grid electrode structure is formed on the first region, and a second grid electrode structure is formed on the second region; a first photoresist layer covering the first grid electrode structure and the first region positioned at the two sides of the first grid electrode structure is formed; the first photoresist layer and the second grid electrode structure are used as masks, and grooves are formed in the second region positioned at the two sides of the second grid electrode structure; the first photoresist layer is removed; germanium-silicon layers are formed in the grooves and on the first region positioned at the two sides of the first grid electrode structure, and the germanium-silicon layers fully fill the grooves; a second photoresist layer covering the second grid electrode structure and the second region positioned at the two sides of the second grid electrode structure is formed; the second photoresist layer is used as the mask for removing the germanium-silicon layers arranged on the first region positioned at the two sides of the first grid electrode structure; the second photoresist layer is removed; silicon layers are formed on the first region positioned at the two sides of the first grid electrode structure and the germanium-silicon layers arranged at the two sides of the second grid electrode structure. The forming method of the CMOS transistor has the advantage that the process is simple.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of transistorized formation method of CMOS.
Background technology
CMOS (Complementary Metal Oxide Semiconductor) (Complementary Metal-Oxide-Semiconductor, CMOS) transistor has become semiconductor device conventional in integrated circuit.Described CMOS transistor comprises: P-type mos (PMOS) transistor and N-type metal-oxide semiconductor (MOS) (NMOS) transistor.
Along with the raising of component density and the integrated level of semiconductor device, the grid size of PMOS transistor or nmos pass transistor becomes than in the past shorter.But the grid size of PMOS transistor or nmos pass transistor shortens and can produce short-channel effect, and then produces leakage current, affects the transistorized electric property of CMOS.Prior art mainly, by improving the stress of transistor channel region, to improve carrier mobility, and then improves transistorized drive current, reduces the leakage current in transistor.
In prior art, in order to improve the stress of the transistorized channel region of PMOS, forming material in the transistorized source electrode of PMOS and drain electrode is the stressor layers of germanium silicon, between silicon and germanium silicon because lattice mismatch forms compression, thereby raising PMOS transistorized performance.In addition, along with reducing of feature sizes of semiconductor devices, the degree of depth of nmos pass transistor and PMOS transistor heavily doped region also needs corresponding reducing, to avoid heavily doped region to cross the short-channel effect of dark initiation, and then avoid transistor to leak electricity, improve the transistor reliability that forms.In order to form the heavily doped region that the degree of depth is less, in the time forming heavily doped region, need first above nmos pass transistor and the transistorized heavily doped region of PMOS, to form silicon layer, then the Semiconductor substrate of silicon layer and below thereof is carried out to Implantation, in Semiconductor substrate, form the more shallow little heavily doped region of the degree of depth.
Existing technique, in the time that formation comprises above-mentioned nmos pass transistor and the transistorized CMOS transistor of PMOS, comprises the steps:
Semiconductor substrate is provided, and described Semiconductor substrate comprises first area and second area, and described first area is used to form nmos pass transistor, and described second area is used to form PMOS transistor;
On described first area, form first grid structure, and form second grid structure on described second area;
On the first area of first grid structure both sides and the second area of second grid structure both sides, form silicon layer by epitaxial growth technology;
At described silicon layer and first grid structure and second grid body structure surface formation hard mask layer;
On the hard mask layer above first area, form photoresist layer;
Taking photoresist layer as mask, remove the hard mask layer of second area top by etching technics;
Remove described photoresist layer;
Taking the hard mask layer of first area top and second grid structure as mask, the silicon layer on second area and second area are carried out to etching, in the second area of second grid structure both sides, form groove;
In described groove, fill full germanium silicon layer;
Remove the hard mask layer of top, first area.
Although above-mentioned technique has improved the mobility of PMOS transistor channel region charge carrier in CMOS transistor, its complex process, need to carry out multiple etching technique, easily CMOS transistor is caused to damage, and the CMOS transistor performance forming is unstable.
The transistorized method of above-mentioned CMOS formed more please refer to the U.S. Patent application that publication number is US2011201164A1.
Summary of the invention
The problem that the present invention solves is to provide a kind of transistorized formation method of CMOS, improving in CMOS transistor in PMOS transistor channel region in carrier mobility, has simplified the transistorized technique of formation CMOS, the transistorized performance of the CMOS that forms better.
For addressing the above problem, the invention provides a kind of transistorized formation method of CMOS, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises first area and second area;
On described first area, form first grid structure, and form second grid structure on described second area;
Form the first photoresist layer that covers first grid structure and first area, first grid structure both sides;
Taking the first photoresist layer and second grid structure as mask, in the second area of second grid structure both sides, form groove;
Remove described the first photoresist layer;
In described groove and on first area, first grid structure both sides, form germanium silicon layer, described germanium silicon layer fills up described groove;
Form the second photoresist layer that covers second grid structure and second grid structure both sides second area;
Taking described the second photoresist layer as mask, remove the germanium silicon layer being positioned on first area, first grid structure both sides;
Remove described the second photoresist layer;
On the first area of described first grid structure both sides and the germanium silicon layer of second grid structure both sides, form silicon layer.
Compared with prior art, technical solution of the present invention has the following advantages:
Taking the first photoresist layer and second grid structure as mask, in the second area of second grid structure both sides, form groove, and after removing the first photoresist layer, in groove and on first area, first grid structure both sides, form germanium silicon layer, then first form the second photoresist layer that covers second grid structure and both sides second area thereof, remove again the germanium silicon layer that is positioned at first area upper surface, finally remove the second photoresist layer, and form silicon layer on the germanium silicon layer of the first area in described first grid structure both sides and second grid structure both sides and second area, due to the step of having omitted at first grid structure and the formation of second grid body structure surface and etching removal hard mask layer, can reduce to form the etching technics quantity in CMOS transistor process, simplify the transistorized formation technique of CMOS, can effectively avoid etching technics to cause damage to first grid structure and second grid body structure surface, improved the transistorized performance of formation CMOS simultaneously.
In addition, although technical scheme has increased the formation of photoresist layer and has removed technique in the present invention, but compare with removal technique with the deposition of hard mask layer, the deposition of photoresist layer and removal technique are simple, and it is less to the transistorized damage of CMOS to remove the required cineration technics of photoresist layer, therefore, in the present invention, technical scheme can effectively reduce and form CMOS transistorized technology difficulty, improve the transistorized performance of the CMOS that forms and rate of finished products.
Brief description of the drawings
Fig. 1 ~ Fig. 8 is the schematic diagram of transistorized formation method one embodiment of CMOS of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implemented but the present invention can also adopt other to be different from alternate manner described here, therefore the present invention is not subject to the restriction of following public specific embodiment.
Just as described in the background section, when existing formation CMOS transistor technology improves PMOS transistor channel region hole mobility by form germanium silicon layer in PMOS transistor heavily doped region, the transistorized formation complex process of CMOS, the transistorized unstable properties of the CMOS that forms.
Inventor finds through research, the transistorized formation method of existing CMOS complex process, the transistorized unstable properties of the CMOS that forms mainly caused by following reason: form germanium silicon layer in PMOS transistor heavily doped region in CMOS transistor time, before forming the groove of filling germanium silicon layer, first at silicon layer and first grid structure and second grid body structure surface formation hard mask layer, and before etching forms groove and in groove, fill the hard mask layer removal that formed at twice after full germanium silicon layer; In the time removing described hard mask layer by dry etch process, dry etch process is larger to the damage of the first grid structure below hard mask layer and second grid mechanism, and then has affected the transistorized performance of formation CMOS.
Inventor also finds through research, can cover first grid structure and first area, both sides the first photoresist layer thereof by formation, and taking the first photoresist layer as mask, in the second area of second grid structure both sides, form groove; But temperature is higher when forming germanium silicon layer by epitaxial growth technology in groove, and photoresist layer unstable properties, is easily removed, the first photoresist layer cannot continue the mask when forming germanium silicon layer.Therefore,, form germanium silicon layer in groove before, must first remove the first photoresist layer.Inventor also finds after further research, after groove in second area forms, can first in groove and on the first area of first grid structure both sides, form germanium silicon layer, then form the second photoresist layer of the second area that covers second grid structure and both sides thereof, and taking this second photoresist layer as mask, remove the germanium silicon layer on first area, first grid structure both sides, then on the first area of first grid structure both sides and on the germanium silicon layer of second grid structure both sides, form silicon layer, thereby omit in first grid structure and second grid body structure surface and formed hard mask layer, and the follow-up step of removing hard mask layer by etching technics, simplify the transistorized formation technique of CMOS, improve the transistorized performance of formation CMOS.
Below in conjunction with accompanying drawing 1 ~ Fig. 8, by specific embodiment, the transistorized formation method of CMOS of the present invention is described further.
With reference to figure 1, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 comprises first area 200a and second area 200b, between described first area 200a and second area 200b, is also formed with fleet plough groove isolation structure 202.
In the present embodiment, the material of described Semiconductor substrate 200 is monocrystalline silicon or silicon-on-insulator; Or the material that can also comprise other, the present invention does not limit this.The first area 200a of described Semiconductor substrate 200 is used to form nmos pass transistor, and second area 200b is used to form PMOS transistor.
In the present embodiment, the material of described fleet plough groove isolation structure 202 is silica, and the formation technique of described fleet plough groove isolation structure 202 is well known to those skilled in the art, and therefore not to repeat here.
It should be noted that, before the first area 200a to Semiconductor substrate 200 carries out subsequent technique, need first first area 200a to be carried out to the doping of p-type well region; And before the second area 200b to Semiconductor substrate 200 carries out subsequent technique, need first second area 200b to be carried out to the doping of N-shaped well region.
Continue with reference to figure 1, on described first area 200a, form first grid structure, and form second grid structure on described second area 200b.
Described first grid structure comprises the first grid dielectric layer 301 being positioned on the 200a of first area and is positioned at the first grid 303 on first grid dielectric layer 301; Described second grid structure comprises the second gate dielectric layer 401 being positioned on second area 200b and is positioned at the second grid 403 on second gate dielectric layer 401.The material of described first grid dielectric layer 301 and second gate dielectric layer 401 is silica, and the material of described first grid 303 and second grid 403 is polysilicon.
In the present embodiment, on described first grid 303, be formed with the first stop-layer 305; On described second grid 403, be formed with the second stop-layer 405.The material of described the first stop-layer 305 and the second stop-layer 405 can be silica, to protect respectively described first grid 303 and second grid 403 in subsequent technique.
In the present embodiment, on described first grid structure both sides first area 200a, be formed with the first skew clearance wall 307; On described second grid structure both sides second area 200b, be formed with the second skew clearance wall 407.The material of described the first skew clearance wall 307 and the second skew clearance wall 407 is silicon nitride, to be respectively used to protect first grid structure and second grid structure in subsequent technique.
With reference to figure 2, in formation coverage diagram 1, the first stop-layer 305, first grid structure both sides first are offset the first photoresist layer 204 of clearance wall 307 and first area 200a.
In the present embodiment, can be first form the first stop-layer 305, the second stop-layer 405, first grid structure both sides first in coverage diagram 1 and be offset clearance wall 307 and first area 200a, second grid structure both sides second and be offset the photoresist layer (not shown) of clearance wall 407 and second area 200b by spin coating proceeding, again to formed photoresist layer expose, developing process, expose the second stop-layer 405, second grid structure both sides second are offset clearance wall 407 and second area 200b.
With reference to figure 3, taking the first photoresist layer 204, the second stop-layer 405 and the second skew clearance wall 407 as mask, in second area 200b, form groove 409.
The method that forms described groove 409 can be dry etching, wet etching or its combination.In the present embodiment, form the method for groove 409 for first carrying out dry etching, then carry out wet etching.
Preferably, described groove 409 is the (sigma of Sigma, Σ) shape, so that the compression that the silicon crystal lattice mismatch in germanium silicon layer and the second area 200b of follow-up formation forms is larger, and then it is larger to make to put on compression in the PMOS transistor channel region of follow-up formation, is beneficial to the raising of PMOS transistor channel region hole mobility.
With reference to figure 4, remove the first photoresist layer 204 described in Fig. 3.
In the present embodiment, removing described the first photoresist layer 204 is cineration technics, and it has been well known to those skilled in the art, does not repeat them here.
Continue with reference to figure 4, groove 409 described in Fig. 3 in, first be offset on clearance wall 307 first area, both sides 200a and form respectively germanium silicon layer 411a, 411b, described germanium silicon layer 411a fills up described groove 409.
In the present embodiment, forming germanium silicon layer 411a and 411b method is epitaxial growth technology, and it is well known to those skilled in the art, does not repeat them here.
With reference to figure 5, form the second photoresist layer 206 of the second stop-layer 405, the second skew clearance wall 407 and germanium silicon layer 411a in coverage diagram 4.
In the present embodiment, the formation technique of described the second photoresist layer 206 please refer to the formation technique of the first photoresist layer 204, does not repeat them here.
With reference to figure 6, taking described the second photoresist layer 206 as mask, remove the germanium silicon layer 411b being arranged on Fig. 5 the first skew clearance wall 307 first area, both sides 200a.
In the present embodiment, the method for removing germanium silicon layer 411b is dry etching, as anisotropic dry etch process.
With reference to figure 7, remove the second photoresist layer 206 described in Fig. 6.
In the present embodiment, the method for removing the second photoresist layer 206 please refer to the method for removing the first photoresist layer 204, does not repeat them here.
With reference to figure 8, in Fig. 7, on the germanium silicon layer 411a of the first area 200a of the first skew clearance wall 307 both sides and the second skew clearance wall 407 both sides, form silicon layer 208.
In the present embodiment, the method that forms silicon layer 208 is epitaxial growth technology, and the thickness of described silicon layer 208 is 100nm ~ 300nm.It should be noted that, after silicon layer 208 forms in Fig. 8, also comprise that formation covers respectively the first side wall and the second side wall (not shown) of the first side wall clearance wall and the second sidewall spacers sidewall; And silicon layer 208 to the first side wall both sides and the first area 200a of silicon layer 208 belows carry out the doping of N-type heavily doped region, the germanium silicon layer 411a of the silicon layer 208 to the second side wall both sides and silicon layer 208 belows carries out the doping of P type heavily doped region, forms respectively the transistorized heavily doped region of nmos pass transistor and PMOS (not shown).
The formation technique of above-mentioned the first side wall, the second side wall and nmos pass transistor and the transistorized heavily doped region of PMOS is well known to those skilled in the art, and does not repeat them here.
Due to the existence of silicon layer 208, make the degree of depth of formed nmos pass transistor and the transistorized heavily doped region of PMOS less, avoid after the transistorized feature size downsizing of nmos pass transistor and PMOS, cross and deeply produce short-channel effect because of its heavily doped region, and avoid nmos pass transistor and PMOS transistor to produce electric leakage, improve the nmos pass transistor and the transistorized reliability of PMOS that form.
In other embodiments, after in Fig. 8, silicon layer 208 forms, also can comprise and remove successively the first stop-layer 305, first grid 303 and first grid medium 301, on the first area 200a between the first skew clearance wall 307, form the grid structure that comprises high K medium layer and metal gates; And remove successively the second stop-layer 405, second grid 403 and second gate medium 401, on the second area 200b between the second skew clearance wall 407, form the grid structure that comprises high K medium layer and metal gates.Its concrete technology, as those skilled in the art's known technology, is not described further at this.
In above embodiment, in formation CMOS transistor process, omit the step at first grid structure and the formation of second grid body structure surface and etching removal hard mask layer, reduce to form the etching technics quantity in CMOS transistor process, in simplifying CMOS transistor formation technique, can effectively avoid etching technics to cause damage to first grid structure and second grid body structure surface, improve the transistorized performance of formation CMOS and rate of finished products.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and amendment to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (12)
1. the transistorized formation method of CMOS, is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises first area and second area;
On described first area, form first grid structure, and form second grid structure on described second area;
Form the first photoresist layer that covers first grid structure and first area, first grid structure both sides;
Taking the first photoresist layer and second grid structure as mask, in the second area of second grid structure both sides, form groove;
Remove described the first photoresist layer;
In described groove and on first area, first grid structure both sides, form germanium silicon layer, described germanium silicon layer fills up described groove;
Form the second photoresist layer that covers second grid structure and second grid structure both sides second area;
Taking described the second photoresist layer as mask, remove the germanium silicon layer being positioned on first area, first grid structure both sides;
Remove described the second photoresist layer;
On the first area of described first grid structure both sides and the germanium silicon layer of second grid structure both sides, form silicon layer.
2. the transistorized formation method of CMOS as claimed in claim 1, is characterized in that, described groove is Sigma's shape.
3. the transistorized formation method of CMOS as claimed in claim 1 or 2, is characterized in that, the method that forms germanium silicon layer is epitaxial growth technology.
4. the transistorized formation method of CMOS as claimed in claim 1, is characterized in that, the method that forms silicon layer is epitaxial growth technology.
5. the transistorized formation method of CMOS as claimed in claim 1, is characterized in that, the thickness of described silicon layer is 100nm ~ 300nm.
6. the transistorized formation method of CMOS as claimed in claim 1, is characterized in that, the method that removal is positioned at the germanium silicon layer on first area, first grid structure both sides is anisotropic dry etch.
7. the transistorized formation method of CMOS as claimed in claim 1, is characterized in that, removes described the first photoresist layer or/and the method for the second photoresist layer is cineration technics.
8. the transistorized formation method of CMOS as claimed in claim 1, is characterized in that, described first grid structure comprises the first grid dielectric layer being positioned on first area and is positioned at the first grid on first grid dielectric layer; Described second grid structure comprises the second gate dielectric layer being positioned on second area and is positioned at the second grid on second gate dielectric layer.
9. the transistorized formation method of CMOS as claimed in claim 8, is characterized in that, after described first grid forms, also comprises: on first grid, form the first stop-layer; After described second grid forms, also comprise: on second grid, form the second stop-layer.
10. the transistorized formation method of CMOS as claimed in claim 9, is characterized in that, described the first stop-layer is or/and the material of the second stop-layer is silicon nitride.
The transistorized formation method of 11. CMOS as claimed in claim 8, is characterized in that, after forming first grid structure, also comprises: on first area, described first grid structure both sides, form the first skew clearance wall; After forming second grid structure, also comprise: on the second area of described second grid structure both sides, form the second skew clearance wall.
The transistorized formation method of 12. CMOS as claimed in claim 1, it is characterized in that, on described first area, form first grid structure, and form second grid structure on described second area before, also comprise: between described first area and second area, form fleet plough groove isolation structure.
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| CN1156902A (en) * | 1995-10-31 | 1997-08-13 | 日本电气株式会社 | Method for fabricating semiconductor device having CMOS structure |
| CN1830092A (en) * | 2003-08-04 | 2006-09-06 | 国际商业机器公司 | Structure and method of making strained semiconductor CMOS transistors |
| US20090246922A1 (en) * | 2008-03-27 | 2009-10-01 | Meng-Yi Wu | Method of forming cmos transistor |
| US20110201164A1 (en) * | 2010-02-12 | 2011-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of Dual EPI Process For Semiconductor Device |
| CN102810482A (en) * | 2011-06-02 | 2012-12-05 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing semiconductor devices |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1156902A (en) * | 1995-10-31 | 1997-08-13 | 日本电气株式会社 | Method for fabricating semiconductor device having CMOS structure |
| CN1830092A (en) * | 2003-08-04 | 2006-09-06 | 国际商业机器公司 | Structure and method of making strained semiconductor CMOS transistors |
| US20090246922A1 (en) * | 2008-03-27 | 2009-10-01 | Meng-Yi Wu | Method of forming cmos transistor |
| US20110201164A1 (en) * | 2010-02-12 | 2011-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of Dual EPI Process For Semiconductor Device |
| CN102810482A (en) * | 2011-06-02 | 2012-12-05 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing semiconductor devices |
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