TW417174B - Plasma processing method - Google Patents

Plasma processing method Download PDF

Info

Publication number
TW417174B
TW417174B TW088111111A TW88111111A TW417174B TW 417174 B TW417174 B TW 417174B TW 088111111 A TW088111111 A TW 088111111A TW 88111111 A TW88111111 A TW 88111111A TW 417174 B TW417174 B TW 417174B
Authority
TW
Taiwan
Prior art keywords
plasma
magnetic field
vacuum container
substrate
film
Prior art date
Application number
TW088111111A
Other languages
English (en)
Inventor
Hideaki Amano
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Application granted granted Critical
Publication of TW417174B publication Critical patent/TW417174B/zh

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/511Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using microwave discharges
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40Oxides
    • C23C16/401Oxides containing silicon
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40Oxides
    • C23C16/401Oxides containing silicon
    • C23C16/402Silicon dioxide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32192Microwave generated discharge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/3266Magnetic control means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H01L21/0212Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312Organic layers, e.g. photoresist
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312Organic layers, e.g. photoresist
    • H01L21/3127Layers comprising fluoro (hydro)carbon compounds, e.g. polytetrafluoroethylene
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31629Deposition of halogen doped silicon oxide, e.g. fluorine doped silicon oxide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/318Inorganic layers composed of nitrides
    • H01L21/3185Inorganic layers composed of nitrides of siliconnitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Analytical Chemistry (AREA)
  • Plasma Technology (AREA)
  • Drying Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)
  • ing And Chemical Polishing (AREA)

Description

A7 B7 五、發明說明(1 ) 技術領域 本發明,係關於一種例如藉ECR(Electr〇n Cycl〇tr〇n ReSonance :電子回旋加速器諧振)處理等之電漿處理對 於半導體晶圓等之被處理基板進行Si〇2膜或含氟碳膜等 薄獏之形成和蝕刻等之電漿處理方法。 技術背景 為了謀求半導體裝置之高積體化,而開發有圖案之微 細化、電路之多層化等之辦法;其中之一者即有把配線多 層化之技術。為了採取多層配線構造,而用導電層來連接 第η層之配線層與第(n+1)層之配線層間同時,在導電層以 外之區域則形成叫做層間絕緣膜之薄膜。此層間絕緣膜之 代表性薄膜者有Si〇2膜和SiOF膜;這些薄膜,係如第11圖 所示,使用一種用來進行ECr電漿處理之電漿處理裝置來 形成者。 例如此裝置,係透過波導管丨丨將例如2 45GHz之微波 供給電漿生成室1A内同時,外加例如875高斯(gauss)之磁 場,在微波與磁場之互相作用(電子回旋加速器諧振)下, 將Ar氣體或A氣體之電漿氣體、和導入於成膜室汨内之 例如SiH4氣體等之成膜氣體加以電漿化,藉此將薄膜形成 於載置在載置台上之半導體晶圓W者。 前述磁場’係在設置成圍繞著電漿室之主電磁線 圈13、與設在成膜室1B下方側之辅助電漿線圈14之組合 下,被外加成從電漿室1A至成膜室⑺之整個部分形成朝 下之磁場。而且’為了使膜質之均勻性提高,而調整主電 本紙張尺度適用#國國家標準(CNS)A4規格(210 X 297公釐) -----------t--------訂---------_ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 A7 ’ ______B7 ' __—
五、發明說明(2 ) 磁線圈13及輔助電磁線圈14之位置和電流以便晶圓面上之 磁通密度成為大致均勻,使之產生均勻之電漿。 --------------裝--- (請先閱讀背面之注意事項再填寫本頁) 且說,實際之工程乃是,將晶圓…載置於載置台12之 後,進行稱做預熱”之處理。此預熱就是,如將常溫之 晶圓W載置於載置台12之後立即導入成膜氣體來進行成膜 處理時,雖藉電漿來加熱晶圓貿,但溫度卻沒上升至成膜 時所設定之給定溫度,因而以低於預定之溫度進行成膜, ) 以致形成不良膜質之薄膜,要言之,為防止此等事之產生 而進行之處理者。 具體s之’將晶圓W載置於載置台12上之後,在導入 成膜氣體之前使電漿產生,藉該電漿把晶圓w加熱至給定 /凰度(例如成膜溫度),接著導入成膜氣體以進行成膜處理 。此時,在不改變微波和磁場之參數下,產生咸認為最適 於成膜之電漿,進行預熱及成膜之處理, 然而,上述之方法,卻配合成膜而使晶圓之附近產生 -線· 絡濟部智慧財產局員工消費合作社印製 ) 均勻之電漿,為此,磁通密度成為被擴大之狀態,每單位 面之熱量輸入量雖變成均勻,但熱量輸入量之總量卻變少 。因此,從預熱方面觀之時,花費之時間過長,即使載置 晶圓W之後立刻使電漿產生’例如為了使8〇。匚之晶圓…上 升至成膜處理之溫度即4〇〇。(:,也需要大約6〇秒,因而存 在著總生產量會降低等問題。 發明之揭露 本發明係在這種情況下創作者,其目的係在於提供一 種可縮短預熱時間之電漿處理方法;另一目的係在於提供 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) A7 4t71T4 --------B7 --Ξ---—--- 五、發明說明(3 ) 一種將多數種之薄膜予以成膜時’可使各膜之膜質之均勻 性提高的電聚處理方法·,更另-目的則在於提供一種進行 蝕刻氣體之餘渣之除去和抗蝕劑膜之除去等之後處理時, 可縮短其後處理所需之時間的電漿處理方法。更且又在於 提供一種進行用來除去基板表面所形成之自然氧化膜等之 前處理時,可縮短其前處理所需之時間的電漿處理方法。 因此,本發明提供一種電漿處理方法,其係藉由高頻 產生機構將微波供給真空容器内同時’藉由磁場形成機構 將磁%形成於則述真空容器内’進而於前述真空容器内藉 微波與磁場之電子回旋加速器諧振使電漿產生’藉該電漿 來處理被處理基板之方法者;其特徵在於:包含有 第一工程一將被處理基板搬入前述真空容器内,使電 漿產生藉此來加熱被處理基板;及 第二工程—接著,於前述真空容器内,使成膜氣體電. 漿化,藉由此電漿將薄膜形成於被處理基板上;其中, 在前述第一工程與前述第二工程間改變磁場形成機構 之電流使磁場形狀變化’俾使前述第一工程之電漿產生時 之被處理基板上之磁通密度大於前述第二工程之電漿產生 時之被處理基板上之磁通密度。 又,本發明之特徵有:包含有 第一成膜工程一於前述真空容器内使第一成膜氣體電 漿化,藉由此電漿將第一膜形成於被處理基板上,及 第二成膜工程一接著,於前述真空容器内使第二成膜 氣體電漿化,藉由此電漿將第二膜形成於前述第一膜上; 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) <請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------_ 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 A7 ~------5Z__ 五、發明說明(4) 其中, 在前述第一成瞑工程與第二成膜工程之間改變磁場形 成機構之電流,使磁場形狀變化。 再者,本發明之特徵為:包含有 蝕刻工程—於前述真空容器内使蝕刻氣體電漿化,藉 由此電漿蝕刻被處理基板,及 後處理工程一接著,於前述真空容器内,使後處理用 } 之氣體電漿化,藉由此電漿來進行後處理;其中, 在前述蝕刻工程與後處理工程間改變磁場形成機構之 電流使磁場形狀變化,俾使前述後處理工程之電漿產生時 之被處理基板上之磁通密度大於前述姓刻工程之電衆產生 時之被處理基板上之磁通密度。在此,前述後處理中,包 含有用來除去蝕刻氣體之餘渣的處理、及藉氧氣體來研磨 加工抗敍劑膜之處理。 又本發明之特徵為:包含有 > 蝕刻工程--於真空容器内使蝕刻氣體電漿化,藉由此 電漿#刻被處理基板表面之自然氧化膜,及 成膜工程·_接著,於前述真空容器内,使成膜氣體電 漿化,藉由此電漿將薄膜形成於被處理基板之表面;其中 在前述蝕刻工程與成膜工程間改變磁場形成機構之電 流使磁場形狀變化,俾使前述蝕刻工程之電漿產生時之被 處理基板上之磁通密度大於成膜工程之電漿產生時之被處 理基板上之磁通密度。 又,本發明提供一種電漿處理方法,其係藉由高頻產 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
I I----袭 i . (請先閲讀背面之注意事項再填寫本頁) 訂·- --線- 五、發明說明(5) 生機構將微波供給真空容器内同時,藉由磁場形成機構將 磁場形成於前述真空容器内’進而於前述真空容器内藉微 波與磁場之電子回旋加速器譜振使電漿產生,藉該電衆來 處理被處理基板之方法者;其特徵在於:包含有 第一蝕刻工程·-於前述真空容器内使蝕刻氣體電漿化 ’藉由此電漿蝕刻被處理基板,及 第二蝕刻工程—繼前述第一蝕刻工程之後,進—步藉 電漿來蝕刻被處理基板;其中 在前述第一蝕刻工程與前述第二蝕刻工程間改變磁場 形成機構之電流使磁場形狀變化,俾使前述第二蝕刻工程 之對於被處理基板基板面之蝕刻各向同性高於第一蝕刻工 程之對於被處理基板基板面之蝕刻各向同性。前述第一蝕 刻工程之磁場形狀為米勒磁場之形狀;前述第二蝕刻工程 中之磁場形狀為發散磁場之形狀。 圖式之簡單說明 本紙張&度適用中國國'家標& (CN、S)A丨規格(m〇 X 297公餐)
A7 B7 ζά)( 0ί · 五、發明說明(6 ) 第,¾係用來說明本發明之更另一實施形態的斷面圖 'Ί,:: 第8圖係用來說明第7圖所示之實施形態的斷面圖。 第9圖係用來說明第7圖所示之實施形態的斷面圖。 第10圖為一縱斷斷面圖,係顯示用來實施本發明之電 漿處理裝置的另一侧。 第11圖係用來說明習知電漿處理裝置之斷面圖。 用以實施發明之最佳形態 首先,第1圖係顯示用於本發明實施形態的電漿處理 裝置之一例。此裝置具有例如由鋁等所形成之真空容器2 ;此真空容器2包含有:一位置在上方使電漿產生之筒形 第一真空室21 ;及一連通連結至下方且口徑大於第一真空 室21之筒形第二真空室22。又’將此真空容器2接地,使 其成為零電位。 此真空容器2之上端係形成開口,且設有一將微波穿 透於此部分之構件、例如由石英等之材料所形成之穿透窗 23,以用來維持真空容器2内之真空狀態。在此穿透窗23 之外側’設有一連接至高頻電源部24(作為用來產生例如 2.45GHz微波之高頻產生機構作用)之波導管25 ;其係例如 藉由TE模式,用波導管25來引導高頻電源部24所產生之 微波’或者用波導管25來變換由TE模式所引導之微波成 TM模式’以便可從穿透窗23導入於第一真空室21内。 在用來劃區第一真空室21之侧壁,設有例如沿其周方 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -I— I I ill — ί- · I I I I I I I 訂-1 — — 1111 (請先閲讀背面之注意事項再填寫本頁) 级 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 9 經濟部智慧財產局員工消費合作社印製 417174 A7 _ B7 五、發明說明(7) 向均衡地配置之氣體喷嘴31,同時,在氣體喷嘴31連接有 例如未圖示之電漿生成用氣體源,俾使Ar氣體或02等之 電漿生成用氣體均勻地得以供給第一真空室21内之上部。 又’在圊中’氣體噴嘴31係為了迴避圖式之繁雜化而只記 載置2支,但實際上設有其以上之噴嘴。 在前述第二真空室22内,設有一與前述第一真空室21 成對向的用做被處理基板之半導體晶圓(以下稱為「晶圓 _i )W之載置台4。此載置台4,係在表面部備有靜電夾盤41 ;在此靜電夹盤41之電極,連接有高頻電源部42,以便除 外加用來吸附晶圓之直流電流(未圊示)以外,更外加用來 引進離子於晶圓之偏壓。 一方面’在前述第二真空室22之上部,就是,與第一 真空室連通之部分,設有環形之成膜氣體供給部5;此成 膜氣體供給部5係構成為:從氣體供給管51供給例*siH4 氣體等之成膜氣體’將此氣體從内周面之氣趙孔52供給真 空容器内。 在用來劃區前述第一真空室21之側壁的外周,配置有 接近於該側壁外周之環形主電磁線圈26,同時,在第二真 空室22之下方側配置有例如環形之輔助電磁線圈27。又, 在第二真空室22之底部,例如在對稱於真空室22之中心轴 的二處之位置分別設有排氣管28。本實施形態,係由主電 磁線圈26及輔助電磁線圈27來構成磁場形成機構。 其次’藉第2圊來說明,使用上述裝置來形成由§丨〇2 膜所成之層間絕緣膜於晶圓W上時之一連工程。首先, 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -------— II--裝----II--訂----— II--β (請先閱讀背面之注意事項再填寫本頁) 10 A7 B7 反濟邹智慧財產局員工消費合作钍印製 五、發明說明(8) 開一設在真空容器2側壁(未圖示)之閘閥,藉由未圖示之 運送臂,從未圖示之貨物關閉室搬入例如在表面形成有鋁 配線之晶圓W後將之載置在載置台上,接著藉靜電夾盤來 靜電吸附’進行如第2(a)圖所示之預熱(第一工程 就是說:關閉閘閥以封閉内部之後,從排氣管28排出 内部氛圍氣抽空至給定之真空度,以維持真空容器2内成 給定處理壓之狀態’先從喷嘴3 1將Ar氣體以給定之流量 導入於第一真空室21内。然後,從高頻電源部24供給 2.45GHz、2.8kW之高頻(微波),且藉高頻電源部42將 13.56MHz、OKW之偏壓外加於載置台4。又,載置台4之 表面溫度’例如’經常設定在80°C之溫度》其所以將偏壓 設定於OKW,是基於為了減少因不均一之規格而造成之 裝置之損傷;但損傷不大之裝置之成膜時,外加3〇〇W左 右之微細偏壓,以進行更高速度之預熱也可。 像這樣進行的話,來自高頻電源部24之微波則通過波 導管25而到達真空容器2之天花部,穿透該穿透窗23而被 導入於第一真空室21内。又,在真空容器2内,將主電磁 線圈26及輔助電磁線圈27之電流分別設定為220A、250A ,從第一真空室21之上部往向第二真空室22之下部,例如 在第一真空室21之下部附近形成875高斯之磁場。 如此在磁場與微波之互相作用下誘導E(電場)χ Η(磁 場)而產生電子回旋加速器諸振;在此諸振下將Ar氣體電 漿化,且加以高密度化。又,像這樣使Ar氣體之電漿產 生,藉此使電漿穩定化。如此產生之電漿流便從第一真空 本紙張义度適闬中國國家標並(CNSJA.l規格(210 X 2y'r公餐) 11 -------I-----裝--------訂·--— II---線 (請先閱讀背面之注意事項再填寫本頁) f' i t ~ ^ ' A7 ___B7 五、發明說明(9 ) 室21流進第二真空室22内’藉該電漿流來加熱晶圓We如 此使電漿產生20秒直到晶園W成為大約400°C之溫度為止 ,然後進行預熱。 接著如第2(b)圊所示,進行8丨02膜之成膜(第二工程) 。就是說:以給定之流量導入Ar氣體及〇2氣趙於第一真 空室21内同時,從成膜氣體供給部5導入siH4氣餿於第二 真空室22内。然後將真空容器内設定為給定之處理壓後外 加 13.56MHz、2.7kW之偏壓。 一方面,將2.45GHz、1.8kW之微波導入於第一真空 室21内同時,將主電磁線圈26及輔助電磁線圈27之電流分 別設定為200A,120A,在電子回旋加速器諧振下,將SiH4 氣體活性化(電漿化)以形成活性種(電漿)。於是,電衆離 子被偏壓引入晶圓W中,藉此削去晶圓表面之圊案(凹部) 的拐角而擴寬開口,如此形成由Si〇2膜所成之層間絕緣膜 〇 這種實施形態,由於在預熱時及成膜時改變主電磁線 圈26及輔助電磁線圈27之電流,藉此使磁場之形狀變化, 產生適於各處理之電漿,所以可縮短預熱之時間。 就是說:預熱時’比均勻性更重視對於晶圓W之熱量 輸入量’以便形成熱量輸入量較多之磁場;成膜時,則比 熱量輸入量更重視均勻性,以便形成面内均勻性較高之磁 場。在此’雖像上述那樣藉主電磁線圈26及輔助電磁線圈 27來形成磁場,但主電磁線圈26之磁場卻為越往下側越向 外側擴大之形狀,辅助電磁線圈27之磁場則為越往上側越 本紙張&度:¾用中國國家標达(C‘NS)AJ規格(21〇 X 297公餐) (請先閱讀背面之注意事項再填寫本頁) · I I I I I I I 訂·1!11- 經濟部智慧財產局員工消費合作社印製 12 經濟部令慧財產局員工消費合作社印製 A7 ___________Β7____ 五、發明說明(ι〇) 向外側擴大之形狀,使得藉輔助電磁線圈27向主電磁線圈 26之外側擴大之磁場變成向内側縮小之狀態。又,電衆雖 像上述那樣藉電場與磁場之互相作用來產生,但其形狀態 卻依存於磁場之形狀。 因此,例如成膜時由於將主電磁線圈26設定為20〇a ’將輔助電磁線圈27設定為120A ’所以由輔助電磁線圈27 ) 所縮小之量並不多,就結果而言外侧之磁場成為被擴大某 程度之狀態。藉此,一如第2(b)圖所示,使磁場b之磁力 線在晶圓W之面内成為大致均勻,但磁通密度卻變小。在 此所產生之電漿的電漿密度(對於晶圓…之熱量輸入強度) 由於與磁通密度成比例,而使得電漿密度在晶圓W之面内 成為大致均勻,然而熱量輪入量之總量卻變小(請參照第3 圖)》 一方面,預熱時’由於將主電磁線圈26設定為22〇A ’並將輔助電磁線圈27設定為250A,所以由輔助電磁線 ) 圈27所縮小之量變多,就結果而言磁場B變成將磁力線集 中於晶圓中心部附近之狀態。此時,磁通密度則在晶圓中 心部附近變大,因此,如第3圖所示,所產生之電聚之熱 量輸入強度雖然在晶圓面内並不均勻,但熱量輸入量之總 量卻變成比成膜時大的多。 像這樣,依照此方法,由於藉著控制主電磁線圈26及 輔助電磁線圈27之電流量,而預熱時形成—種對於晶圓w 之熱量輸入量變多之磁場,成膜時則形成面内均勻性較高 之磁場,所以例如待搬入常溫之晶圓评於真空容器2内之 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ---11--------------11 訂--— — — — — — (請先閱讀背面之注意事項再填寫本頁) 13 * 417174 A7 B7 五、發明說明(11) ,使之載置、吸附於載置台4,因而可將預熱時間(即,將 在此時間點溫度上升至80°C左右之晶圓W,加熱至成膜溫 度即400 C左右之時間)設定為20秒左右,且,可將預熱時 間縮短至習知之1/3左右。 其次’藉第4圖來說明本發明之另一實施形態。此實 施形態係將本發明方法適用於層合形成數種膜之場合者。 由本實施形態所形成之膜的構造之一例,例如有:將含氟 碳膜63(以下稱為「CF膜」)形成於由Si02所成之基板的上 面而成者;SiN膜62即介於Si02膜61與CF膜63之間,以作 為密合層作用。 如就該層合構造之膜之製造方法說明的話,首先例如 於上述電漿處理裝置,進行將第一膜即SiN膜62成膜於Si02 膜61上之第一成膜工程。也就是說:分別以給定之流量導 入電漿生成用氣艘例如Ar氣體、第一成膜氣艘例如石夕烧 氣體及Nz氣體;在給定之處理壓下,導入13.56MHz之偏 壓及2.45GHz之微波同時,將主電磁線圈26之電流設定為 200A,並把輔助電磁線圈27之電流設定為小於主電磁線 圈26之值(包含〇在内)例如50A,在電子回旋加速器諧振下 使上述氣體電漿化後,將大約5〇A(angstrom)之SiN膜62 形成在Si02膜61之上面。 其次,進行將第二膜即CF膜63成膜於SiN膜62上之第 二成膜工程》也就是說:於上述之電漿處理裝置,使用Ar 氣體作為電漿生成用氣體,使用C4F8氣體及C2H4氣體作為 第二成膜氣體,同時,將主電磁線圈26及輔助電磁線圈27 本紙張&度適用t國國家標準(CNS)A.l規格(210 X 297公S ) (請先閱讀背面之注意事項再填寫本頁) · -----—訂---I-----^ 經濟部智慧財產局員工消費合作社印製 14 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(12) 之電流分別設定為200A,160A,在前述電子回旋加速器 错振下使c4F8請及㈣氣體„化後,在siN麟之上 面形成厚度大約8000人之CF膜63。 依照這種實施形態,由於在SiN㈣之成膜時及咖 63之成膜時改變主電磁線圈26及辅助電磁線圈以電流藉 以改變磁場之形狀,使適於各處理之電浆產生,所以可提 高各膜之面内均勻性。 丨 就是說:若要形成SiN層62時,將輔助電磁線圈27之 電流值設定得相當小於主電磁線圈26,所以㈣助電⑽ 圈27所縮小之量極少,而如第4(a)圖所示,磁場b便成為 愈往下侧愈接近向外側擴大之發散磁場。由於這種磁場會 使成膜速度變小,所以即使為只5〇A之極薄的siN層62之 成膜,也可調整成膜量,可形成膜質均勻的薄膜。 方面,在CF膜63之成膜時,由於把輔助電磁線圈27 之電流值增大,使由輔助電磁線圈27所縮小之量增加,所 ) 以磁場B雖如第4(b)圖所示愈往下側愈鼓起,但繼續往下 側時卻成為愈往下侧愈縮小之形狀而形成米勒磁場。這種 磁場雖會使成膜,度變大,但由於(:1?膜63具有 比 SiN 62 較厚之8000A之膜厚,所以儘管成膜速度變大也可調整成 膜量,因而可用大速度來形成膜質均勻的薄獏。 接著’藉第5圖來說明本發明之更另一實施形態。此 實施形態係將本發明適用於蝕刻者。如就此實施形態之蝕 刻之一例說明的話’例如有〔於由si〇2膜所成之基板71之 上面形成链層鋁(A1)層72,然後在該A1層72之上面形成 本纸張义度遺用中國國家標準(CNSM.丨規格(210 X 297公餐) 15 ^-----------------線 (請先閱讀背面之注意事項再填寫本頁) :4 A7 B7 五、發明說明(13) 由抗蝕劑層73所成之圖案,用蝕刻氣體例如ci2氣體來蝕 刻A1層72等之例者。 如就這種蝕刻具體地說明的話,首先如第5(a)圖所示 ,於上述電漿處理裝置,進行用Cl2氣體來蝕刻A1層72之 工程。就是說:分別以給定之流量導入電漿生成用氣體例 如Ar氣體及Cl2氣體;在給定之處理壓下,導入13 56MHz 之偏壓及2.45GHz之微波同時,將主電磁線圈26及辅助電 磁線圈27之電流分別設定為200A,100A,在處理壓〇.5Pa 下’藉電子回旋加速器諧振使Cl2氣體電漿化後,藉電漿 來進行A1層72之钮刻。就是’ 一面藉由偏壓將電漿離引入 A1層72中,一面削去表面之圖案(凹部)的拐角以擴寬開口 ,進行濺射蝕刻》 此後如第5(b)圊所示’進行藉後處理用氣體來除去殘 留在溝部74(藉蚀刻來形成)之餘渣75的後處理工程《就是 說:分別以給定之流量導入電漿生成用氣體例如Ar氣體 及後處理用氣體即ΝΗ3(氨)氣體;將主電磁線圈%及輔助 電磁線圈27之電流分別設定為220Α,250Α,在處理壓133Pa 下’藉電子回旋加速器諧振使NH3氣體電漿化,藉此把餘 逢75即C〖(氣)還原及熱蒸發以便加以除去。 依照這種實施形態’由於在A1層72之蝕刻時與後處理 時之間改變主電磁線圈26及輔助電磁線圈27之電流,藉此 改變磁場之形狀’使適於各處理之電裝產生,所以可進行 均勻之蚀刻同時’可縮短後處理所需要之時間。 就是說:由於蝕刻時,將主電磁線圈26及輔助電磁線 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) (請先閲讀背面之注意事項再填寫本頁)
-裝-----!1 訂·------—.V 經濟部智慧財產局員工消费合作社印製 16 A7 A7 五 經濟部智慧財產局員工消費合作社印製 發明說明(η) 圈27分別設定為2〇〇Α,120Α,所以一如上述實施形態之 說明,磁場Β係如第5(a)圖所示,成為磁力線在基板71之 面内大致均勻之米勒磁場。這種磁場之電漿密度由於在基 板71之面内大致成為岣勻,所以可進行均勻之蝕刻。 一方面在後處理時,由於將主電磁線圈26及輔助電磁 線圈27分別設定為220Α,250Α,所以磁場Β係如第5(b)圖 所示’成為磁力線集中在基板71之中心部附近之米勒磁場 。這種磁場之電漿密度雖較之姓刻時相當大,但電漿密度 變大k活性種也變多’所以易於進行餘渣之除去處理,可 縮短後處理所需要之時間。 接著,藉第6圖來說明將本發明適用於蝕刻之例的其 他例。如就此實施形態之蝕刻之一例說明的話,例如有: 於由多晶矽所成之基板81之上面形成8丨02膜82,然後在該 Si〇2膜82之上面形成抗蝕劑層83,用蝕刻氣體例如C4F8氣 體之C(碳)與F(氟)之化合物氣體(以下稱為「CF系氣體」) 來蝕刻8丨02膜82等之例者。 如就這種蝕刻具體地說明的話,首先如第6(a)圖所示 ’於上述電漿處理裝置,進行用C4F8氣體來蝕刻3丨02膜82 之蝕刻工程。就是說:分別以給定之流量導入電漿生成用 氣體例如Ar氣體及C4F8氣體;在給定之處理壓〇.8Pa下, 導入13.56MHz之偏壓及2.45GHz之微波同時,將主電磁線 圈26及輔助電磁線圈27之電流分別設定為200A,120A, 在電子回旋加速器諧振下使C4F8氣體電漿化後,藉電漿來 進行5丨02膜82之蝕刻》 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) — — — — — — — — - In —--—ti-----I (請先閲讀背面之注意事項再填寫本頁) 17 經濟部智慧財產局員工消費合作社印製 417174 A7 _ B7 五、發明說明(15 ) 此後如第6(b)圖所示,進行用02氣體來研磨抗蝕劑膜 83之後處理工程。就是說:分別以給定之流量導入電漿生 成用氣體例如Ar氣體及後處理用氣體即02氣體;將主電 磁線圈26及辅助電磁線圈27之電流分別設定為220A,250A ’在處理壓、1.5Pa下,藉電子回旋加速器諧振使〇2氣體 電漿化;藉由此電漿使抗蝕劑膜83成為H2〇及C02之後加 以除去》 依照這種實施形態,由於在蝕刻時形成磁力線在基板 81面内大致成為均勻狀態之磁場,一方面在研磨時,則形 成一種磁力線集中於基板81之中心部附近的磁場,所以在 姓刻時在基板81之面内產生大致均勻之電衆,可進行均勻 的蝕刻之一方面’在研磨時可使電漿密度成為大於蝕刻時 ’因而可縮短研磨時間。 再者’本發明’例如欲在形成有p型和η型之矽膜的晶 圓表面形成例如多晶矽膜時,也可適用_首先蝕刻晶圓表 面(矽膜表面)所形成之自然氧化膜,接著形成多晶矽膜之 工程。此時,首先形成磁力線集中於中心部附近之磁場; 然後例如用CF系氣體來蝕刻矽膜表面之自然氧化膜;接 著,形成一在晶圓表面可獲得均勻的電漿密度之米勒磁場 後進行處理。此時,也可在短時間内進行所謂「自然氣化 膜去除」之前處理。 其次,用第7圖乃至第9圖來說明本發明之其他實施形 態。此實施形態,係藉著改變主電磁線圈26及輔助電磁線 圈27之電流而改變磁場之形狀,首先,藉由如第7(a)圓所
本紙張疋度適闲中國國家標車(CNS)A丨規格dO (請先閱讀背面之注意事項再填寫本頁) ----I — 1 I 訂·! !·λ 18 經 濟 部 智 慧 財 產 局 員 X 消 費 合 社 印 製 A7 B7 五、發明說明(16) 示之米勒磁場來進行第一㈣工程,其次藉由第7(b)圖所 示之發散磁場來進行第二姑刻工程者。 以下就蝕刻之一例說明的話,例如有:將si〇2膜82 形成於由多a曰石夕所成之基板81之上面,然後在該Si〇^82 之上面形成抗蝕劑膜83,藉蝕刻氣體例氣體等之以 碳)與F(氟)之化合物氣體(以下稱為「CF系氣體」)來蝕刻 8102膜82等之例者。 首先,於第一蝕刻工程,一如第7(a)圖所示,把輔助 電磁線圈27之電流值增大,以增加由辅助電磁線圈所縮小 之量;而磁場B雖愈往下愈鼓起,但繼續往下側時卻成為 愈在下侧愈縮小之形狀態而形成米勒磁場,在此磁場形狀 下進行蝕刻。在第7(a)圖所示之米勒磁場下,蝕刻之各向 異性則變大而在晶圓W之面向垂直方向形成姓刻特性,以 高縱橫比藉蝕刻來形成孔85 » 其次,在孔85被形成至某深度之階段,轉向第二蝕刻 工程。於第二姓刻工程,一如第7(b)圖所示,將輔助電磁 》 線圈27之電流值作成頗小於主電磁線圈26,使得由輔助電 磁線圈27所縮小之量極小,磁場B便成為愈往下侧愈向外 側擴大之近乎發散磁場之形狀。在此磁場形狀下進一步進 行蝕刻。在第7(b)圖所示之發散磁場下,蝕刻特性之各向 同性變高。結果,蝕刻作用向孔85之深度方向推進之同時 ,可在孔85之進口形成向外側擴展之推拔部85a。 接著,參照第8圖或第9圖,說明在孔85之進口附近形 成向外侧擴展之推拔部85a時之效果。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 19 --------I I I I I ---I----訂--— — — — — — — (請先閱讀背面之注意事項再填寫本頁) 4 4 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(17) 第8圊,係顯示在孔85中用A1來進行導線配線之工程 。用此A1來進行導線配線時,藉濺射向孔85供給A1之同時 ’將Si02膜82加熱至500°C乃至550°C。由濺射所供給之A1 之一部分則附著於Si02膜82之膜表面上成A1塊87。由於 Si〇2膜82被加熱至500°C乃至550°C,所以A1塊87便回流而 流進孔85中。此時,在孔85之進口附近形成有向外側擴展 之推拔部85a,所以如箭形符號所示,可使A1塊87向孔85 有效地回流。 接著’參照第9圖,說明在孔85之進口附近形成向外 側擴展之推拔部85a時之其他效果。 第9圚,係顯示在孔85中用Cu來進行導線配線之工程 。將Cu之鍍液89導入孔85中,進行借助Cu之導線配線。 此時,由於在孔85之進口附近形成有向外側擴展之推拔部 85a,所以用來導入Cu鍍液89之導入寬度變寬,可將Cu鍍 液89輕易地供給孔85中。藉此,可藉低於A1之低電阻的Cu ,在CF膜等之層間絕緣膜間進行導線配線。 上述實施本發明方法之電漿處理裝置,也可使用例如 如第10圊所示之主電磁線圈9 »此主電磁線圈9係分割成例 如三個,以便分別改變各電磁線圈91〜93之電流。又,依 照此例’氣體喷嘴94係被構成,通過第一真空室21及第二 真空室22之壁部,向第一真空室21内導入電漿生成用氣體 。其構成係與第1圊所示之電漿處理裝置相同。 如上述那樣改變磁場,係意味著藉改變處理空間之磁 場外形’來控制基板之電漿處理。而且,處理時間之磁場 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 20 •裝------— —訂--— II--IA . (請先閲讀背面之注意事項再填寫本頁) 發明說明(18) 外形之變更’係意味著對於基板面内之處理結果,使對於 中央之集中及向周邊之擴散等控制,成為可能。 又’若除了 Si02以外更形成SiOF膜和CF骐時,可適 用本發明。又’若要層合多數種之膜時,可適用於Si〇F 膜與Si〇2膜之組合等。再者’於A1層72之姓刻,在不添加 氣體下使電漿產生,藉由此電漿之熱來進行後處理也可; 此時也一樣’調整主電磁線圈26及輔助電磁線圈之電流值 ’俾使對於基板之電漿之熱量輸入量變大。 再者,本發明並不一定藉ECR來生成電漿,例如,藉 由從捲在園頂形容器之線圈將電場及磁場給與處理氣體之 方法等來生成電漿時也可適用本發明。此方法係叫做 ICPdnductive Coupled Plasma)。又,在與藉由叫做螺旋 (helicon)波電漿的例如13_56MHZ2螺旋波及磁線圈來外 加之磁場之互相作用下生成電漿時,在外加磁場成大致平 行於叫做磁控管電漿的二張平行陰極藉以生成電漿時、及 將高頻電力外加於叫做平行平板等之互相對向的電極間藉 以生成電漿時’也可適用本發明。 如依本發明,則可提供_種變更磁場之外形,藉此可 進行適於二工程之各個的電裝處理之方。 417174 A7 B7 五、發明說明(19) 2···真空容器 4…載置
9,26…主電磁線圈 21... 第一真空室 22··· 第二真空室 23··· 穿透窗 24··· 高頻電源部 25··· 波導管 27··· 輔助電磁線圈 28··· 排氣管 31··· 氣體噴嘴 41." 靜電夾盤 42··· 高頻電源部 61, 82…Si〇W 元件標號對照 62-"SiN 膜 63…含氟碳膜(CF膜) 71,81…基板 72…A1膜 7 3,8 3…抗蚀劑層 74…溝部 75…餘渣 85···孔 85a…推拔部 87…A1塊 89…鑛液 94…氣體喷嘴 91〜93…電磁線圈 W…晶圓 ------------ ^--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 22 本紙張尸、度適用中國國家標準(CNS)A.1規格(210 X 297公g )

Claims (1)

  1. 申請專利範圍 1. 一種電漿處理方法,係藉由高頻產生機構將微波供給 真空容器内同時,藉由磁場形成機構將磁場形成於前 述真空容器内,進而於前述真空容器内藉微波與磁場 之電子回旋加速器諧振使電漿產生,藉該電漿來處理 被處理基板之方法者;其特徵在於:包含有 第一工程―將被處理基板搬入前述真空容器内, 使電衆產生’藉以加熱被處理基板,及 第二工程··接著,於前述真空容器内,使成膜氣 體電漿化,藉由此電漿將薄膜形成於被處理基板上; 其中, 在前述第一工程與前述第二工程間改變磁場形成 機構之電流使磁場形狀變化,俾使前述第一工程之電 漿產生時之被處理基板上之磁通密度大於前述第二妥 程之電漿產生時之被處理基板上之磁通密度。 2. —種電漿處理方法,係藉由高頻產生機構將微波供給 真空容器内同時,藉由磁場形成機構將磁場形成於前 述真空容器内,進而於前述真空容器内藉微波與磁場 之電子回旋加速器諧振使電漿產生,藉該電漿來處理 被處理基板之方法者;其特徵在於:包含有 第一成膜工程--於前述真空容器内使第一成膜氣 體電漿化,藉由此電漿將第一膜形成於被處理基板上 ,及 第一成膜工程一接著,於前述真空容器内使第二 成膜氣體電漿化,藉由此電漿將第二膜形成於前述第 六、申請專利範圍 一膜上;其中 在前述第一成膜工程與第二成膜工程之間改變磁 場形成機構之電流’使磁場形狀變化。 3. -種電漿處理方法,係藉由高頻產生機構將微波供給 真空容器㈣時’藉由磁場形成機構將磁場形成於前 述真空容器内’進而於前述真空容器内藉微波與磁場 之電子回旋加速器諧振使電漿產生,藉該電漿來處理 被處理基板之方法者;其特徵在於:包含有 敍刻工程--於真空容器内使姓刻氣體電漿化藉 由此電漿蝕刻被處理基板,及 後處理工程一接著,於前述真空容器内,使後處 理用之氣體電漿化,藉由此電漿來進行後處理;其中 在前述蝕刻工程與後處理工程間改變磁場形成機 構之電流使磁場形狀變化,俾使前述後處理工程之電 漿產生時之被處理基板上之磁通密度大於前述蚀刻工 程之電漿產生時之被處理基板上之磁通密度。 經濟部智慧財產局員工消費合作社印製 4. 一種電漿處理方法,係藉由高頻產生機構將微波供給 真空容器内同時,藉由磁場形成機構將磁場形成於前 述真空容器内,進而於前述真空容器内藉微波與磁場 之電子回旋加速器諧振使電漿產生,藉該電漿來處理 被處理基板之方法者;其特徵在於:包含有 姓刻工程--於真空容器内使蝕刻氣體電漿化,藉 由此電襞蝕刻被處理基板,及 •本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 24 六、申請專利範圍 後處理工程--接著,於前述真空容器内,使後處 理用之氣體電漿化,藉由此電漿來除去蝕刻氣體之餘 渣;其中, 在前述蝕刻工程與後處理工程間改變磁場形成機 構之電流使磁場形狀變化,俾使前述後處理工程之電 漿產生時之被處理基板上之磁通密度大於前述蝕刻工 程之電流產生時之被處理基板上之磁通密度。 5· —種電漿處理方法,係藉由高頻產生機構將微波供給 真空容器内同時,藉由磁場形成機構將磁場形成於前 述真空容器内,進而於前述真空容器内藉微波與磁場 之電子回旋加速器諧振使電漿產生,藉該電漿來處理 被處理基板之方法者;其特徵在於:包含有 蚀刻工程―於前述真空容器内使蝕刻氣體電漿化 ’藉由此電漿蝕刻被處理基板,及 後處理工程--接著’於前述真空容器内使氧氣體 電漿化,藉由此氧電漿來研磨抗蝕劑膜;其中, 在前述蝕刻工程與後處理工程間改變磁場形成機 構之電流使磁場形狀變化,俾使前述後處理工程之電 漿產生時之被處理基板上之磁通密度大於前述蝕刻工 程之電流產生時之被處理基板上之磁通密度。 6·—種電漿處理方法,係藉由高頻產生機構將微波供給 真空容器内同時,藉由磁場形成機構將磁場形成於前 述真空容器,進而於前述真空容器内藉微波與磁場之 電子回旋加速器諧振使電漿產生,藉該電漿來處理被 經濟部智慧財產局員工消費合作社·印製 A8 cl __________ D8 六、申請專利範圍 處理基板之方法者;其特徵在於:包含有 蝕刻工程於前述真空容器内使蝕刻氣體電漿化 ,藉由此電漿蝕刻被處理基板表面之自然氧化膜,及 成膜工程—接著,於前述真空容器内,使成膜氣 體電浆化,藉由此電衆將薄膜形成於被處理基板之表 面;其中, 在前述蝕刻工程與成膜工程間改變磁場形成機構 之電流使磁場形狀變化,俾使前述蝕刻工程之電漿產 生時之被處理基板上之磁通密度大於成膜工程之電漿 產生時之被處理基板上之磁通密度。 7_ —種電漿處理方法,係藉由高頻產生機構將微波供給 真空容器内同時,藉由磁場形成機構將磁場形成於前 述真空容器内,進而於前述真空容器内藉微波與磁場 之電子回旋加速器諧振使電漿產生,藉該電漿來處理 被處理基板之方法者;其特徵在於:包含有 ) 第一姓刻工程一於前述真空容器内使蝕刻氣體電 漿化,藉由此電漿蝕刻被處理基板,及 第二蝕刻工程--繼前述第一蚀刻工程之後,進一 步藉電漿來蝕刻被處理基板;其中 在前述第一蝕刻工程與前述第二蝕刻工程間改變 磁場形成機構之電流使磁場形狀變化,俾使前述第二 蝕刻工程之對於被處理基板基板面之蝕刻各向同性高 於前述第一蝕刻工程之對於被處理基板面之蝕刻各向 同性。 本紙張尺度適用中國國家標準(CNS>A4規格(210 X 297公笼) 26 ---------------------^---------^ (請先閱讀背面之注意事項再填寫本頁) 六、申請專利範圍 8.如申請專利範圍第7項所述之電漿處理方法,其特徵在 於: 前述第一蝕刻工程中之磁場形狀為米勒磁場之形 狀; 前述第二蝕刻工程中之磁場形狀為發散磁場之形 狀。 ----------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 27 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
TW088111111A 1998-06-30 1999-06-30 Plasma processing method TW417174B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10201287A JP2000021871A (ja) 1998-06-30 1998-06-30 プラズマ処理方法

Publications (1)

Publication Number Publication Date
TW417174B true TW417174B (en) 2001-01-01

Family

ID=16438483

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088111111A TW417174B (en) 1998-06-30 1999-06-30 Plasma processing method

Country Status (6)

Country Link
US (1) US6392350B1 (zh)
EP (1) EP1100119A4 (zh)
JP (1) JP2000021871A (zh)
KR (1) KR100377582B1 (zh)
TW (1) TW417174B (zh)
WO (1) WO2000001007A1 (zh)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE1011576A3 (fr) 1997-11-27 1999-11-09 Solvay Produit a base d'epichlorhydrine et procede de fabrication de ce produit.
US8617351B2 (en) 2002-07-09 2013-12-31 Applied Materials, Inc. Plasma reactor with minimal D.C. coils for cusp, solenoid and mirror fields for plasma uniformity and device damage reduction
US8048806B2 (en) 2000-03-17 2011-11-01 Applied Materials, Inc. Methods to avoid unstable plasma states during a process transition
US6458722B1 (en) * 2000-10-25 2002-10-01 Applied Materials, Inc. Controlled method of silicon-rich oxide deposition using HDP-CVD
AU2002232395A1 (en) * 2000-11-03 2002-05-15 Tokyo Electron Limited Hall effect ion source at high current density
US6733957B2 (en) * 2000-12-27 2004-05-11 Victor Company Of Japan Disk substrate and manufacturing method therefor, and disk manufactured by the disk substrate
IL164685A0 (en) 2002-04-22 2005-12-18 Marcio Marc Aurelio Martins Ab Apparatus and method for measuring biologic parameters
AU2002325215A1 (en) * 2002-05-08 2003-11-11 Leonhard Kurz Gmbh And Co. Kg Method of decorating large plastic 3d objects
US20060233682A1 (en) * 2002-05-08 2006-10-19 Cherian Kuruvilla A Plasma-assisted engine exhaust treatment
US20060228497A1 (en) * 2002-05-08 2006-10-12 Satyendra Kumar Plasma-assisted coating
US7638727B2 (en) * 2002-05-08 2009-12-29 Btu International Inc. Plasma-assisted heat treatment
US7497922B2 (en) * 2002-05-08 2009-03-03 Btu International, Inc. Plasma-assisted gas production
US20050233091A1 (en) * 2002-05-08 2005-10-20 Devendra Kumar Plasma-assisted coating
KR20050025173A (ko) * 2002-05-08 2005-03-11 다나 코포레이션 플라즈마-보조된 엔진 배기 처리
US20060237398A1 (en) * 2002-05-08 2006-10-26 Dougherty Mike L Sr Plasma-assisted processing in a manufacturing line
US7445817B2 (en) * 2002-05-08 2008-11-04 Btu International Inc. Plasma-assisted formation of carbon structures
US20060057016A1 (en) * 2002-05-08 2006-03-16 Devendra Kumar Plasma-assisted sintering
TWI283899B (en) * 2002-07-09 2007-07-11 Applied Materials Inc Capacitively coupled plasma reactor with magnetic plasma control
US7189940B2 (en) * 2002-12-04 2007-03-13 Btu International Inc. Plasma-assisted melting
KR20040054091A (ko) * 2002-12-17 2004-06-25 아남반도체 주식회사 반도체 소자의 제조방법
KR100536797B1 (ko) * 2002-12-17 2005-12-14 동부아남반도체 주식회사 화학 기상 증착 장치
US20050205210A1 (en) * 2004-01-06 2005-09-22 Devine Daniel J Advanced multi-pressure workpiece processing
US7695590B2 (en) * 2004-03-26 2010-04-13 Applied Materials, Inc. Chemical vapor deposition plasma reactor having plural ion shower grids
US20050211546A1 (en) * 2004-03-26 2005-09-29 Applied Materials, Inc. Reactive sputter deposition plasma process using an ion shower grid
US20050211547A1 (en) * 2004-03-26 2005-09-29 Applied Materials, Inc. Reactive sputter deposition plasma reactor and process using plural ion shower grids
US20050211171A1 (en) * 2004-03-26 2005-09-29 Applied Materials, Inc. Chemical vapor deposition plasma reactor having an ion shower grid
WO2006127037A2 (en) * 2004-11-05 2006-11-30 Dana Corporation Atmospheric pressure processing using microwave-generated plasmas
KR100683416B1 (ko) 2004-11-25 2007-02-20 피에스케이 주식회사 플라즈마 챔버 시스템 및 이를 이용하여 저유전막을 갖는기판 상에 형성된 포토레지스트 패턴을 애싱하는 방법
US9157151B2 (en) 2006-06-05 2015-10-13 Applied Materials, Inc. Elimination of first wafer effect for PECVD films
KR100790779B1 (ko) 2006-06-09 2008-01-02 주식회사 아이피에스 갭 필 능력을 향상시킨 절연막 증착 방법
US20080060676A1 (en) * 2006-09-11 2008-03-13 Dana Scranton Workpiece processing with preheat
US8312384B2 (en) 2008-06-11 2012-11-13 Honeywell International Inc. Apparatus and method for fault-tolerant presentation of multiple graphical displays in a process control system
US20120160840A1 (en) 2010-12-23 2012-06-28 Eastman Chemical Company Wood heater with alternating microwave launch locations and enhanced heating cycles
KR101390900B1 (ko) * 2011-05-31 2014-04-30 세메스 주식회사 기판처리장치
DE102011111449B4 (de) 2011-08-30 2014-07-17 Carl Freudenberg Kg Klemmmverbindung zur Befestigung von plattenförmigen Bauelementen insbesondere von Solarmodulen
RU2682744C2 (ru) * 2016-12-02 2019-03-21 Открытое акционерное общество "Научно-исследовательский институт точного машиностроения" Устройство для вакуумно-плазменного осаждения материалов с ионной стимуляцией
JP6764383B2 (ja) * 2017-09-20 2020-09-30 株式会社日立ハイテク プラズマ処理装置
US10544499B1 (en) * 2018-08-13 2020-01-28 Valeo North America, Inc. Reflector for vehicle lighting
CN117070924B (zh) * 2023-08-30 2024-04-26 江苏艾匹克半导体设备有限公司 一种化学气相沉积气流调节装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2546405B2 (ja) * 1990-03-12 1996-10-23 富士電機株式会社 プラズマ処理装置ならびにその運転方法
JP2598336B2 (ja) * 1990-09-21 1997-04-09 株式会社日立製作所 プラズマ処理装置
US5198725A (en) * 1991-07-12 1993-03-30 Lam Research Corporation Method of producing flat ecr layer in microwave plasma device and apparatus therefor
JPH11162958A (ja) * 1997-09-16 1999-06-18 Tokyo Electron Ltd プラズマ処理装置及びその方法

Also Published As

Publication number Publication date
KR20010053278A (ko) 2001-06-25
JP2000021871A (ja) 2000-01-21
WO2000001007A1 (fr) 2000-01-06
KR100377582B1 (ko) 2003-03-29
EP1100119A4 (en) 2003-05-07
US6392350B1 (en) 2002-05-21
EP1100119A1 (en) 2001-05-16

Similar Documents

Publication Publication Date Title
TW417174B (en) Plasma processing method
TWI657499B (zh) 蝕刻方法
TWI686863B (zh) 蝕刻有機膜之方法
US7449414B2 (en) Method of treating a mask layer prior to performing an etching process
TWI716378B (zh) 蝕刻方法
TW201717276A (zh) 蝕刻方法
TWI722187B (zh) 蝕刻方法
JP5271267B2 (ja) エッチング処理を実行する前のマスク層処理方法
KR100894345B1 (ko) 플라즈마 에칭 방법 및 컴퓨터 판독 가능한 기억 매체
US20140273461A1 (en) Carbon film hardmask stress reduction by hydrogen ion implantation
JP5064319B2 (ja) プラズマエッチング方法、制御プログラム及びコンピュータ記憶媒体
TW201724252A (zh) 蝕刻方法
US20040058541A1 (en) Sample surface processing method
US9793136B2 (en) Plasma etching method
US6573190B1 (en) Dry etching device and dry etching method
JP2019186501A (ja) エッチングする方法及びプラズマ処理装置
WO2018084255A1 (ja) 被処理体を処理する方法
JP4577328B2 (ja) 半導体装置の製造方法
JP2001326217A (ja) プラズマ処理装置
TW425605B (en) Plasma film-forming method
JP3172340B2 (ja) プラズマ処理装置
KR20210035073A (ko) 플라즈마 처리 방법 및 플라즈마 처리 장치
TW200302694A (en) Etching method and etching device
US11201063B2 (en) Substrate processing method and substrate processing apparatus
WO2022059440A1 (ja) エッチング方法、プラズマ処理装置、及び基板処理システム

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees