TW407453B - Multiple layer printed circuit board and method for manufacturing the same - Google Patents

Abstract

An opening is made in a resin (20) with a laser to form a viahole. A copper foil (22) etched into a thin film (3 mu m) to lower the heat conductivity is used as a conformal mask, thereby making an opening (20a) in the resin (20) by fewer times of irradiation with a pulse laser beam. This prevents formation of any undercut in the resin (20) on which an interlayer resin-insulating layer is to be formed, enabling improvement in the connection reliability of the viahole.

Description

V. Description of the Invention (l) 407453 [Technical Field] Two aspects of the present invention relate to a multilayer printed wiring board and a method for manufacturing the same, and a method for forming an opening through a laser through the opening and forming a plating film on the opening. Via holes, solder resists, resist layer openings, and through-hole (core) substrates are formed. [Known technology] A conductor layer is formed on the surface of the resin insulation layer, and an opening is formed by etching in a part of the m, and then the + body layer is opened—a hole is made in the resin insulation layer.仃 Irradiation and ― jc ^ iformai standard sk) of the multilayer printed wiring board is disclosed in JP 9-1 300 38. However, in the above-mentioned technology, because the thick steel foil is used as the uniform covering cover, and the heat conduction of copper foil 2 is easy to dissipate heat, it must be large in pulse type, which is not tolerable. Therefore, the m rows of holes formed in the resin insulation layer are expanded in multiple directions to cause side erosion (undercut). It is easy to cause the holes to be formed on the holes with electrolytic copper plating and electroless copper plating. Layered holes, the electrolytic copper coating and electroless copper coating will be changed to β, which will reduce the reliability of the disconnection.卞 It is very easy to peel into a micro-pitch process to form an electrolytic steel electroplating film (0 · go further). Right based on the above technology is a fine pitch conductor circuit. However, after manufacturing copper electroplating film, it must be removed. No electricity under photoresist

Page 5 Γ: Description of the invention ⑵40 Li ^^-1 1 μιη) and copper foil (12 μιη ~ 18 μια), at this time, the width of the conductor circuit is too narrow to perform. Similarly, since a thick copper foil is used as the uniform cover, it is impossible to form a via hole having a fine pore diameter. That is, in the manufacturing process, it is difficult to reduce the diameter of the via hole because the electroless copper plating film (2am) and the copper foil (12 / zm ~ 18 ')' under the photoresist must be removed. 1. The present invention proposes a manufacturing method of a multilayer printed wiring board that does not cause side erosion even if the screen is covered evenly, in order to solve the above problems. On the other hand, as shown in JP 4-3 6 76, the method of "uniform covering, ~ curtain cover" is used to form a metal layer on the insulating resin layer, and then to form the 1ν hole forming part of the interlayer. The metal layer is removed by etching to provide an opening, and then laser light is irradiated on the opening portion to remove only the insulating resin layer exposed through the opening. According to this technique, since a plurality of openings for via holes can be provided in the insulating resin layer, the productivity is excellent. Once it is' according to the inventor's research, in the above-mentioned technology, resin will remain in the opening for mesopores, and when the cold and heat cycle is encountered, the residual resin will serve to press the mesopores and make them bulge. Causes so-called electrical insulation problems between the upper and lower layers. Furthermore, through research by the present inventors, it was found that the resin Λ 'and the bulge' at the edge of the opening caused the so-called open circuit problem in the via hole. The purpose of this book is to obtain a multilayer printed wiring board that can further increase the reliability of the connection of the via hole. The other side is bu 1 id up multilayer printed wiring board

5. Description of the invention (3). A multilayered technology using RCC (Resin Coated Copper: resin-coated copper box) has been proposed. In this technology, Rcc is laminated on a circuit board, and the steel foil is removed by a moment. Then, through-holes are set in the formation part of the via hole, and then the resin layer of the through-hole portion is irradiated with laser light to remove the resin. Layer to form an opening, and finally fill the opening with plating to form a via hole. Furthermore, as described in Japanese Patent Application Laid-Open No. 365 '51, a multi-layer technology has been developed in which a single-sided circuit substrate in which a conductive material is filled in a bayonet is laminated with an adhesive layer interposed therebetween. In the multilayer printed wiring board as described above, in order to ensure the tight adhesion between the surface of the underlying conductor circuit and the interlayer resin insulation layer, the surface of the underlying conductor circuit must be roughened. As a roughening method, for example, a method for m-body circuit surface = a needle-like or porous plating layer made of Cu-hp alloy to cover and roughen it (hereinafter referred to as Cu-Ni-P plating treatment method) : A method of roughening the surface of a circuit by performing a blackening (oxidation) -reduction treatment (known as a blackening-reduction treatment method); using a mixed aqueous solution of hydrogen peroxide-sulfuric acid for soft etching on the surface of a conductor circuit (S0ft is roughened by mail) (hereinafter referred to as soft etching method); and a method of roughening the circuit surface by rubbing with sandpaper or the like to generate a gap (hereinafter referred to as the scratch method) Wait. Broadcast .........% After the conductor circuit is roughened or blackened-reduced, the interlayer resin insulation layer is formed after the conductor circuit is roughened, and then the light is irradiated to form the interlayer resin insulation layer. After opening the vias

Page 7 4074S3 V. Description of the invention (4) The laser light is generated and formed because the laser light is absorbed. In addition, when the surface is roughened, the roughening is sufficiently tight between the roughened layers. The present invention The purpose is to provide a layered printed circuit board with excellent tightly formed interstitial f-holes and flattened. Therefore, interstitial holes (conductors on the other hand are penetrated through the insulating layer. Interlayer resins have been known to have a black round mask It is equivalent to the black circle. However, the upper minimum diameter penetrates through the multilayer printed wiring and the interlayer on the conductor is treated as described above. Therefore, the use of soft etching surface will not prostitute, so it will be productive; Solve a kind of multi-layer printing which is formed in the guide adhesion, and can form a lower circuit with the laser light). In the conventional technique, the through-hole, and then, the through-hole insulation layer, the photosensitive portion (mask), the limit of the lithography imaging hole is the high density of the board.

The roughened surface of the circuit disappeared and flattened, resulting in a problem of poor adhesion of the holes. The roughened surface formed is dyed, so a rough laser light is formed on the conductor circuit by the rubbing method or the rubbing method. However, the problem of so-called conductor circuit and interlayer resin insulation cannot be caused by the roughened surface. Those who solve the problems of the above-mentioned conventional techniques, such as a printed circuit board and a method for manufacturing the same, the interlayer resin insulation layer on the multibody circuit is provided with a roughened layer for forming a conductor circuit surface on the interlayer resin insulation layer. In the technique that the conductor circuit of the layer is not tight, the via hole is formed by disposing a metal film on the through hole between the interlayer resin and the photoresist. The description of the hole position makes the interlayer resin insulation layer photosensitive, and then dissolves it to form it. The method of (photolithography) has a diameter of 80 jtzm and cannot meet the requirements. Therefore, the inventors have obtained

Page 8 V. Description of the invention-13 The idea of using lasers to form through-holes. After conducting experiments, it is possible to form through-holes with a diameter of 80 μm or less. However, when the via hole is formed by a through hole having a thickness of 80 μm or less, the reliability of the via hole is found to be very low. After researching the reason, it was found that the problem was the close adhesion between the through hole and the electroless plated film. That is, the interlayer hole formed by precipitating the electroless plated film has a low adhesion using the laser κ small-aperture through hole and the electroless plated film. Therefore, the electroless plated film is peeled from the through hole And an open circuit occurred. On the other hand, since the conventional lithography imaging system uses exposure and development to perforate through holes, only the photosensitive material is used, and thus the performance that can meet the requirements of multilayer printed wiring boards cannot be obtained.

Moreover, in the multilayer printed wiring board of the conventional technology, the reliability of the solder bump C bump is also very low. After researching the reasons, it was found that the tight adhesion between the through hole and the metal film was found. That is, a solder bump formed by filling solder on a nickel plating film deposited on a conductor circuit under an opening has a low adhesion to the conductor circuit and the nickel plating film. The plating film is peeled off by the conductor circuit and the solder bump is broken.

The present invention is a person who can solve the above-mentioned problems, and an object of the present invention is to provide a multilayer printed wiring board capable of forming a highly reliable small-aperture interlayer hole and a method for manufacturing the same. A multilayer printed wiring board capable of forming highly reliable solder bumps and a method for manufacturing the same. On the other hand, the through-holes provided on the core substrate are required

Page 9 of the fifth invention description (6) " ------? C " Π η ^ ^ ^, ^ drilled copper-clad laminates by laser processing pretending to be ϊ: ϊ ϋ ΐ! Ί Light: In other words, carbon dioxide gas laser is the most suitable because it has low cost. However, since the carbonic acid laser is another laser, it is impossible to use laser processing directly on the copper plating layer to make it into a technical hole based on common sense. (The surface of the steel pig is blackened ... oxidized.) It was proposed that the technique of irradiation is described in JP-A S6b 9959959

{It is in this technology that the blackening treatment must be done at the beginning, which causes the problem of lengthening the process. As a result of intensive research by the present inventors, it was unexpectedly discovered that by reducing the thickness of copper 4, although the reflection on the surface still occurs, an opening can be formed in the copper foil.

The present invention is a person who can solve the above-mentioned problems, and its purpose is to propose a technology that can be directly perforated by laser on a steel-clad laminate, and a through-hole forming substrate and a multilayer printed wiring board obtained by the method. . ^ On the other hand, due to the recent demand for high-density multilayers, laminated multilayer printed wiring boards have attracted attention. This multilayer circuit board is formed by conducting conductor circuits and interlayer resin layers alternately on a die station substrate to form a 'conductor circuit of each layer' and then connecting via vias. As the core substrate of the multilayer wiring board as described above, a glass epoxy substrate of FR_4 grade conventionally used can be used.

Page 10 4〇74S. ^ V. Description of the invention (7) However, 'the FR-4 glass epoxy substrate was subjected to the rHAST test and the vapor test, etc.', the insulation resistance between the plated through holes decreased In the heat cycle test, the problem that the impedance value of the through hole chain of the electric money changes greatly is generated. That is, its reliability is low during long-term use. In order to solve the above problems, although a core substrate using a BT (bismaleimide triazine) resin (bismaleimide triazine) resin has been proposed ', the price is too high. The present inventors and others' when considering using a resin such as epoxy resin with a low price like an BT resin and using a resin such as epoxy resin with a low price: why would there be a gap between the through-holes: the insulation resistance value will be reduced and the connection between the through-holes When the impedance (j) value of the conductor circuit cannot be controlled, it is unexpectedly found that the cause of the above problem lies in the fact that the Tg point (glass transition temperature) of the purpose of the tree is at the end and the present invention is completed. The invention of the invention proposes a low price. The insulation resistance value between the interlayer holes does not decrease during the HAST test and the steam test. The resistance value of the conductor circuit between the through holes does not change during the thermal cycle test. Brush the circuit board. On the other hand, the method of manufacturing printed circuit boards can be roughly divided into the Subtractive Process. And the Additive Process.

Process). The subtractive method is also called an etching method, which is characterized by chemically corroding the copper-coated surface. Here, the method of using a subtractive layer method to brush a circuit board (two panels) is briefly explained. First, a steel-clad laminate composed of a steel foil having a thickness of several layers is attached to the rain surface of an insulating substrate. In this copper-plated laminate = predetermined two m set 40745 ^ V. Description of the invention (8) A through-hole forming hole is formed by a drill or the like. After the perforation process is completed, since a smear is generated in the through-hole forming hole, it is dissolved and removed by a desmear solution to process the copper-plated laminate. After the residue removal process, a thin layer of electroless copper is formed on the entire bottom layer of the steel foil and the inner wall surface of the through-hole forming hole by electroless copper plating. After the above electric chain process, a photomask is formed on the thin plating layer. Then, a thick-coated electric shovel layer was formed on the portion exposed through the opening of the photomask by electrolytic copper ore. After the above-mentioned electroplating process, the photomask is peeled off, and then the etching is performed in a state where an etching resist is formed on the thick coating electroplating layer by solder or the like. The thin, covered plating layer and the bottom layer are removed by this etching, and the conductor patterns are separated from each other by a γ interval. Then, the etching resist is finally peeled off, and the desired printed wiring board can be completed. 'However, the above method cannot accurately form a fine pattern with an excellent shape. This is because of the characteristics of the etching, it is easy to form a so-called lower change in which the bottom is longer than the top. Wide-shaped conductive pattern β Therefore, it is very difficult to form a pattern (such as a bonding pad part) required for miniaturization and high refinement. The present invention has been made in view of the above-mentioned problems, and provides a Manufacturing method of printed wiring board with excellent shape of fine conductor pattern [disclosure of invention]. The manufacturing method of multilayer printed wiring board described in item 1 of the scope of patent application is to achieve the above purpose, and its technical characteristics Must include the following

Fifth invention description (9) (1) ~ (5) process: (1) pressure-cure process, is a layer forming resin pressure-bonded to the conductor electricity 'to form a metal film interlayer resin insulation (2) thinning process, The system is formed on a substrate. Into. 3. The block metal film is thinned by etching. (3) The opening setting process is (4) the opening for the formation of the via hole is provided with an opening on the metal film. The process of removing the interlayer openings exposed by the openings is to use lasers to open the openings for the formation of via holes.丨 The purpose is to provide resin for insulating layer formation (5) through hole formation process, depositing plated conductors to form interlayer holes' for opening the above-mentioned through hole formation [: Phase film and reduce its thermal conductivity. The use of etch can use a low-power laser to p as a uniform cover, the edge layer will not be produced on the resin: at the same time in the interlayer resin method 'application The manufacturing of the multilayer printed wiring board under the second item of the patent: Its technical characteristics include the following processes (1) to (8): Layer ^ 1) Pressure bonding process, which insulates the interlayer resin that has formed a metal film into (2) a thinning process, in which the above-mentioned metal film is thinned by etching; (3) an opening setting process, in which openings are provided on the above-mentioned metal film; The opening setting process for forming a via hole is formed by using laser light to remove the resin for forming an interlayer resin insulation layer exposed through the opening.

Page 13 4074453 V. Description of the invention (10) Opening for formation of via hole; (5) Electroless plating film forming process, which forms an electroless plating film on the above-mentioned conductor circuit forming substrate; (6) Electroplating light The resist formation process is to form a photoresist on the conductor circuit forming substrate; (7) The electrolytic plating process is to perform an electrolytic key on the unformed part of the above plating resist; (8) The removal process is to firstly The photoresist is removed by electroplating, and then the metal film and electroless copper plating film under the photoresist are removed by etching. In addition, in the invention of the second scope of the patent application, since a metal film that is thinned and reduced in thermal conductivity using a button cut is used as a uniform cover, a laser with a low power can be used to form the opening, and In the case of interlayer resin insulation, no side erosion occurs on the formed resin. θ dissolves the plating layer. In the electroplated layer, a thin film is left in the middle, the above-mentioned gold is in the middle, and the intervening layer is further removed by a physical circuit, so that the circuit area can be easily removed, and the layer can be formed, and then the conductive layer can be formed. It can be reported to form a special application film for application of special technology. After applying the opening for special technology, it can be formed on the metal film. When electroless plating and interlayer holes are placed on the electroless plating layer, the photoresist layer will be lowered. No electrolysis, and at the same time, because the metal film and the electroless electric boat layer are removed, so the electrolytic plating layer of the via hole will not be reached during the etching. The manufacturing method of the multilayer printed wiring board of item 3 is described in item 1 or 2 of the patent application scope, and the manufacturing method and production method of the multilayer printed wiring board of item 4 is described in item 1 or 2 of the patent application scope. Mentioned

Page 14

5. Description of the invention (11) The process of thinning the above metal film by etching, wherein the thickness of the metal film is 5 to 0.5 m. In item 4 of the scope of patent application, the thickness of the metal film is reduced to 5 ~ β. This is because if the thickness of the metal film exceeds 5 # m, a side invasion button will be generated; on the other hand, if the thickness is 0.5 / 5 / m or less, the effect as a uniform cover cannot be obtained. In item 5 of the scope of the patent application, the resin for forming an interlayer resin insulation layer having a thickness of m 瞑 is formed on the conductor circuit forming substrate by pressure bonding. ‘In this invention, because a tree-wrinkled thin & film (f i I til) formed in advance with a thin metal film is pressure-bonded, it is excellent in flexibility and can be easily pressure-bonded to a conductor circuit γ " to form a substrate.

The invention relates to a method for manufacturing a multilayer printed wiring board. The multilayer printed wiring board is to form a lower-layer conductor circuit on a substrate, and an insulating resin layer and an upper-layer conductor circuit are provided on the lower-layer conductor circuit. The circuit and the above-mentioned upper conductor circuit are connected by using via holes. The manufacturing method includes the following steps: forming the above-mentioned lower conductor circuit on the substrate, followed by setting the above-mentioned insulating resin layer on the above-mentioned lower conductor circuit, and then the above-mentioned insulation A roughened surface is formed on the surface of the resin layer, and a metal layer provided with an opening exposing a part of the roughened surface is formed, and the roughened surface exposed by the opening (J) is irradiated with laser light to remove the above. After forming an opening for a via hole by insulating a resin layer, the above-mentioned upper conductor circuit and the via hole are provided. The present invention relates to a method for manufacturing a multilayer printed wiring board.

Page 15 V. Description of the invention (12) Method, the multi-layer printing is conducted on the lower layer and the above-mentioned lower layer is connected, and the above-mentioned layer and the above-mentioned layer are formed on the lower-layer conductor electrical layer. Thermal compression causes it to form an opening The insulating resin layered body circuit exposed by the opening and the original reflection generated by the rupture of the present invention cannot be used to restrain the surface of the present invention to suppress the resistance of the present invention, and a metal (S ρ 〇) diameter layer is formed between the Layer holes The present invention forms a rough edge resin layer on the surface of the layer to completely brush the circuit board system circuit and the method of manufacturing the circuit. Secondly, the insulating resin layer conductor circuit is phase-integrated to connect the insulation and the roughened surface. The formation of interstitial vias. This is due to the lightning insulation resin layer based on the above reflection of the reflected light. Use a metal layer or metal foil. The opening is larger than the opening diameter. The Yu system will be removed by the metallized surface. In order to describe the upper layer of the base insulation, the following steps will be used on a single metal contact. The upper resin layer will use a 5-hole open-shaped resin layer conductor on the upper resin layer. There is a foil on the surface. After the laser light port is roughened, the above-mentioned base roughened layer is formed between the lower layer and the upper road. The one side of the upstream laminated foil is exposed to perform the photo-setting. The insulating resin is described, and by using partial etching to remove the upper layer as a result of the above investigation, it is found that the radiation surface of the opening for the via of the via is a mirror surface, and the laser light is therefore completely removed. It was found that an opening was provided in the light corresponding to the laser light by changing the laser irradiation surface to a thick f or a metal foil. The opening is irradiated with laser light at a point and the insulating resin exposed from the opening of the insulating resin (the opening of the metal layer, etc.) suppresses the reflection of the laser light, and can prevent the edge of the insulating resin layer.

Page 16 Five 'Explanation of the invention (13) 407 ^ 53's bulge', so the interstitial hole will not be disconnected. 'But it is speculated that the reason should be that the grease is easy to plasma, and the acidic etching of the road surface is based on the excellent roughening of the conductor circuit as the main type of multi-layer printing, and the conductor electric engraving liquid is formed on the insulation layer on the conductor grease insulation layer. As a result of the roughening process, strips are formed, and the liquid guides the laser light into the formed surface, and is thus constituted. On the circuit board, a dielectric layer is formed on the circuit so that the surface of the dielectric path is treated with striated depressions. Although the reason for suppressing the bulge is not clear because the rough surface has a high laser light absorption rate, so the plasma is formed. As a result, no uplift occurs. In order to achieve the above object, the present inventors have discovered that the use of an etching treatment using a second copper complex and a body circuit can make the conductors uneven when irradiated, and can form a resin insulation layer between the layers and In the present invention, the adhesiveness of the via hole is conceived in the present invention. The application of the patent application No. 12 is related to the following. The structure is to form a conductor circuit on a substrate, and an interlayer resin insulation layer is placed between the interlayers. The opening for the tree hole and the other conductor circuit in the interlayer resin layer hole are further characterized in that: the second copper complex and the organic acid are used to etch into the inner wall of the opening for the interlayer hole at the same time. No. 3 of the patent application scope relates to a method for manufacturing a multilayer printed wiring board, including the following steps: ① a process of forming a conductor circuit; ② a process of providing an interlayer and a resin insulation layer, which is provided with an interlayer resin on the above conductor circuit Insulating layer; ③ The process of setting openings for vias in the interlayer is performed by irradiating laser light.

Page 17 407453 Description of the Five 'Invention (14) The above interlayer resin insulating layer is provided with openings for vias; and ④ The process of forming other conductor circuits containing vias is to form vias on the interlayer resin insulation layer Other conductor circuits; wherein the surface of the conductor circuit is roughened by using an etching solution containing a second copper complex and an organic acid before carrying out the above-mentioned process of (2). In the manufacturing method of the above-mentioned multilayer printed wiring board, the roughening treatment for the conductor and the circuit surface is performed by spraying and washing the dispersion liquid containing the second copper complex and the organic acid on the conductor. It is preferable that the circuit surface is impregnated with the above-mentioned conductor circuit in the above-mentioned shoe scoring solution under foaming conditions. The 15th item in the scope of the factory's patent application relates to a multilayer printed wiring board. The multilayer printed wiring board alternately laminates the interlayer resin insulation layer and the conductor layer, and through-holes formed by the above interlayer resin insulation layer. A via hole formed by forming a metal film thereon to connect between the conductor layers is technically characterized in that stripe-shaped unevenness is formed on the side wall of the through hole. In the invention of the patent application No. 15, since the stripe-shaped unevenness is formed on the side wall of the through hole, the contact area with the metal film can be increased, and the tight adhesion can be improved, so a highly reliable medium can be formed. Layer holes.

In addition, the stripe-shaped unevenness is provided along the direction of the hole, so even if an external force is applied to the up and down direction of the via hole, the via hole will not peel off. Therefore, even if a resin residue remains in the through hole for the via hole, The residue is expanded by heating and the interstitial hole is not lifted when it is squeezed up, so it can ensure its connection reliability. Also ’forming a bump in the via hole and mounting such as 1C wafer and thermal expansion with resin

V. Description of the invention (15) After parts with different expansion rates, an external force will be applied in the up and down direction of the hole. The heat cycie is used in the interstitial irregularities along the direction of the hole. Even in the above-mentioned situation, Since the stripe-like depressions Δ AQ are provided, the via holes do not peel off. reduce. This interval is approximately the same as the effect of the compact withdrawing of the disk / metal film, and the wavelength of the light emitted by the person a is 1/2. The structure of the metal layer of the hole is generally based on electroless plating 貘 貘: = the side of the side wall of the two holes, 隹. This is because the formation of the I electrolytic thunder and electrolytic electricity ore film is smoother than the bumps. It can be regarded as a pseudo 2 plating film that is harder than the electrolytic plating film, and the stripe causes the metal film to tear and break. Outside force is applied away. When He Shi breaks, the interstitial holes will not be improved by peeling through the holes. On the surface of the stripe-like unevenness, the average surface roughness Ra is 0, 〇5 ～ 5 PLUS > ,,, 乂Office style ten competes with watchmakers, and Fendian uses a 1 * roughened surface (the enlarged figure of Figure 31 (Λ) U Shishi §. This is because it can further improve the tight adhesion. If the thickness of the side wall of the through hole If the surface is too complicated, the transmission delay or noise (no 1 se) will occur due to the surface effect when transmitting high-frequency signal lines. However, the stripe-shaped unevenness of the present invention has a gap of 20 cm, so There is almost no problem with the skin effect, and it can improve the tight adhesion. The surface of the conductor circuit that leads to the through-hole is most suitable for the electrolytic plating film. This is because compared with the electroless plating film. The crystal particles are small, have excellent gloss, and are easy to reflect laser light, and are most suitable when incident light and reflected light of laser light interfere as described later.

Page 19 V. Description of the invention (16) It is preferable that the surface of the conductor circuit leading to the through hole is provided with a metal roughening layer. By providing a metal roughened layer on the surface of the conductor circuit, the laser light on the surface of the metal roughened layer can be reflected and the incident wave of the laser light can interfere with the reflected wave. Therefore, the wall surface of the through hole of the interlayer resin insulation layer can be used. The stripe-shaped unevenness is provided along the upper direction to the hole direction. In addition, since the reflection of the laser light can be suppressed below a certain limit by the roughened layer, it is possible to prevent the resin on the surface of the conductor circuit from becoming hard. Furthermore, since the roughened layer can ensure close adhesion to the interlayer resin insulation layer, it can prevent the interlayer resin insulation layer from peeling due to deterioration caused by thermal shock of laser light. 〇 'If the roughened layer is not provided, the resin will harden easily due to the high reflectance. In addition, even if the roughened layer is provided by oxidation (blackening) treatment, it will be absorbed by laser light. Dropped and unable to reflect. Rj 'of the roughened layer is preferably from 0.05 / zm to 20jCim. If it is less than 0.005 Am, the inside will be black and the laser light will be absorbed; if it exceeds, then the laser light will be too scattered to interfere with the incident wave and the reflected wave. As for the roughened layer as described above, it is preferred to apply the following treatment to the roughened layer: physical roughening such as grinding; physical gasification (blackening)-reduction Non-oxidizing chemical roughening, such as treatment, sulfuric acid hydrogen peroxide aqueous solution treatment, and roughening treatment using an extreme etching solution composed of a second steel complex and an organic acid in the presence of oxygen; -p, Cu_c〇_p and other alloy plating, etc. Of the above

Page 20 474553 V. Description of the invention (17) Any metal roughened layer can reflect laser light. For the above-mentioned Cu-Ni-p plating, for example, copper sulfate (0.1X102 ~ 25χΐ 0-2 ^ 0! / 1), nickel sulfate (〇 · 1 X i 〇_3 ~ 4〇X 10— 3nioi / U, citric acid (ix 1〇-2 ~ 20X 1〇-2m〇1 / 1), sodium hypophosphite (lXlCM-lOXlO-i mol / 1), acid deletion (ΐχΐ〇-ι ~ ιο .οχ 1 mo 1/1) and surfactant (manufactured by Nissin Chemical Industry Co., Ltd., surfinol 465) (〇 · 卜 1〇g / 1) aqueous solution of pH = 9 composed of an electroless plating bath. In addition, in this case The second steel complex used in the invention is preferably a second steel complex of the azole type. The second copper complex of the azole is used as an oxidizing agent such as metal oxide copper. As far as azoles are concerned, dijun, trisial, and tetrasial are preferred. Among them, imidazole (iraidazole), 2-methylimidazole, 2-fluorimidazole, 2, ethylimidazole, 2-ethyl 4-methyl imidazol, 2-phenyl imidazol and 2-undecyl imidazole (2-undecyl imi dazο 1 e), etc. are preferred. The addition amount of the second copper complex of saliva is 1 ~ 15% by weight is better. So it will be excellent in solubility and stability. In addition, it can also dissolve noble metals such as Pd that form the catalyst core. In addition, in order to dissolve copper oxide, organic acids can be blended in the second copper complex of rhenium. For specific examples, selective free formic acid, Acetic acid, propionic acid, butyric acid, valeric acid, hexanoic acid, acrylic acid, succinic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, stearic acid, glycolic acid, propionic acid, It is preferred that at least one component of the group consisting of malic acid and amino acid is contained. The content of organic acid is preferably 0.1 to 30% by weight. This can maintain the solubility of the oxidized copper and ensure dissolution. Stability. The first copper error

Page 21 _4〇7453 5. Description of the invention (18) " 'The compound is dissolved by the action of acid, then combined with oxygen to become a second copper complex, and then used for the oxidation of steel. In addition, in order to supplement the dissolution of steel and the oxidation of azoles, i element ions can also be added to the etching solution. The above-mentioned tooth ions can include, for example, fluoride ions, chloride ions and bromine ions. , Sodium gas, etc. can supply halogen ions. The amount of halogen ions is more preferably 20% by weight. In this way, the adhesion between the roughened surface formed and the interlayer resin insulation layer is very excellent. ’,

The etching solution is adjusted by dissolving the second copper complex of azoles and an organic acid (corresponding to the use of halogen free cattle if necessary) in water. In terms of oxidation-reduction treatment, oxidation baths of NaOH1 ~ 100g / i, NaC102l ~ 100g / l, Na3P041 ~ 50g / l, and

NaOHi ~ 100 g / l, NaBH4h50g / l reduction bath. The above metal roughened layer may be further coated with a selective Ti

More than one metal. In this way, it can ensure its gloss and improve the adhesion to the solder light p. The thickness of the above-mentioned metals is preferably 0.001 to 10 # claws. In the present invention, in particular, the through-holes for the vias of the interlayer, and the diameter thereof is preferably from 80 to m. The contact area between the above-mentioned minute via hole and the metal film constituting the via hole and the side wall of the via hole for the via hole is extremely easy to peel off. Therefore, it is impossible to fully imitate peeling when forming the enlightenment of knowledge; If the roughened surface is too complicated, problems such as propagation delay or noise may occur due to the surface effects described above. ; Ming can solve the above contradictions.

Article 22 ^^ V. Description of the invention (19) Also 'item 16 of the scope of patent application is explained in item i 5 of the scope of patent application' Its technical feature is that the interlayer resin insulation layer is made of thermosetting resin A composite of a thermosetting resin and a thermoplastic resin. In the invention claimed in item 16 of the patent application range, since the interlayer resin insulating layer is made of a thermosetting resin or a composite of a thermosetting resin and a thermoplastic resin, it can be easily interfered by lasers. Streaks are formed. '

In addition, item 17 of the scope of patent application is described in item J 5 of the scope of patent application, and its technical feature is that it contains a propylene-based monomer. In the invention of claim 17 in the scope of the patent application, the interlayer resin insulating layer preferably contains a propylene-based monomer. In this way, the crumbs of the resin can be reduced. The diene-based single system is formed by crosslinking a monomer or polymer (oligomer) of a thermosetting resin (containing a part of a photosensitized substance). Since propylene-based monomers are relatively easily decomposed by laser light, it is estimated that if a propylene-based monomer is contained in the molecular chain as described above, the propylene-based monomer can be decomposed by laser light, and even if the thermosetting resin is reduced in molecular weight Furthermore, since the resin which becomes a low-molecule can be further decomposed by laser light, it is easy to be plasmatized and almost no resin residue remains.

In terms of acrylic monomers, 'commercial products such as DPE-6A, KAYAMAER PM-12 and PM-21 manufactured by Nippon Kayaku Co., Ltd. and R-60 manufactured by Kyoeisha Chemical Co., Ltd. 7' &7; Eve: ^ M_315 u25 & m_215 and so on.

V. Description of the invention (20) DPE-6A is disclosed in Chemical Formula 1 as shown in FIG. 59, R-604 is disclosed in Chemical Formula 2, and 歹 only two M-315 series are disclosed in Chemical Formula 3; M- The 215 series is disclosed in Chemical Formula 4 shown in FIG. 60, and the KAYAMAER PM-1 2 and PM-21 series are disclosed in Chemical Formula 5. The 18th item of the scope of patent application relates to a method for manufacturing a multilayer printed wiring board, which includes at least the following processes (a) to (d): (a) a process for forming a conductor circuit; (b) a resin coating process The process is to coat resin on the above-mentioned conductor circuit; 0 ”(c) The process of forming stripe-shaped unevenness is to form carbon dioxide gas laser ft? In the manufacturing process of the above-mentioned conductor circuit through-hole, the carbon dioxide gas laser fan & ^ A +, -rf ^ ^ ^ ^ is irradiated with the above-mentioned conductor circuit under the resin vertically, and: Postscript β from the early and also ^ ^% reflections of the reflected wave and incident waves N, π: the human side & forming a stripe-shaped unevenness; and

Cd) The formation of the via hole to form the via hole. 'In the above invention, the coating of gold on the through-hole is in the patent application No. 1 + the laser is directed vertically under the resin. Because the reflected wave of the carbonic acid gas and the incident wave path are irradiated, stripes can form from the conductor circuit wall Like bumps. It can be formed on the side of the through hole and has high reliability. The interlayer hole can form close adhesion with the metal. The scope of patent application is 19%. The technical characteristics are as follows: The 18th patent scope of the patent is made of thermosetting resin or heat

^^ 453 5. Composition of invention description (21). 'Because the laser light of the interlayer resin insulating grease and the thermoplastic resin forms a stripe-shaped composite of a hardening resin and a thermoplastic resin, in the invention of item i 9 of the patent application, the layer is composed of a thermosetting resin or a thermosetting resin. The composite is composed, so the unevenness can be easily used. Chu RS applied for the 20th patent scope in the patent application to explain that the 18th or technical feature of the patent application scope is that the above-mentioned process for forming the interlayer hole is coated with an electroless copper bond film, and then a photoresist is formed, and then Mine; the ore film is energized to form electricity in the unformed part of the photoresist. In the invention of the range 20, the formation of the interstitial pores is first = after the copper electrolysis is solved, a photoresist is formed, and then borrowed = electricity: The clock film is energized to form an electrolytic system on the unformed part of the photoresist. Stripe-shaped unevenness is formed on the side wall of the through hole by laser interference, and then an electroless plated film is formed. Therefore, the resin insulating layer is formed between the through holes. High tightness: = High indicates that the above-mentioned interlaminar resin insulation layer contains the C-application patent No. 21 and No. 6 in the patent application scope. Its technical characteristics are: olefinic monomer. The method is to achieve the above-mentioned purpose ’and use the formula in Item 22 of the scope of patent application! !! The 22nd item is about a method of making a printed circuit board, including at least the following U) and (b) processes: The process of forming a fresh tin photoresist layer is a

Page 25 V. Description of Invention (22)

A solder photoresist layer is formed on the surface of the substrate of the road; and (b) the process of penetrating through holes is to make a tin photoresist layer so as to penetrate through the above-mentioned conductor circuit ... The above-mentioned welding In the 22nd invention of the patent application scope, the laser is "..." so the material is not limited to layers but various materials that can be used as solder photoresist layers can be used.

In addition, the resin residue of the solder photoresist layer can reduce the surface of the electrode. Electrolytic ore film is most suitable. Electrolytic Plating 2: The electrolytic plating film has large crystal particles, excellent gloss, and is easy to reflect laser light. It is most suitable in the case of incident light and reflection of laser light as described later. The “23rd” patent application scope indicates that in the 22nd patent application scope, the technical feature is that the surface of the conductor circuit contains a metal roughened layer.

Because the metal roughened layer is provided on the surface of the conductor circuit, the laser light will be reflected on the surface of the metal roughened layer, and then the incident wave of the laser light and the reflected wave can be interfered as described later, so it can be used in the solder resist layer. The wall surface of the through hole is provided along the hole direction. Item 24 of the scope of patent application is that in item 22 of the scope of patent application, the technical characteristics are as follows: after the above process (b) is performed, then cp is arranged on the through-hole to form a bump composed of a low melting point metal. Process (c) ° In the invention according to the 24th aspect of the patent application, a bump made of a low melting point metal is formed on the solder photoresist layer through hole. On the bump, on the one hand,

Page 26 V. Outline of the invention) —---- £ Or on the other hand, the bump can be used to actually load the printed circuit board into other printed circuit boards. In addition, item 25 of the scope of patent application is that in the patent application item ^ 'its technical feature is that the above-mentioned process order for forming a through hole is irradiated with a single H (S1I ^ erode) laser to form a diameter of 300 ^ m ~ 650 / zm through hole. & In the invention of the 25th item of the patent scope, since the beam 3 Γ is used to irradiate a single-mode laser with a variable size, it can form a diameter through-hole, which can also be used in solder light and other printed circuit boards. (For example, motherboard-rd, the through hole of the bump used by the factory. From item 1: the scope of item 26, it is explained in item 22 of the scope of patent application that its ingenious technique is characterized by the process of forming the through hole. In the invention, a laser beam is used to illuminate the laser beam to form a shell hole with a diameter of 50 " ~ 30 "m. In the invention of item 26 of the patent scope, because the beam is used, The diameter ^ Shiding $ mode laser is irradiated, so it can form a diameter of 50 kernels and 300, that is, a through-hole of the bump for the IC chip connection can be formed on the fresh tin photoresist layer. G MH special scope item 27 It is explained that in item 22 of the scope of application for patents, Jiang Xi's technique is characterized by: in the process of forming the above-mentioned through-holes, the carbon dioxide gas is emitted by the laser, the laser is perpendicular to the above-mentioned conductor under the solder resist layer. The ice is involved in the through-hole by the reflected wave and incident wave reflected by the conductor circuit. The side wall is formed with striped unevenness.

V. Description of the invention (24) In the application for the interference of the above-mentioned through-hole wave, the through-hole is formed in the hole. In the patent application, the technology features streaks and melting points on the walls. Through-holes formed by forming stripe-shaped dot metal on the application patent are tightly closed. In the application for a patent, a strip is formed on the wall with the technical characteristics of the conductor. The through-hole is formed in the application layer. In addition, the thermal expansion coefficient is different, but in the invention of the 27th scope, because Because the reflection wave generated by the carbon dioxide gas laser in the forming process and the side wall incident on the through hole form a stripe-like unevenness, when the metal film is formed, the metal film can be closely adhered to the penetration range. The 27th feature of S Erming in the scope of patent application lies in that the above-mentioned process for forming bumps is to install a metal film on the through-holes with side asperities, and then fill the low-margin invention in the 28th invention. The low-melting bump is filled after the metal film has been provided on the through-holes in the unevenness of the side wall, so that the metal film can be closely adhered with the stripe-like unevenness, and the bumps can be firmly connected to the conductor circuit area. The substrate of the 9th circuit is thermally circulated at the time of the perforated side wall metal film of the above-mentioned textured unevenness, so the surface of the solder in the present invention has a shape Q Paragraph invention in a photoresist layer is formed on the article 'can be the time, since the photoresist layer will be the gold, the metal species of the printed wiring board? It is made of solder resist, and the side of the through-hole that it is penetrated is tightly adhered to the through-hole because of the bump-like unevenness of the solder resist. It belongs to the crack of film and solder photoresist layer.

Hi Page 28 —-_ ^ 07453 _____ ^ 5. Description of the invention (25) The wall surface of the through hole is tightly adhered, so it is not easy to crack. In addition, by providing stripe-shaped unevenness along the direction of the through-hole wall surface, the contact between the wall surface and the low-melting-point metal can be a line contact instead of a surface contact. Ionization diffusion phenomenon (mi gr at i on). The low-melting metals and metal films used are the same as those described above. As described above, the surface of the conductor circuit is most preferably an electrolytic plated film. Compared with the electroless plating film, the electrolytic plating film has smaller crystal particles and excellent glossiness. In addition, there is a little so-called yellowing discoloration phenomenon of the electric clock, so that the laser light can be more easily reflected. Stripe-shaped unevenness is provided in the direction of the hole. 'The interval between the convex and convex (or concave and concave) of the stripe-shaped concavo-convex is preferably 20, / ym. If it is too small or too large, the effect of close adhesion with the metal film is reduced, and since the state of surface contact is almost unchanged, the above effect cannot be obtained. This interval is approximately 1/2 of the wavelength of the laser light. For low melting point metals, solders such as Sn / Pb, Ag / Sn, and Ag / Sn / Cu can be used. In addition, the above-mentioned bumps can pass through Ni / Au, Ni / Pd / Au,

Cu / Ni / Au and Cu / N i / Pd / Au and other metal films are formed. 〇1〜1〇 Cu, Ni layer system is adjusted to 0.1 ~ 10 m 'and Pd, Au layer is adjusted to 〇1〜1〇. Item 30 of the scope of patent application is described in item 29 of the scope of patent application. Its technical feature is that G forms a bump composed of a low-melting-point metal by a metal film located in the aforementioned through hole. 1. In the invention of the 30th scope of the patent application, since the low-melting-point metal is filled with a metal film located in the through hole to form a bump, the through hole can be formed with a stripe-like unevenness on the metal film. Tightly adhere and will be convex

Page 29 ^ 07453

V. Description of the invention (26) The block is firmly connected to the conductor circuit. The 31st item in the scope of the patent application, the 30th item, its technical characteristics are made of resin or thermosetting resin. In the scope of application for patent No. 31, it is made of thermosetting resin or thermosetting material, so it can use thunder-like unevenness. In addition, when only the stripe is decomposed, it is difficult to form the item No. 32 in the scope of patent application. Its technical features are: layers. A metal roughened layer is formed on the 32nd surface of the scope of the patent application as a metal roughened layer. Therefore, the laser is formed as described later, and the wall of the solder photoresist layer through hole is uneven. In the present invention, a resin insulating layer is preferably used. The untreated acid or ammonium is most suitable for dispersing in acid or oxidizing agent. on. It is explained that the chemical resin and the thermoplastic resin injected in the through-holes form a clear recess in the invention of the invention of soldering and thermoplasticity. The characteristics of the invention of the conductor are described in Shen. In the case of light, the incident wave of the metal and the reverse surface along the hole, electroless plating, soluble, hardly soluble, patentable range, tin photoresist layer resin compound, because the side of the solder thermoplastic resin is easily greased Convex shape. The patented Fanyuan circuit surface shape is set in the interference direction of the wave guided on the surface of the conductor's electric roughening layer. The adhesive is used as an adhesive. It is the uncured heat-resistant resin particle No. 29 or a heat-cured material. The structure of the photoresist layer is compounded to form stripes. The resin is melted. The 29th to 31st, the surface of the circuit surface with a roughened body is reflected and enters. Therefore, the stripe shape is the same in the hardened and simultaneous resin.

Page 30 V. Description of the invention (27) By treating with acid and oxidant, 'the heat-resistant resin particles can be bathed and removed', the surface is formed by a stripe-shaped thickening layer (anchor). Chemical surface. In the above-mentioned adhesive for electroless plating, especially the above-mentioned hardened heat-resistant resin particles, it is preferable to use those having the following conditions: ① heat-resistant resin powder having an average particle diameter of 10 m or less; ② make Aggregated particles of heat-resistant resin powder with an average particle diameter of 2 m or less;

③ A mixture of heat-resistant resin powder having an average particle diameter of 2 to 10 and a heat-resistant resin powder having an average particle diameter of 2 m or less; ④ on the surface of the heat-resistant resin powder having an average particle diameter of 2 to 10 Am Similar particles formed by attaching at least one component of a heat-resistant resin powder or an inorganic powder having an average particle diameter of 2 am or less; ⑤ Heat-resistant resin powder with an average particle size of 0 to 0.8 A mixture of heat-resistant resin powder having a diameter y of 0.8 μm but less than 2 μm; ⑥ A heat-resistant resin powder having an average particle diameter of 0. W'0. Based on this, the use of the foregoing and the like makes it possible to form a more complicated adhesion-promoting layer. The depth of the dense pupa is preferably R J = 〇. 〇 卜 20 # m, because f 耆 properties can be ensured. Especially in semi-additive method

One ancient _ better. This makes it possible to remove the electroless plated film while ensuring tight wear resistance. Among the above-mentioned acids or sulfonating agents, the resin composite is composed of a thermosetting resin and a thermosetting resin, which is a hardly soluble heat-resistant resin.

Page 31 --- ^ tf-453 ---- 5 'Invention (28) or "Resin composite composed of photosensitive resin and thermoplastic resin" is preferred. The former has higher heat resistance. As the thermosetting resin, epoxy (ep0xy) resin, phenol resin, polyimide resin, and the like can be used. Among them, acrylate of epoxy resin is most suitable. For epoxy resins, phenol novolak solid type (pheno 1 novalak) type, cresoi novalak solid type type phenolic solid type epoxy resin, and dicyclopentadiene ( dicyclopentad Uene) modified alicyclic epoxy resin. In terms of thermoplastic resins, polyethers can be used; (poiyethersulfone) (PES), poly (polysulfone), (PSF), polyphenylenesulfone (PPS), polyphen.ylenesulfide ) (PPES), polyphenylether (PPE), and polyether imide (PI). The mixing ratio of thermosetting resin (photosensitive resin) and thermoplastic resin is preferably thermosetting resin (photosensitive resin) / thermoplastic resin = 95/5 to 50/50. In this way, high toughness can be secured without compromising heat resistance. The mixed weight ratio of the heat-resistant resin ′ particles is preferably 5 to 50% by weight, particularly θ, 10 to 40% by weight, with respect to the solid content of the heat-resistant resin f matrix. '& Heat-resistant resin particles ’can use ammonia (a m i η 〇) resin [melamine resin, urea resin, guanainine tree

Page 32

Grease] and mounting oxygen resin. Furthermore, it may contain a propylene-based compound. The 'adhesive' may be composed of two layers having different compositions. In addition, in the case of the solder photoresist layer attached to the surface of the multilayer printed wiring board, > the two thermosetting resins or a composite of the thermosetting resin and the thermoplastic tree η are forcefully used, for example, Shuang A ( bisphe η ο 1 A) type epoxy tree month, double discretion · acrylic acid vinegar of type A epoxy resin, acrylate solid epoxy resin and acrylic solid epoxy resin etc. Resin which is cured by amine hardener or im 丨 da ζ ο 1 e hardener. On the other hand, since the above-mentioned solder photoresist layer is made of a tree cock with a rigid bone frame, it will peel off. Therefore, it is possible to prevent the solder resist from peeling off by providing a reinforcing layer. Here, as for the acrylate of the above-mentioned phenol old solid-type epoxy resin, 1 a ring capable of making phenol novolac solid or cresol novolac solid can be used. Glycidyl ether and acrylic or methyl Acrylic and other epoxy resins. The above imidazole hardening is preferably liquid at 25 ° C. Because if it is liquid, it can be mixed uniformly. For the so-called liquid imidazole hardener, 1-benzyl-2-Q methyl group (l-benzyl-2-methyl imidazole) (product name: 1B2MZ), 1-cyanoethyl can be used. L-cyanoethyl-2-ethyl-4-methyl imidazole (product name: 2E4MZ-CN) and 4-methyl-2-ethylimidazole (4-

5. Description of the invention (30) methyl-2-ethyl imidazole (product name: 2E4MZ). The added amount of the sialyl sclerosing agent is preferably 1 to 0% by weight relative to the total solids content of the solder photoresist composition. The reason is that if the added amount is in the above range, it is easier to mix uniformly. It is preferable to use a glycol ether solvent as the solvent for the above-mentioned hardened photoresist composition. E. The solder photoresist layer using the above composition does not generate free acid and the surface of the copper pad. It will not oxidize. In addition, the harmfulness to the human body is also very small. For the above-mentioned glycol mysterious solvents, it is 'as shown in the following structural formula,' as shown below, especially by using diethylene glycol dimethyl ether i (diethyleneglycol dimethyl ether) (DMDG) and triethyleneglycol dimethyl ether (DMTG) are preferred. At this point, the above-mentioned solvents can completely dissolve benzophenone and Michler's ketone by heating at a temperature of about 30 to 50 ° C. CH30-(CH2CH20) n-CH3 (n = 1 to 5) The ethylene glycol solvent is preferably 10 to 70% by weight relative to the weight of the solder resist. In the solder photoresist composition described above, v-other substances such as various defoamers or leveling agents (1 eve ii), "'," can be added with good heat resistance or alkali resistance and can be given The flexible thermosetting tree r is used to improve the photosensitivity of image resolution and the like. m u

407453

V. Description of the invention (31) For example, in the case of a flattening agent, it is preferable to use an acrylic polymer. In addition, the starting line is based on Shanghai's eight-party system, which is equal to Y. j g 〇 7 is preferred 'and the photosensitizer is DETX-S made by Nippon Kayaku. Furthermore, a pigment and a surface may be added to the solder resist composition. Accordingly, the circuit pattern can be hidden. The pigment is preferably Phthalocyanine Green.

As the above-mentioned thermosetting resin as an additive component, a bisphenol type epoxy resin can be used. The bisphenol type epoxy resin includes bisphenol A type epoxy resin and bisphenol F type epoxy resin. It is better to use the former when the alkali resistance is emphasized, and when the viscosity is required to be lowered For coating properties), the latter is preferred. As the above-mentioned photosensitive monomer as an additive component, a polyvalent propylene-based monomer can be used. The use of polyvalent propylene monomers can increase the resolution. For example, DPE-6A manufactured by Nippon Kayaku Co., Ltd. and r-604 manufactured by Kyoeisha Chemical Co., Ltd. can be used as the polyvalent propylene monomer. In addition, the above-mentioned solder resist composition is more preferably 0.5 to 10 Pa · s at 25 ° C, and more preferably 10 Pa · s. Accordingly, a low-viscosity coating can be performed using a roll coater.

In addition, the manufacturing method of the multilayer printed wiring board described in item 34 of the scope of the patent application is to set up through-holes by laser processing on both sides of the copper-clad laminate, and to conduct the inner wall of the conductive plate to form through-holes. The core substrate is formed with an interlayer resin insulation layer and a conductor circuit on the core substrate. The technical feature is that the thickness of the copper foil on the two-sided copper-clad laminate is less than 12

Page 35

β Π1 0 ^ Further, the through-hole forming substrate of the 37th scope of the patent application is formed by providing through-holes on both sides of the copper-clad laminate and conducting the inner wall of the through-hole. The technical features are as follows: The multi-layer printed circuit board is formed in a cone shape and additionally has a patent application scope of 40. It is provided with through-holes on both sides of the copper-clad laminate and a substrate formed with through-holes whose inner walls have been guided and transformed An interlayer resin insulation layer and a conductor circuit are formed on at least one of the surfaces, and its technical characteristics are as follows: The above-mentioned through-holes are formed in a tapered shape. The result of intensive research by the present inventors found that the carbon dioxide gas laser light cannot penetrate i The reason for the copper foil of 2m or more is that the surface cannot reflect i, that is, the thicker the steel box, the easier the heat conduction, so the energy of the laser light will be converted into heat and transferred. Going further—Using to control the thickness of the copper foil to less than 2 μ melon or better 1 to 10 from m, that is, the energy of laser light can be inhibited from being converted into heat and transferred ', so the use of laser light can be achieved The goal of perforation. The steel-clad laminate used in the present invention can be pre-impregnated in glass cloth epoxy resin, glass-breaking cloth bismaleiin-triazine resin, and glass cloth fluororesin. (Pre ~ preg) Copper-clad laminate with copper foil attached. The thickness of the copper box is preferably 10 mm, because if it is less than 10 mm, it is easy to perforate with laser light. On the other hand, if it is less than 1 // Π1, it will easily produce the phenomenon of swelling and bulging.

0

Page 36 5. Description of the invention (33) _ _ The thickness of the copper foil is adjusted in μm, and the length of the thickness is adjusted using the remaining time. And knight i you use sulfuric acid-peroxide + η concrete and 5 7 application of chloride and second iron and other aqueous solutions, neodymium gasification of the first copper and (., ,,.) Chemical etching, or ion beam etching (ion beam etchincF \ 丁丁 木 次 jg) and other physical etching. Copper thick-clad laminates ,,, Λ c, Λ and 乂 U · 5 ~ 1. 〇πππ is better. If the thickness is too thin, Zi Dan Xuanshu's life will not be paid. It will easily cause bending and other phenomena. The carbon dioxide gas laser used in the present invention is compared with a short pulse laser of -4 ~ 10-8 seconds. ， 乂 is 20 ~ 4〇111】 The number of shots is 5 ~ 100 times. The diameter of the formed through-hole is from 50 ～ 15 ～ 50 in m. If the car is not full, the wall surface is electrically conductive by electroplating, etc. If it is over 150, it will be detrimental to the perforation process. If the diameter of the through-hole exceeds 100, it will be strong. Dragon p 口 丨 ”a rain 6 丄, H is tapered at the through hole, that is, a large through hole is formed in a straight shape at the incident side of the laser light. The eight member bud hole is straight. Fang You 'after irradiating laser light on the surface and inside of the bank-shaped through-holes. That is to say, the cross-section is generated by the conduction of the through-holes. The conductive method is electroplating, electroless plating, sputtering, gas Deposition, solder paste (paste), etc. In terms of filling conductivity, it is better to fill the conductive solder paste with a cone at the through hole. This way the solder paste can be filled more easily. In the case where the inner wall surface is metalized by electroplating, electroless galvanization, splattering, etc. to form a through hole,

Formation of vapor phase deposition

Page 37

Description of the invention (34) " Through-hole filling filler. Also, the inner wall of the through-hole which has been metalized may be roughened again. When metalizing the inner wall of the through-hole, the thickness of the copper foil and the metallization layer is preferably 10 to 3 (). J If there is no electricity to fill the material, bisphenol F (bisphenol F Oxygen and oxygen; various substances such as soil made of inorganic particles such as May, alumina, or metal particles and resin, etc., forming substrates in the through holes formed as described above The conductor circuit is formed by the after-treatment. The surface of the slave conductor circuit is better to improve the adhesion. Tertiary. Next, an interlayer resin insulation layer made of insulating resin is set. As the insulating resin, a thermosetting resin or a thermoplastic resin 1 can be used. In the present invention, the interlayer resin insulating layer is also 2 or an adhesive for electroless plating. The above interlayer resin insulating layer can be used as 3 Or exposure, development processing to set the opening. Item 45 of the scope of patent application for 5 shots is a multilayer printed wiring board. The layered printed wiring board is formed by insulating the interlayer resin on the substrate on which the through holes and the conductor circuit have been formed. Layers and conductor circuits are alternately stacked to form 'different layers of conductor circuits. Electrical connections are made between vias provided in the interlayer resin insulation layer between the conductor circuits. It is characterized in that the above substrates use Tg points at 1 Glass epoxy substrate made of epoxy resin above 90 ° C. As a result of intensive research by the inventors, it was found that the implementation of HAST test and steam test will reduce the insulation resistance between the through holes, which is because

Page 38 V. Description of the invention (35)-Metals such as holes of steel will ionize and cause shifts (m i gr a t i on) between the holes, thus reducing the insulation resistance value. In addition, the inventors also found that the implementation of a thermal cycle test will change the resistance value of the conductor circuit between the through-holes. This is because thermal amine = shrinkage caused the conductor circuit or the plated through-hole torn and broken. In order to reduce offset and thermal expansion and shrinkage, we want to increase the crosslinking density of epoxy resins and resins and increase the Tg point. If the Tg point of the epoxy resin is above 190 ° C, the above problems can be suppressed. According to this, the phenomenon of shifting between the through holes due to the ionization of copper and other metals constituting the plated through holes, and the decrease in the insulation resistance between the plated through holes due to the implementation of the HAST test and the vapor test, etc., will not occur. Therefore, the thermal expansion and contraction caused by the thermal cycle test will cause the conductor circuit or the plated through hole to tear and break, and the impedance value will not change. … For glass epoxy substrates with a Tg point above 190 t: (DMA method (temperature rise: 20 ° C / min)), the existing substrates for multi-layer printed wiring boards developed for a large number of lamination methods can be used. For example, Mitsubishi Gas Chemical HL830 (Tg point 217 ° C), HL8 30FC (Tg point 212 ° C); Hitachi Chemical Industries MCL-E-679LD (Tg point 205 ~ 215 ° C), MCL-E-679F (Tg point 205 ~ 217 ° C); and Matsushita Electric Works R-5715 (Tg point 190 ° C). In the glass epoxy substrate or the copper-clad laminate as described above, holes can be made by laser or the like, and the inner wall surface can be metallized by methods such as galvanic plating, electroless plating, sputtering, vapor deposition, and the like. Form a through hole. Also in the

Page 39 407453 V. Description of the invention (36) Filling material for through holes. In addition, the inner wall of the metalized through hole can be roughened again. As the filler, various materials such as bisphenol F-type epoxy resin, inorganic particles such as dioxane, alumina, or the like composed of metal particles and resins can be used. A conductor circuit is provided on the through-hole forming substrate formed as described above. The conductor circuit is formed by an etching process. The surface of the conductor circuit is preferably roughened to improve tight adhesion. The resin can be made by heat and then an interlayer resin insulating layer is provided. It is called a resin, a thermoplastic resin, or a composite resin of the above. In order to solve the above problems, the invention described in item 46 of the patent application scope can be used. The 46th scope of the patent application is mainly related to a method for manufacturing a printed circuit board. The printed circuit board has a plated through hole and a conductor pattern formed by a subtractive layer method. The method includes the following steps: forming a through hole for forming a through hole The hole manufacturing process is performed at a predetermined position of a shovel metal laminate formed by attaching a conductive metal foil having a thickness of 0.50 m to both sides of an insulating base material to form a through-hole. The process of removing holes; the process of removing residues, dissolving and removing the above-mentioned holes for forming through-holes; the first plating process, forming a thin layer on the bottom layer derived from the above-mentioned conductive gold and the inner wall surface of the holes for forming through-holes Covered with white lightning plating; the second electroplating process is to form a plating on the exposed part of the opening of the same-screen cover after covering the thin coating plating layer; By the above-described curtain after release cover etched to parties other electrical position =

Page 407453

Body pattern 5. V. Description of the invention (37) The thin coating plating layer and the bottom layer under the same curtain cover separate the conductors from each other. If the invention according to item 46 of the scope of patent application is applied, the residues generated during ^ ^ " and in the same hole can be dissolved through the residue removal process to remove them, and the conductive metal at this time The foil is also thinned by dissolving and removing. Then, a thin coating plating layer is formed by the ^ 1 plating process, and only a portion where a conductor pattern should be formed thereafter is formed by using the second plating system to form a thick coating plating layer = $ Optionally thicken. Then use the engraving to remove the thin coating layer, the layer and the bottom layer under the curtain to separate the conductor patterns from each other. In the present invention, the thin coating layer and the bottom layer are both Very thin, so the thickness of the conductor pattern is removed by etching in the process of the public / force separation process is very small. Therefore, the conductor pattern of β is not easy to form a widened lower part, but can be The fine pattern with excellent shape is accurately formed. The conductive metal foil can use copper, aluminum, tin, gold, silver, platinum, and nickel. Among them, copper or copper is the most preferred metal. For example, the scope of patent application is 48 Said invention In item 47 of the scope of patent application, an electroless electroplating bath is used in the above-mentioned first plating process, and an electrolytic plating bath is used in the above-mentioned second plating process. 〇If the invention is described in item 48 of the scope of patent application In the formation of the plating layer on the inner wall surface of the through-hole forming hole, only an electroless electric bell bath is used, and then an electrolytic plating bath that is inexpensive and has a high plating deposition speed is used. According to this, γ improves the cost and productivity. The invention described in item 49 of the scope of patent application is that in item 47 of the scope of patent application, the above-mentioned first electroplating process uses electroless steel plating

Page 41 407453 V. Description of the invention (38) '-~ --- The bath is formed to cover the steel plating layer with a thickness of 0 · 2μηι ~ 2 · 5, and electrolytic steel plating is used in the above-mentioned second plating process. Bath-shaped copper plating layer with a thickness of 80 claws or more. According to the invention described in item 49 of the scope of the patent application, only the electroless clock is used when forming the plating layer on the inner wall surface of the through-hole forming hole ^, and then the electrolytic electrode that is very cheap and has a fast plating deposition speed is used Forging bath. Accordingly, cost and productivity can be further improved. In addition, after the extremely thin copper plating layer is formed in the i-th plating process, the amount of thickness that should be removed by etching in the process of dividing and breaking the conductor pattern also becomes very small. Therefore, a fine pattern having an excellent shape can be formed more accurately. According to the invention described in item 50 of the scope of patent application, it is explained that in the item 4, 7, 4, 8 or 49 of the scope of patent application 9, the above-mentioned process of separating and disconnecting the conductor pattern by etching is performed in the above-mentioned second plating The thick coated electrical chain layer formed in the manufacturing process is performed without silver etched photoresist. According to the invention described in claim 50 of the scope of the patent application, the formation of an etching photoresist is not required in the process of separating and disconnecting the conductor pattern. As a result of the peeling process, the working hours are reduced. Productivity is increased β In addition, since the thickness of the thick plated plating layer to be removed accompanying the etching at this time is also very small, it does not adversely affect the accuracy of pattern formation and the like. The invention claimed in item 51 of the scope of patent application is a printed wiring board. The printed wiring board having a conductor pattern formed by, for example, a subtractive method, is mainly characterized in that the structure of the conductor pattern includes: Metal base layer with a thickness of 0.2 / zm ~ 3.0 // 0 on an insulating substrate and formed on the metal base layer

Page 42 V. Description of the invention (39) '-------- Plating layer. _ Shen Qingzhuan 丨 The invention in item 52 of the scope is a printed wiring board, and in the printed wiring board having a conductor pattern formed by, for example, a subtractive method, the main features are: The system includes: a metal base layer provided on the insulating base material; an electric clock layer formed on the above metal base layer with a thickness of 0.2 // Π1 ~ 2_5βιη; and a layer formed on the above electroplated layer with a thickness of SO / zm or more Plating layer β [Schematic description] Figure 1 (A) 'Figure 1 (B)' Figure 1 (C) and Figure 1 (β) (This is a printed circuit board of the first embodiment of the present invention Manufacturing engineering drawing. Figure 2 (E), Figure 2 (F) 'Figure 2 (G) and Figure 2 (Η) are manufacturing engineering drawings related to the printed wiring board according to the first embodiment of the present invention. Figure 3 (1), Figure 3 (: 0, Figure 3), and Figure 3 (1) are drawings of the manufacturing process of the printed wiring board according to the first embodiment of the present invention. Figure 4 (M), Figure 4 (N)., Figure 4 (0), and Figure 4 (P) are manufacturing engineering drawings of the printed wiring board according to the first embodiment of the present invention. Figure 5 (M '), 5 (N,), 5 (0 '), and 5 (P') are manufacturing process drawings of a printed wiring board according to the first modification of the first embodiment of the present invention. C) FIG. 6 (Q) and FIG. 6 (R) are manufacturing process drawings of the printed wiring board according to the first embodiment of the present invention. FIGS. 7 (A), 7 (B), and 7 (C) are related to the present invention. Manufacturing process drawing of the multilayer printed wiring board of the second embodiment of the invention.

Page 43 407453 V. Description of the invention (40) Figure 8 (D), Figure 8 (E) and Figure 8 (F) are the manufacturing engineering drawings of the multilayer printed wiring board of the second embodiment. Fig. 9 (G), Fig. 9 (H), and Fig. 9 (I) are manufacturing process drawings for the multilayer printed wiring board of the second embodiment. FIG. 10 (J), FIG. 10 (K), and FIG. 10 (L) are manufacturing engineering drawings related to the multilayer printed wiring board of the second embodiment. Figures 11 (M) and 11 (N) are drawings of the manufacturing process of the multilayer printed wiring board of the second embodiment. 12 (A), 12 (B), and 12 (C) are manufacturing process drawings of the multilayer printed wiring board according to the first modification of the second embodiment. Figure 13 is a manufacturing process drawing of a multilayer printed wiring board according to a first modification of the second embodiment. FIG. 14 is a schematic plan view of an example of a roughened surface when a roughened surface is formed on a conductor circuit on a substrate by using the roughened processing method of the present invention in a third embodiment of the present invention. Fig. 15 is a longitudinal sectional view taken along the line A-A of the conductor circuit surface shown in Fig. I4. . = The other parts of the surface of the conductor circuit shown in Figure 14 (D), the dried figure (^), Figure 17 (B), Figure (C), and Figure 17 ku) This is not a part of the longitudinal section of the hottest process of the present invention, the manufacturing process of the layered printed circuit board. Figure 18 shows the manufacturing process of the printed circuit board (D). | Figure 18 (β), Figure 18 (C), and Figure 18 J are not the third example of the present invention = 口

A 'Zoufen' longitudinal section view of the '41 invention description process. (D) Household | 9_ Figure (A), Figure 19 (B), Figure 19 (C), and Figure 19 (a) are not the manufacturer of the multilayer printed wiring board of the third embodiment of the present invention,- Partial vertical section view.帛 2 π er μ is an oblique view of an opening σ for a via hole of a printed circuit board according to a third embodiment of the present invention. The eighth wish figure is a cross-sectional view of the opening for a hole after the printed circuit board is roughened in the third embodiment of the present invention. (D) Figure i2 (A), Figure 22 (B), Figure 22 (C), and Figure 22 # Drawings on the manufacturing process of the multilayer printed wiring board of the fourth embodiment of the present invention. Figure 23 s CE), Figure 23 (F), Figure 23 (G) and Figure 23 \ η) # rb ', a manufacturing engineering drawing (L) of a multilayer printed wiring board according to the fourth embodiment of the present invention Light picture_ 2 4 Picture (1), Picture 24 (J), Picture 24 (K), and Picture 24 are drawings (M) of the manufacturing process of the multilayer printed wiring board according to the fourth embodiment of the present invention, Figure 25 (N), Figure 25 (0), and Figure 25T 'on the manufacture of the multilayer printed wiring board according to the fourth embodiment of the present invention J 〇 2 β Invention 4 (Q) and 26 ( R) and FIG. 26 are drawings of the manufacturing process of the multilayer printed wiring board of the second embodiment. Section 7 is a drawing of the multilayer printed wiring board of the fourth embodiment of the present invention (P: process diagram L)

Page 45 407453 V. Description of the invention (42) Figure 28 is a sectional view of a multilayer printed wiring board according to a fourth embodiment of the present invention. Fig. 29 is an enlarged view of part c of Fig. 24 (I). Figure 30 (A) is an enlarged photo of the through-hole through the interlayer resin insulation layer, which is an enlarged view of the through-hole obliquely viewed from above, and Figure 30 (B) is a state from directly above. Figure 31 (A) is an enlarged view of Part A of Figure 26 (R), and Figure 31 (B) is an enlarged view of Part B of Figure 26 (R). 0 Figure 32 (A) is an enlarged photo of the through hole (upper side) penetrated by the solder photoresist layer, which is viewed from the top of the through hole obliquely, and Figure 32 (B) is viewed from directly above status. Figure 33 (A) is an enlarged photograph of a through hole (lower side) penetrated by the solder resist layer, which is viewed from directly above, and Figure 33 (B) shows the side wall of the through hole viewed from the side Fig. 33 (C) shows the state of the through-hole viewed obliquely from above. Fig. 34 is an explanatory diagram of a laser device forming a through hole. 35 (A), 35 (B), 35 (C), and 35 (D) are manufacturing process drawings of the through-hole forming substrate according to the first modification of the fifth embodiment. 36 (A), 36 (B), 36 (C), and 36 (D) are manufacturing process drawings of a through-hole forming substrate according to a second modification of the fifth embodiment. Figures 37 (A), 37 (B), 37 (C), and 37 (D) are drawings of a through-hole forming substrate according to a third modification of the fifth embodiment.

Η Page 46 407453 V. Description of the invention (43) Manufacturing engineering drawing. Fig. 38 (A), Fig. 38 (B), Fig. 38 (C), Fig. 38 (D), Fig. 38 (E), and Fig. 38 (F) are the fourth of the fifth embodiment Manufacturing process drawing of a multilayer printed wiring board of a modified example. Figure 39 (G), Figure 39 (H), Figure 39 (I), Figure 39 (J), and Figure 39 (K) are multilayer printed wirings concerning the fourth modification of the fifth embodiment Manufacturing drawings of boards. Figure 40U), Figure 40 (M), Figure 40 (N), Figure 40 (0), and Figure 40 (P) are drawings of a multilayer printed wiring board according to a fourth modification of the fifth embodiment. Manufacturing engineering drawing. j Figure 41 (Q), Figure 41 (R), Figure 41 (S), and Figure 41 (T) are manufacturing process drawings of a multilayer printed wiring board according to a fourth modification of the fifth embodiment. 42 (U), 42 (V), and 42 are manufacturing process drawings of a multilayer printed wiring board according to a fourth modified example of the fifth embodiment. Fig. 43 is a sectional view of a multilayer printed wiring board according to a fourth modification of the fifth embodiment. Fig. 44 is a sectional view of a multilayer printed wiring board according to a sixth modification of the fifth embodiment. 45 (A), 45 (B), 45 (C), 45 (G), 45 (E), and 45 (E,) relate to the sixth aspect of the present invention. Manufacturing engineering drawing of the multilayer printed wiring board of the embodiment. Figure 46 (F), Figure 46 (G), Figure 46 (H), Figure 46 (I), Figure 46 (J), and Figure 46 (K) relate to the sixth implementation of the present invention

Page 47

V. Description of the invention (44) The manufacturing engineering drawing of the multilayer printed wiring board. Figure 47 (L), Figure 47 (M), Figure 47 (N), Figure (0), and Figure 47 (P) are drawings of the manufacturing process of a multi-screen circuit board according to a sixth embodiment of the present invention. θ 丨 brush ΛΩΊ4 ^ Figure 48 (Q), Figure 48 (R), Figure 48 (S), and Figure 48 (T) are & process diagrams of the multilayer printed wiring board according to the sixth embodiment of the present invention. Fig. 49 (II) and Fig. 49 (V) are sectional views of the multilayer printed wiring board according to the sixth embodiment of the present invention. Example Γ Figure 50 is a cross-sectional view of a sixth embodiment of the present invention after multi-layer printing. Figure 51 (A), Figure 51 (B), and Figure 51 (C) of Yin board are schematic cross-sectional views of a portion of the plated steel used in the manufacture of the printed wiring board of the seventh embodiment. Figs. 52 (A) and 52 (B), on the other hand, are schematic cross-sectional views of a part of a copper-clad laminate used in the manufacture of a brush circuit board of the seventh embodiment. Figures 53 (U) and 53 (B) are schematic cross-sectional views of a part of a copper-clad laminate used in the manufacture of a printed wiring board according to the seventh embodiment. Fig. 54 is a schematic sectional view of a part of a multilayer printed wiring board according to a first modification of the seventh embodiment. Fig. 55 is a schematic sectional view of a part of a multilayer printed wiring board according to a first modification of the seventh embodiment;

407453 V. Description of the invention (45) Figure 5-6 shows a comparison chart between the second embodiment and the comparative example. Fig. 57 is a comparison chart between the third embodiment and the comparative example. Fig. 58 is a comparison chart between the sixth embodiment and the comparative example. Figures 5 and 9 show the chemical formulas. Figure 60 shows the chemical formula. [Best Embodiment of the Invention] [First Embodiment] Hereinafter, a method for manufacturing a multilayer printed wiring board according to an embodiment of the present invention will be described with reference to the drawings. / (1) Laminated on both sides of a substrate 30 with a thickness of 1 min and made of glass epoxy resin or bt (bismaleic anhydride imine triazine) resin 8 / ΐ ΐ copper foil 32 The formed copper shovel laminate 30A is used as a starting material (see FIG. 1 (A)). First, 'drill this mineral copper laminate 30A with a drill bit and then apply electroless plating treatment' and according to the pattern shape, the inner layer copper pattern 34 and the through hole 3 colors are formed on the two sides of the substrate 30 by drinking (Figure 1) (Β)). (2) The substrate 30 having the inner copper pattern 34 and the through-hole 36 formed thereon is washed with water and dried, and then used in an oxidation bath (blackening bath).

NaOH (10g / l), NaC 1 02 (40g / l), Na3P04 (6g / l), oxidation-reduction treatment using NaOH (10g / l), NaBH4 (6g / l) on a reduction bath, in A roughened layer 38 is set on the surfaces of the inner layer copper pattern 34 and the through holes 36. (3) The following raw material composition for preparing a resin filler is mixed and kneaded to obtain a resin filler. [Resin composition ①]

P.49 ^ 07453 V. Description of the invention (46) The average particle size of 100 parts by weight of a bi-phase F-type epoxy resin monomer (made by oleochemical χ, molecular weight 310, YL983U) and coated with a silane coupling agent on the surface S i 〇2 spherical particles with a diameter of 1.6 / zm (7 γ made by V., CRS110 1-CE, where the size of the largest particles is the thickness of the inner copper pattern (1 5 # m The following) i 70 parts by weight and leveling (manufactured by Meng & Co., Ltd.) 1.5 parts by weight are stirred and mixed 'and the viscosity of the mixture is adjusted to 45,000 at 23 ± 1 t ~ 49,000cps. [Hardener composition ②] Imidazole hardener (manufactured by Shikoku Chemical Co., Ltd., 2E4MZ-CN) 6.5 parts by weight. (4) The resin filler 4 obtained in the above (3) is coated on both sides of the substrate 30 with a roller coater within 24 hours after the preparation, so that the conductor circuit (inner layer steel pattern) can be filled. Between 34 and the conductor circuit 34 and in the through-hole 36 'are tested at 70 C for 20 minutes, and the other surfaces are also filled with the resin filler 40 between the conductor circuits 34 or in the through-hole 36 by the same method as above. And heat-dried at 70 ° C for 20 minutes (refer to the second figure (D)) ° (5) The surface of the substrate 30 after the above (4) treatment is processed by using # 600 belt-shaped (belt) abrasive paper A belt sander (manufactured by Sankyo Ricoh Chemical Co., Ltd.) was used to polish the surface of the inner layer copper pattern 34 and the surface of the land 36a of the through hole 36 until no resin filler remained. Buff grinding to remove the scars caused by the grinding of the belt sander. ^

Page 50 407453 V. Description of the invention (47) Then 'perform 1 hour at 100 t, 3 hours at 120 ° C, 1 hour at 150 ° C, and 7 hours at 180 ° C Heat treatment to harden the resin filler 40. (6) Alkaline degreasing soft etching is performed on the substrate 30 where the conductor circuit 34 has been formed. Then, a catalyst solution composed of palladium chloride and an organic acid is used for treatment, and a P d catalyst is given. After activating the catalyst, it was recorded by copper sulfate 3.2 parent 10_2111〇1 / 1, sulfuric acid record 3.9 /

1 0_3mo 1/1, Miter 5. 4 X 1 〇-2mol / 1, Sodium hypophosphite 3.3 X 1 0_1 mo 1/1, Butterfly acid 5 · 0 X 1 0-1 mo 1/1 And surface active agent (manufactured by Nissin Chemical Industry Co., Surfinol 465) O. lg / 1 and pH = 9 and soaked in an electroless electro-mineral fluid, and then immersed for 1 minute every 4 seconds And lateral vibration so that a needle-shaped alloy coating layer and a roughened layer 42 made of Cu-Ni-P are provided on the surfaces of the conductor circuits 34 and the ridges 36 a of the through holes 36 (see FIG. 2 (F)). Here again, a Cu-Sn. Substitution reaction was carried out under conditions of tin boron fluoride 0-lm01 / l, thiourea urea 1.0mol / 1, temperature 35C, and pH = 1.2. An Sn layer (not shown) having a thickness of 0.3 mm is provided on the surface of the roughened layer. (7) Continuing, the thickness of the resin-coated copper foil (manufactured by Li Kasei Industrial Co., Ltd .: MCF-6000E's resin 20 is 60 μm, and the thickness of the copper foil 22 is

12 / ζιπ) 20A is pressure-bonded to both sides of the substrate 30 having a thickness of 0.8 mm by vacuum pressure bonding method (Figure 2 (G). Here, the vacuum pressure point method is at 175 ° C. 90min, The pressure is 30Kg / cm2 and the vacuum degree is <50torr). (8) Secondly, use an etching solution (Mitsubishi Gas

Page 51 407453 V. Description of the invention (48) &quot; I Chemical system: trade name SE-07) Fully carved to thick. The flatness is about 3yra (Figure 2 (Η)). (9) Attach a dry film photoresist (dry fUm ^ to) on the steel box 22 (referred to as dry V system: trade name NIT-215), install a curtain cover for exposure, and then use 0 · 8% sodium carbonate is used for the development process, and the pore layer is provided with an etched photoresist 43 having an opening 43a (Figure 3 Pantu HI will read the copper 羯 22 in the opening 439 to etch the second copper with gasification. Water is mixed with two liquids (see Figure 3 (J)), and the etching photoresist 43 is separately ordered with sodium hydroxide to form a copper foil 2 2 as a uniform cover (Figure 3

Ui)) 〇 (11) Using a carbonic acid gas laser irradiation device (Mitsubishi Electric Mechanism: called, irradiate 2 and short at the opening 22a of each copper pig:; resin insulation layer (resin) between 2 and 6 at 0 0 #m 必 通通 孔, T ,, ν (L)). The copper foil 22 with a thickness of 3 / zm will also be used as it curtain cover ’to make use of laser penetration. Here, carbonic acid gas

The irradiation method of Bg Tianhu 'can be directed toward the opening 2 2 a of the individual copper foil 22 as described above. It can be irradiated with a hole at the beginning of nw, or the entire printed circuit board can be scanned by laser irradiation at 0%. To remove the resin 20 under each opening 22 &amp; of the steel foil 22. The diameter of the beam (beam) is more than 1.3 times the opening diameter. It can also be removed after the opening 20a is formed. in,

Page 52 407453__ Five 'invention description (49) Or use oxygen plasma, carbon tetrafluoride plasma or a plasma of oxygen and carbon tetrafluoride to remove the residue of wax. In particular, when using fluororesin as an insulation layer between resins, 'plasma treatment is the most suitable β. (12) First, after forming an electroless copper plating film 52 on the surface of the substrate 30 by a general electroless office, (Fig. 4 (M)), and further ^ formed a 10 / ηη electrolytic steel keying film 56 using copper sulfate electrophoresis (Fig. 4 (N) (13) Paste a dry film photoresist on copper foil 22 (say Combined with a system: product name ΝΙΤ-215), and a patterned curtain cover (not shown) is installed at a predetermined position to perform exposure at 100 mJ / cm2. Then, 0.8% sodium carbonate is used. The development process is performed, and a line / space (11116/313 巳 6): 30/30 &quot; 111 covering the via hole forming portion and the circuit forming portion is provided (Fig. 4 (0)). (14) After that, the second copper chloride is used to carry out pattern engraving, and the etching resist 54 is further stripped with 2% NaOH to form a via 60 and a conductor circuit 58 (Fig. 4 (P)). 0 In addition, in the above (12) to (14), the step of forming the photoresist 54 after forming the electrolytic copper electrical identification film 56 can also be used after the photoresist 54 is formed. The steps of dissolving the copper electroplated film 56 are replaced. The manufacturing process of the first modification is described below with reference to FIG. 5. First, as shown in FIG. 30 was immersed in an electroless copper electroplating bath having the following composition to form an electroless copper electroplated film 52 having a thickness of 0.5 # m (Fig. 5 (M,)).

Page 53 407453 V. Description of the invention (50) [Electroless plating solution] EDTA 150 g / 1 copper sulfate 20 g / 1 HCH0 30 ml / 1 NaOH 40 g / 1 α, a '-bi-bi ratio 唆 80 mg / 1 (a, a '-bi py ri dy1) PEG 0. 1 g / 1 [Electroless plating conditions] Paste dry film photoresist on copper foil 22 for 30 minutes at a temperature of 70 ° C (say Hewang Yibu &gt; System: trade name NIT-21 5) 54, and then attach a patterned curtain cover (not shown) at a predetermined position, and expose at 100mJ / cm2. Thereafter, development processing is performed with 0.8% sodium carbonate, and an etching photoresist 54 having an opening 5 4a provided in the via hole forming portion and the circuit forming portion is provided. (Figure 5 (N ')). Next, electrolytic copper plating was performed under the following conditions to form an electrolytic copper plating film 56 having a thickness of 20 / m (Fig. 5 (0 ')). [Electrolytic plating solution] Sulfuric acid 1 80 g / 1 Copper sulfate 8 0 g / 1 Additive (manufactured by Japan and Japan under the brand name AF GL) 1 ml / 1

Page 54 407453 V. Description of the invention (51) [Electrolytic plating conditions] Current density 1 A / dm2 Time 30 minutes temperature room temperature v After stripping and removing the plating photoresist 54 with 5% KOH, sulfuric acid and hydrogen peroxide are performed. The mixed solution is etched to dissolve and remove the electroless steel plating film 5 2 and the copper foil 22 located under the electroplating photoresist 5 4 to form an electroless copper plating film 30, 40 and an electrolytic copper plating film 44. The thickness of the circuit pattern 58 is 18 # m and the via 60 (see FIG. 5 (P ′)). (1 5) Finally, 'the same process as in the above step (6) is performed, 1 a roughened surface 62 made of Cu-Ni-P is formed on the surfaces of the conductor circuit 58 and the via 60, and Further, Sn substitution was performed on the surface (see FIG. 6 (Q)). (16) By repeatedly operating the processes of (7) to (15) above, it is possible to further form the upper-layer conductor circuit 88 and the via hole 90 to obtain a multilayer circuit substrate (refer to FIG. 6 (R)). However, the roughened surfaces formed on the surfaces of the conductor circuits 88 and the vias 90 are not replaced by Sri. In the first embodiment, since a metal foil (copper foil) 22 that is thinned by etching (3 # m) and reduced in thermal conductivity is used as a uniform curtain, it is possible to use a low-power laser to An opening 20a is formed. Specifically,-. In other words, in the manufacturing method of the conventional technology, if the carbonic acid gas laser described above is used, when the laser device is provided with an opening 20a at the resin 20, it is necessary to irradiate the two-pulse laser three times. In the first embodiment, the opening 20 a can be formed only by irradiating the short pulse laser twice.

^ 07453 V. Description of the invention (52) In addition, in the "first embodiment", since the opening 20a can be formed by using a low-power laser as described above or reducing the number of times of short-pulse laser irradiation, The interlayer resin insulation layer does not cause the phenomenon of knowing money on the resin 2 (refer to Figure 3 (L)) ° Therefore, the reliability of the connection of the via hole can be improved. The thickness of the metal film is preferably reduced to 5 to 0.5 / zm by etching. This is because if the thickness of the metal film is exceeded, side erosion occurs. On the other hand, if the thickness is 0.5 m or less, the effect as a uniform cover cannot be obtained. In addition, when the interlayer resin insulating layer forming resin on which a metal film has been formed is press-bonded to a conductor circuit-forming substrate and then etched, there is a thick metal film as a reinforcing material during the press-bonding, so it is easy to handle. The aspect is excellent. In addition, although the "interim order" in this embodiment is to etch after laminating the interlayer resin insulating layer forming resin on which a metal film has been formed, it is also possible to use an interlayer having a thin metal film having a thickness of 5 to 0.5 m / zm The resin insulating layer is formed of resin for pressure bonding.

-In the first embodiment, the metal film used for the uniform cover is etched and thinned. When the conductive circuit 58 and the interlayer hole 60 are formed, unnecessary portions that are uniformly covered with the cover 30 are removed by etching to complete the thinning, so they can be easily removed. Therefore, when the etching is performed, The electrolytic copper plating film 56 forming the conductor circuit 58 and the via hole 60 will not cause great erosion. Therefore, finely spaced lines and microvias can be formed. That is, the formation ability of the circuit in the manufacturing method of the conventional technology is only 75 cores.

407453 Five 'invention description (53) In the above-mentioned conventional technology, the forming ability of all covering screen covers is only 50%, and in the first embodiment, an opening of 1 3 0 # m can be provided, that is, Can form interlayer pores with fine diameter. Next, "the manufacturing method of the multilayer printed wiring board according to the second modification of the first embodiment will be explained." Because the second modification is basically the same as the first one except the base material used! Since the manufacturing method of the embodiment is the same, it will be described with reference to FIGS. 1 to 6. 〇 Using the processes of (1) to (6) above to form a core substrate 3 having a thickness of 0.4 mra as shown in FIG. 2 (jr). Next, a resin-coated copper foil (manufactured by Matsushita Electric Industrial Co., Ltd. ·· Trade name ARCC r ~ 〇88 (); thickness of resin 20 is 60em, thickness of copper foil 22 is i2 // m) 20A is pressed on both sides of the substrate 30 by vacuum pressure bonding method (No. 2 (G)). Here, the vacuum pressure-bonding method is performed at 13 0 C. 30 mi η 'and further at 175 eC. 9 0 mi η', and the pressure is 30 Kg / cm2, and the vacuum degree is <50torr. Proceeding> Next, the copper foil 22 on the surface was etched with silver (made by Mitsubishi Gas Chemical Co., Ltd. SE-07) to a thickness of 3 ^^ (Figure 2 (H)). Paste a dry film photoresist (Nikkei; made: trade name NIT-215), put on a mask, expose at 100mJ / cm2, and then develop with 080% sodium carbonate. The hole forming portion is provided with an etching photoresist 44 (see FIG. 3 (I)) of Jin Youwen 44a. '' The copper foil 2 2 in the opening 44a is removed by using a second chloride steel etching solution

Page 57 407453 V. Description of the invention (54)! The steel foil 22 is formed as a uniform cover by performing "peeling" (Figure 3 (κ) using a carbon dioxide gas laser irradiation device (Mitsubishi Electric Corporation: trade name 605GTX)) A short pulse laser was irradiated twice at the opening 22a of each copper foil to form a 60 # m 0 through-hole 20a at the interlayer resin insulation layer (resin) 20 (Figure 3 (L)) After the electroless copper plating film 52 is formed on the surface of the substrate 30 by ordinary electroless plating (Fig. 4 (jj)), further copper sulfate plating is used to form a 10 // m electrolytic copper plating film (Fig. 4). (N)).

A dry film photoresist (Nitsubishi-Buy: product name: NIT-21 5) is pasted on the copper foil 22, and a patterned curtain cover (not shown) is mounted on a predetermined position and exposed. Then, the development process was performed with 0.8% sodium carbonate, and the line / space (1 ine / space) of the hole-forming portion and the circuit-forming portion of the overlying interlayer was set. The photoresist was engraved with 50/50 m (Figure 4 (〇 ) After that, the second copper chloride is used for the pixel etching, and then the photoresist 54 is peeled off with 2% of MaOH to form a circuit 5 ^ 4M). Then, the same process is repeated for the operation layer to complete the 6-layer printed wiring board combining the two sides (6th is the manufacturing method of the multilayer printed wiring board according to the 3rd modification of the i-th embodiment: description. Because this The third modified example is substantially the same as the first one except for the base material used. Therefore, the method is performed by referring to FIGS. 1 to 6.

407453 V. Description of the invention (55) The process of (1) to (6) above is used to form a core substrate with a thickness of 0,6mm as shown in Fig. 2 (F). Then, the cover glass is filled with cloth. (glass fabrics) resin copper foil (manufactured by Mitsubishi Gas Chemicals: trade name CCL-HL8 30LS, glass filler / resin 2 thickness 60, copper pig 22 thickness 1 2 / zm) 2 0 A The two surfaces of the substrate 30 were pressure-bonded by a vacuum pressure-bonding method (Fig. 2 (G)). Here, the vacuum pressure-bonding method is performed at 50 ° C. 30min, and further at 75 ° i20min, and the pressure is 30Kg / cffi2, and the degree of vacuum is <50 〇tor. Carry on. Next, the copper foil 22 on the surface is completely etched to an thickness of 3 // m using an etching solution (manufactured by Mitsubishi Gas Chemical Co., Ltd .: SE-07) (Fig. 2 (H)). A dry film photoresist (NIT-made: trade name NIT-215) was attached to the steel pig 22, a curtain was attached, exposure was performed at 100 mJ / cm2, and development treatment was performed with 08% sodium carbonate, and An etching photoresist 44 having an opening 44a is provided in the via hole forming portion (FIG. 3 (I)). After removing the copper foil 22 in the opening 44a by vaporizing the second copper etchant (Fig. 3 (J)), "the etching resist 44 is peeled off with a sodium hydroxide aqueous solution" to form a uniform cover. Copper foil 22 (Fig. 3 (κ)) »Using a carbon dioxide gas laser irradiation device (Mitsubishi Electric Corporation: Trade name 6 0 5GTX) 'Irradiate the laser pulse twice at each opening 22a of the copper foil 'As a result, a through hole 20a of 60e0 is formed at 20 of the interlayer resin insulating layer (resin) (Fig. 3 (L)).

Page 59 407453

After the electroless clock film 52 is formed on the surface of the substrate 30 by ordinary electroless plating (Fig. 4 (M)), a 10-mm electrolytic copper plating film 56 is further formed by using sulfuric acid steel J steel (Fig. 4 (N )). Qian Attach a dry film photoresist to a copper foil 22 (referred to as "Built-in-Bulk &gt; Product: Product NIT-215"), and then attach a patterned curtain cover (Z name) at a specified position and expose it. After that, the development treatment pattern was performed with 0.8% sodium decomposing sodium and a line / space covering the via hole-forming portion and the circuit-forming portion was provided (1 ine / space): 50/50 / zm of etching resist 54 (No. 4 Figure (〇)) ° After that, “etching with a second copper chloride pattern is performed” and then take 2% NaOH to peel off the photoresist 54 to form a via 60 and a circuit 58 (Figure 4). (P)). Then, the same process is repeated iteratively to complete the 6-layer printed circuit board combining the two sides (Figure 6 (R)). In addition, in the above-mentioned embodiment, the steel foil was attached to the resin beforehand, but the metal foil such as copper foil was attached to the resin after use. Furthermore, although "the copper foil adhered to the resin is used in the first and second modified examples" and the copper foil adhered to the resin containing the glass cloth is used in the third modified example, Various materials can be added to the resin (such as non-woven fabrics). As described above, according to the first embodiment, since the openings for the vias can be formed by using a low-power laser or a small number of short-pulse laser irradiations, the resin for forming the interlayer insulating layer is formed. No side erosion phenomenon will occur ', so the connection reliability of the via hole can be improved.

Page 60 V. Description of the invention (57) [Second embodiment] Hereinafter, a multilayer printed wiring board and a manufacturing method thereof according to a second embodiment of the present invention will be described. As the substrate used in the second embodiment, a resin substrate such as a glass cloth epoxy substrate, a glass cloth bismaleic anhydride imide-triπazine resin substrate, a glass cloth fluororesin substrate, or the like can be used. Copper-plated laminates, copper substrates, metal substrates, ceramic substrates, and the like are attached to the above resin substrates. A conductor circuit is provided on the substrate. The conductor circuit can be formed by an etching process in the case of electroless plating, electrolytic plating, or copper-plated laminate. Next, an insulating resin layer is provided. In the second embodiment, the insulating resin layer is irradiated with laser light to form an opening for a via hole. Therefore, in the above-mentioned insulating resin layer, a material which can be provided with an opening portion by irradiation with laser light is selected. As the material, a thermosetting resin, a thermoplastic resin, or a composite resin as described above can be used. For example, an electroless electro-mineralizing adhesive using a thermosetting resin as a base can be used. As the thermosetting resin, an epoxy resin, a phenol resin, a polyimide resin, or the like can be used. In addition, as for the thermoplastic resin, polyether stele (PES), polypyrene (PSF), polyphenylene (pps), polyphenylene sulfide (PPES), polyphenylene ether (PPE), and polyether Etherimine (pi) and the like. In the second embodiment, the roughened surface of the insulating resin exposed from the metal layer or the metal foil is formed in the following manner. Specifically, 'is that the available acid is contained in the insulating resin layer in advance,

P.61 407453 V. Description of the Invention (Smudge) Dissolved particles such as emulsifiers, so that the particles can form a roughened surface on the surface of the insulating resin layer by the acid. After dissolving the roughened surface in the solvent, a metal layer must be provided next. Λ is formed in this shape. With the above heat-resistant resin particles, cyanamide resin, urea resin, and guanamine resin can be used. The purpose of the hardening month (heat-resistant resin suitable for the future consisting of acid anhydride imide-triazine resin :), Shuangma In addition, in the above-mentioned adhesive for electroless plating, the bean contains田 # &amp; Office &amp; Ύ If necessary, heat-resistant resin particles, fillers, etc., which are hardened, can be used... Machine particles or fibrous materials, the above-mentioned heat-resistant resin particles are used It is preferred to select at least i of the following groups of particles: (1 particle size, heat-resistant resin powder with a particle size of 10 or less; (2) agglomeration of heat-resistant resin powder with an average particle size of 2 # m or less Agglomerated particles; (3) a mixture of a heat-resistant resin powder having an average particle diameter of 2 to 10 / im and a heat-resistant resin powder having an average particle diameter of less than 2; (4) an average particle diameter of 2 to 10; ; 111 heat-resistant resin powder surface with an average particle size of 2 or less Similar particles formed from at least one component of resin powder and inorganic powder; (5) heat-resistant resin with an average particle size of more than 0.8 m but less than 2 ο powder and an average particle size of 0_b 0t 8 kernels A mixture of heat-resistant resin powders; (6) heat-resistant resin powders having an average particle diameter of 0.1 to 1.0 # m β In addition, as the roughened surface of the insulating resin layer in the second embodiment, a so-called RCC (Resin Coated Copper: Resin Coated Copper) is formed of a metal foil formed by a roughened layer. In this case,

Page 62 407453 V. Description of the invention (59) A roughened layer is provided on one side, and an insulating resin layer is provided on the roughened layer to form a metal foil. The roughened layer on the metal surface can be formed by various roughening treatments. The roughening treatment may include, for example, matte treatment, oxidation treatment, redox treatment, blackening-reduction treatment, sulfuric acid-hydrogen peroxide treatment, and use of a second copper complex and an organic acid. The solution is subjected to an etching treatment such as a treatment, a plating treatment using a copper-nickel-phosphorus needle alloy plating, or the like. The metal foil produced by the above method is set on the core substrate and then laminated on the lower-layer conductor circuit. At this time, make the surface of the insulating resin layer and the + lower layer. If the conductor circuits are in contact with each other and the core substrate and the metal foil are heated and compressed, the above-mentioned ones can be integrated. : By removing the above-mentioned metal foil by etching, the roughened surface derived from the roughened layer can be transferred to the surface of the insulating resin layer exposed on the insulating resin layer. As the etchant in the case of a copper foil, a sulfuric acid-hydrogen peroxide aqueous solution, an ammonium persulfate aqueous solution, a second ferric chloride, and the like can be used. The roughened surface formed on the surface of the insulating resin layer or the roughened layer formed on the surface of the copper alloy is preferably a maximum roughness (Rj) of 0, 〇1 and ^^ 5. If the maximum roughness If the seam is less than 0.01, the roughened surface formed on the surface of the insulating resin layer or the roughened surface (person) transferred on the surface of the insulating resin layer can easily reflect the laser light, so it cannot sufficiently The insulating resin layer is removed. In addition, if the maximum roughness exceeds 5 V m, the roughened layer may be removed in a manner that is difficult to etch. In the second embodiment, the roughened surface formed as described above is used.

V. Description of the invention (60) The laser light is irradiated to remove the insulating resin layer and to form the opening portion for the via hole 'Then, the aforementioned opening portion is electroplated to form the via hole. As the above-mentioned laser light, carbon dioxide gas laser light, ultraviolet laser, electronically excited laser, etc. can be used. In particular, carbon dioxide gas laser light is preferable because it can be generated by an inexpensive device. In the second embodiment, in order to increase the close adhesion between the lower conductor circuit and the insulating resin layer, and the close adhesion between the lower conductor circuit and the via hole conductor, the roughening is provided on the surface of the lower conductor circuit. The surface is better. The aforementioned roughened layer can be formed using various roughening processes. As for the above-mentioned roughening treatment, for example, oxidation treatment, redox treatment, blackening-reduction treatment, acid-hydrogen peroxide treatment, treatment using a solution containing a second copper complex and an organic acid, and the like can be mentioned. Etching treatment, electroplating treatment using a copper-recording-scale alloy electron microscope, and the like. In the above-mentioned lower-layer conductor circuit, resin is liable to remain on the roughened surface when openings for vias are opened. However, in the method of the second embodiment, a roughened layer is provided on the surface of the insulating resin layer. Therefore, if the roughened surface is irradiated with laser light, then "there will be no resin remaining on the roughened surface of the underlying conductor circuit", and the insulating resin layer can be removed. Next, a catalyst for electroless plating, such as a P d catalyst, is provided in the via hole, and the via hole is electroplated in the opening to provide a via hole. In addition, a conductor circuit is provided on the surface γ surface of the insulating resin layer. A non-electrolytic plating film is formed on the entire inner wall surface of the opening, and after the entire surface of the resin layer is provided with a plating resist, a conductive circuit is formed by performing galvanic plating, removing the plating resist, and performing etching.

407453 V. Description of Invention (61) Next, a method for manufacturing a multilayer printed wiring board according to the second embodiment will be described with reference to FIGS. 7 to 11. [Preparation of Adhesives for Electroless Plating] (1) 35 parts by weight of a 25% propylene compound of a cresol novolac solid epoxy resin (manufactured by Nippon Kayaku Co., Ltd. with a molecular weight of 2500) and a photosensitive monomer (manufactured by Toa Kosei: Trade name 70 2 7 eve M315) 3.15 parts by weight, defoaming agent (廿 &gt; v) made of S — 6 5) 0 · 5 parts by weight and n _ methyl d-pyrrolidone (N-methylpyrrolidone) (NMP ) 3.6 parts by weight for scramble mixing. (2) 7.2 parts by weight of an average particle diameter of 12 parts by weight of poly-fluorescein (PES), epoxy resin particles (manufactured by Sankayo Kasei Corporation: trade name polymer pole), and 7.2 parts by weight and average After mixing 3.09 parts by weight with a particle size of 0.5 // m, further add 30 parts by weight of NMP, and stir and mix with a beads mill (3) imidazole hardener (Shikoku Kasei Co., Ltd .: Trade name 2E4MZ_CN) 2 parts by weight, photoinitiator (manufactured by Bafang γ 芊: &lt; Erfang Niu Λ 7 1 _ 9 0 7) 2 parts by weight, photosensitizer (manufactured by Benhua Pharmaceutical: DETX-S) 0.2 parts by weight and 1.5 parts by weight of NMρ were stirred and mixed. (4) Mixing the mixtures (1) to (3) to obtain a j-adhesive for electroless plating. ^ [Adjustment of resin filler]

Explanation of the invention (62) Sio2 spherical particles with an average particle diameter of 6 (7 pv7 'CRS11 0 1 -CE' here) The size of the largest particles is in the inner copper pattern described later. 170 parts by weight (under 15era) and 1.5 parts by weight of a leveling agent (manufactured under the brand name-S4) kneaded with 3 rollers (r〇11), and the viscosity of the mixture was adjusted to 23 ± 1. (: 45, 000 to 49,000 (^ 3. (2) Miwa hardener (made by Shikoku Kasei: trade name 2E4MZ_CN) 6.5 parts by weight. (3) the mixture (1) and (2) The resin filler can be prepared by mixing. [Manufacture of printed wiring board] (1) As shown in FIG. 7 (A), in the second embodiment, glass epoxy resin or double epoxy resin having a thickness of 1 mm is used. The mineral copper laminate 30A formed by laminating 18 copper foils 232 on both sides of a substrate 230 made of maleic anhydride imine triazine () resin is used as a starting material. (2) First, in the copper plating As shown in FIG. 7, the laminate 23 0A is drilled with iron holes to perform “electroless plating and electrolytic plating”, and then the copper foil 232 is engraved in accordance with a general pattern and shape according to a general method, and the substrate 230 is engraved. An inner sound (lower conductor circuit) 234 and a through hole 236 are formed on both sides of a thickness of 25 // Ιβ. Now, add 0 ° to the surface of the inner copper pattern 23 4 and the ridge of the through hole 236 &amp; &amp; J ^ $ A question about clothes and inner belts

The roughening layer 238 is placed and manufactured as shown in FIG. 7 (B). The roughening surface 238 of J is used to wash and dry the above substrate, and then use an etching solution.

V. Description of the invention (63) The two surfaces of the substrate are spray-washed on the surface of the inner copper pattern 2 34 and formed between the ridge surface and the inner wall of the through hole 236. This etching solution is a mixture of 10 parts by weight of copper imidazole (11) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride, and 78 parts by weight of ion-exchanged water. (3) Next, a resin layer 2 40 as shown in FIG. 7 (c) is provided between the inner layer steel patterns 234 of the circuit board 230 and within the through holes 236. The resin layer 240 ′ is a resin prepared by applying a resin filler prepared in advance on both sides of the circuit substrate 230 with a roll coater to fill it between the inner copper patterns 234 and the through holes 236. It is formed by hardening by individually applying heat treatment for 1 hour at 100 ° C, 3 hours at 120 ° C, 1 hour at 150 ° C, and 7 hours at 180 ° C. C 4) One side of the substrate obtained by the process (3) is polished with a belt sander. In this polishing, the roughened surface of the inner layer copper pattern 2 34 and the ridge surface of the through-hole 236 were ground using a strip-shaped abrasive paper # 600 (manufactured by Sankyo Chemical Co., Ltd.) to leave no resin filler remaining. Polishing to remove the scars caused by the grinding of the belt sander. The same steps as above are also performed on the other substrates to obtain the circuit substrate 230 as shown in FIG. 7 (C). The circuit substrate 230 'thus obtained is provided with the resin layer 240' between the inner-layer copper patterns 234, and the resin layer 240 is also provided within the through-holes 236. The removal of the roughened surface 238 of the inner layer copper pattern 234 and the roughened surface 2 3 8 of the ridge surface of the through hole 236 is performed by smoothing the resin filler on both sides of the substrate. Resin layer 240 is a roughened side of the inner layer copper pattern 234

The description of the invention on page 67 of (5) of the invention (64) 238a or the through hole 23 6 The roughened surface 2 38a of the side of the ridge portion is closely adhered. In addition, the resin layer 240 is also closely adhered to the roughened surface 238 penetrating the inner wall of the 孑 L 236 With. (5) Further, as shown in FIG. 8 (D), the exposed inner layer copper pattern 234 and the ridges of the through holes 236 are roughened by using the etching treatment of (2) to form a rough depth of 3化 面 242. The roughened surface 242 was subjected to tin instead of plating to provide a Sn layer having a thickness of 0.3 m. Substitute electric ship system: Under the conditions of tin boron fluoride 0.1 im / i, thiourea 10 mol / 1, temperature 50 ° C, and pH = 1.2, the roughened surface 242 is subjected to a Cu-Sn substitution reaction. (Sn layer is not shown). (6) On both sides of the obtained circuit board, a roll coater was used to apply the adhesive for electroless plating. After the adhesive was left on the substrate in a horizontal state for 20 minutes, it was dried at 60 for 30 minutes to form an adhesive layer having a thickness as shown in FIG. 8 (E). (7) Expose both sides of the obtained circuit substrate at 500mJ / cra2 using ultra-high pressure mercury, and heat it at 15 (pc for 5 hours. (8) immerse the substrate to be immersed in chromic acid} minutes, The ring 4 on the surface of the adhesive layer 4 0AL removes the particles of the oxygen oxide tree. By continuing the treatment, it can be formed on the surface of the main layer of the adhesive layer Ketiantong 1 Α Γ 50 as in Section 8. (F) The roughened surface 250a, which is not the same as shown in Figure (F). Then, the obtained substrate is immersed in a neutralizing solution (manufactured by the company) and then washed. (9) Next, as shown in FIG. 9 (G). ^ Jr &amp; [] a ^.,), An electroless copper electro-membrane film having a thickness of 0.6 / ^ is formed on the entire surface of the substrate. V. Description of the invention In the interlayer as shown in (65), (10) set an etching photoresist on the obtained substrate, and etch with an aqueous sulfuric acid and hydrogen peroxide solution, and as shown in FIG. 9 (the hole forming part is set to 50) 〇251a. (11) Irradiated by a short pulse (10- 4 seconds) (2Mitsubishi Electric ML605GTL) on the opening 2 51a, and as shown in Fig. 9 An opening is shown in the contact agent layer 250 as shown in the figure. Furthermore, the surface of the circuit substrate after the roughening treatment is provided with a palladium catalyst, and the catalyst core is attached to the non-electricity. On the surface of the mineral film 251 and on the roughened surface of the via 248 for the vias. C 1 2) The obtained substrate was immersed in an electroless copper electroplating bath under the same conditions as in the i-th implementation {column, and a thickness of 1.6 jt was formed on the entire roughened surface as shown in FIG. 10 (j). / m 的 无 电 铜 铅 膜 252. (13) Next, as shown in FIG. 10 (K), a commercially available photosensitive dry film 254 is attached to the electroless copper plating film 25 2, and a curtain with a printed pattern 255A is mounted thereon. Mask film (255). Next, the substrate was exposed at 100 mJ / cni2, and then subjected to a development treatment with 0.8% sodium acid barrier, and a plating resist 2 54 having a thickness of 15 jtzm as shown in FIG. 10 (L) was established. (14) Next, electrolytic copper plating was performed on the obtained substrate under the same conditions as in the first embodiment to form an electrolytic copper plating film with a thickness of 15 # m 2 5 6 ° (1 5) After stripping and removing 5% KOH, the electroless copper plating film 252 under the plating photoresist 254 was mixed with sulfuric acid and argon peroxide.

Page 69 V. Description of the invention (66) ^ The liquid mixture is subjected to money engraving treatment to be dissolved and removed, and as shown in FIG. 丨 丨 (N), an electroless copper plating film 2 52 and an electrolytic copper plating film 256 are obtained. The conductor circuit 2 58 (including via 260) has a thickness of 18 &quot; m. Furthermore, the substrate was immersed in chromic acid at 80 g / i for 3 minutes at 701 to perform 1 # m etching treatment on the surface of the adhesive layer 250 for electroless plating between conductor circuits 258, thereby The surface palladium catalyst was removed, and a multilayer printed wiring board as shown in Fig. 11 (N) was manufactured. Next, a first modification of the second embodiment will be described with reference to Figs. 2 and 13. The processes (1) and (2) of the first embodiment are performed to produce a core substrate 2 30 having a roughened surface of the lower-layer conductor circuit as shown in FIG. 7 (B). On the other hand, a resin-coated steel foil 2 2 9 as shown in Fig. 12 (a) was also produced. This resin-coated copper foil 2 2 9 is formed on one side of a copper foil 2 3 2 having a thickness of 12 mm by using the etching treatment shown in (2) of the second embodiment to roughen it to form a depth of 3 Roughened layer 23 2a. The roughened surface was coated with epoxy resin 2 2 0 and heated at 60 ° C for 3 hours to be used as a B-stage.

As shown in FIG. 12 (6), 'two pieces of resin-coated copper foil 229 Ampere are applied to both sides of the core substrate 2 30, and a pressure of iokg / cm2 is applied under i5 (pc) to perform pressure integration. A substrate as shown in FIG. 12 (c) is obtained. At this time, the adhesive layer 220 shown in FIG. 12 (A) is brought into contact with the conductor circuit 234 under the core substrate 230, and the bonding The agent layer 220 is made of a resin-coated copper foil epoxy resin. Next, the substrate 230 is applied in synchronization with (10) of the second embodiment.

Chapter 70

The step of processing is to attach a dry film on the surface of copper 232, and perform exposure and development processing with ultraviolet light. To set an etching photoresist, use an aqueous solution composed of sulfuric acid-hydrogen peroxide to form a part of the interstitial hole. The copper foil 232 is removed by etching and an opening 233 is provided as shown in FIG. 13. Thereby, the roughened surface 220a of the shape of the transferred copper roughened layer 232a is made on the surface of the adhesive layer 22 *. On the roughened surface, the same step as in the second embodiment (1) is performed, and the carbon dioxide gas laser light is irradiated to form an opening for the diameter layer hole, and this laminated substrate is used as in the second embodiment. (1 3) ~ (15) to form the electroless plating film and electrolytic plating film under the same conditions, and dissolve and remove the electroless plating film according to the pattern shape, and then the electroless copper plating film and the electrolytic steel can be made. Multilayer brush circuit board with interlayer hole formed by coating. Comparative Example 1 Except that a roughened surface was not provided on the surface of the adhesive layer, and the laser light was directly irradiated, the rest of the steps were the same as in the second embodiment * to prepare a multilayer printed wiring board. Comparative Example 2 A roughened layer was not provided on the surface of the resin-coated copper foil. [Heating test and thermal cycle test] The circuit board obtained in the second embodiment and the modified examples of the second embodiment and the comparative example 1 was subjected to 5000 times of heat at -55 ° C to 125 ° C. Cycle test. After each test, the pore size and resistance to change of the mesoporous portion were measured. In addition, it was confirmed with an optical microscope whether the resin around the opening was swollen.

Page 71 407453 V 'Explanation (68) The results are shown in the table in Figure 56. If the He Hao method of the second embodiment is used, the subordinates are discarded _ Xuezheng μ i, then the surface of the lower-layer conductor circuit at the via hole interface 筮 9% is covered by / sl%% Residual remains. Therefore, according to the second lean embodiment, the phenomenon of peeling between the hole conductors will not occur during thermal cycling, and the circuit and the interposer will have poor performance, so it can be obtained Will produce as many T printed circuit boards. Excellent in connection reliability [Third embodiment] The manufacturing method is to set the interlayer resin, laser light and ④ interlayer resin.

^ The multilayer printed wiring board of the third embodiment and its Hu Ming. The third embodiment is related to a multilayer printed wire method including the following steps: ① a process of forming an interlayer resin insulation layer of a conductor circuit, based on the above-mentioned conductor circuit "insulation layer; ③ a process of providing an opening for a via hole, In the south, the process of setting the vias in the interlayer resin insulation layer to open other conductor circuits containing vias is a process of forming other conductor circuits containing vias in the 4 insulating layers. Before the process described in ②, the process of manufacturing square circuit boards using the second copper complex is used; ② the layer is provided by the irradiation port; the surface of the conductor circuit is roughened with the etching solution of organic acid in the above layer .

According to the multilayer printed wiring board obtained by the same manufacturing method, the surface of the conductor circuit is provided with an interlayer resin insulation layer on the conductor circuit at the same time after being roughened with an etching solution containing a second copper complex and an organic acid. Furthermore, the interlayer resin insulating layer is further formed with a structure having an opening for a via hole and a stripe unevenness on an inner wall of the opening. According to the structure of the third embodiment as described above, since

Page 72 V. Description of the invention (69) The conductor circuit is roughened by the etching solution of two copper complexes and organic acids, so the surface of the conductor circuit can be formed as shown in Figures 14 to 16 Rough surface of complex shapes. This roughened surface has excellent close adhesion to the interlayer resin insulating layer formed thereon. In addition, the roughened surface does not change its shape, that is, it is not flattened, when the laser light is reflected or irradiated with the laser light. Therefore, after the interlayer resin insulating layer is formed on the conductor circuit, the above-mentioned conductor circuit is not flattened even if it is irradiated with laser light, so that an opening for a via can be formed. In addition, the use of the above-mentioned etching solution containing the second copper complex and an organic acid to form the roughening: surface 'rarely causes the resin to protrude even when opening is performed by using laser light. Therefore, there is no phenomenon that the connection with the interlayer pores is damaged due to the expansion of the remaining resin during heating. Furthermore, since the reflection of the laser light becomes easier, the incident light of the laser light and the reflected light can be interfered with each other. Therefore, it is also easy to form a stripe-like unevenness on the inner wall of the opening of the via hole. After the stripe-like unevenness is formed on the inner wall of the opening, since the contact surface of the metal constituting the via hole has an overall thickening effect, the connection reliability of the via hole can be improved.

Therefore, 'the multilayer printed wiring board of the third embodiment is excellent in close adhesion between a conductor circuit including a via hole portion and an interlayer resin insulating layer' at the same time as the conductor circuit and formed thereon The interposer hole (conductor circuit) is also very good in terms of tight adhesion. S FIG. 14 is a schematic plan view of a roughened surface of a conductor circuit formed by the roughening processing method of the third embodiment, and FIG. 15 is shown in FIG. 14

0

Page 73 V. Description of the invention (70) --- A vertical cross-sectional view taken along line A-A, and FIG. 16 is a vertical cross-sectional view of other parts of the surface of the conductor circuit shown in FIG. 14. In the drawing, 3 2 1 is a residual portion (hereinafter referred to as an anchor portion) that is not etched on the surface portion, and 322 is a recessed portion 323 is a ridge formed between the recessed portion 322 and the recessed portion 322. g If the roughening method of the third embodiment is used, a roughened surface having a shape as shown in Figs. 14 to 1b can be formed. That is, most of the anchor-shaped portion 321 has a portion having an upper width larger than a lower width. In addition, in the third embodiment, a stripe-like unevenness as shown in Fig. 20 is formed on the inner wall of the opening for the via hole.

The depth in the direction of the wall surface of the unevenness is preferably 0.05 mm, and the interval between the unevenness is preferably 20 mm. Too large or too small may cause poor adhesion to the metal constituting the vias.

Also, as shown in Fig. 21, a roughened surface having an average degree of roughness may be further formed on the surface of the striped unevenness. In this way, 1 can increase the drying effect and make the adhesion with the interlayer holes more excellent. Β If the interlayer holes are formed on a conductor circuit with a roughened surface as described above, then the anchor shape on the roughened surface The portion 321 and the like have a thickening effect, and as a result, a via hole having excellent adhesion to the underlying conductor circuit can be formed. 4. If the via hole is formed by electroplating, the electric key coating on the roughened surface is good, so it can form an electric money layer with the recess 3 2 2 and the anchor 3 2 1 and so on. Forms via holes with better adhesion to the underlying conductor circuit. In addition, in the case of opening with laser light, because there is very little

Page 74 V. Description of the invention (71) The roughened structure of the resin bump is very excellent in the reliability of the connection of the via hole. Next, a method for roughening the surface of the conductor circuit using an etching solution containing a second steel complex and an organic acid will be described. The second copper complex is not particularly limited, but a second copper complex using azoles is preferred. The second steel complex of the azole is used as an oxidizing agent such as copper oxide. As for azoles, diazole, triazole and tetrazole are preferred. Among them is Mic. Sit, 2-methylimidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, and 2-undecylimidazole are preferred. Above. The addition amount of the second copper complex is preferably 15% by weight. Within the above-mentioned addition amount of the range Y, the second copper complex is excellent in solubility and stability. In addition, in order to dissolve copper oxide ', an organic acid may be blended in the second copper complex to be used. When the second copper complex of azoles is used, the organic acid is selected from acetic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, butenoic acid, oxalic acid, malonic acid, Succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid ', propionic acid, malic acid, and amino acid are at least one component in the group. The content of the organic acid is preferably 0.03 wt%. This maintains the solubility of the oxidized copper and ensures dissolution stability. In the above-mentioned etching solution ', in order to assist the dissolution of copper and the oxidation of azoles, fluoride ions, chloride ions, bromide ions and the like can be added to the etching solution. The halogen ion can be supplied using hydrochloric acid, sodium chloride, or the like. The addition amount of the halogen ion is preferably 0.01 to 20% by weight. So that layers can be formed

Page 75 407453 V. Description of the invention (72) * -------- A roughened surface with excellent adhesion between resin insulation layers. The above-mentioned engraving solution is prepared by dissolving the above-mentioned second steel complex and the organic ions that are used when necessary, such as cerium ions, sulfonium ions, and other ions, in water. In addition, a commercially available money engraving solution can also be used. For example, the company's product, trade name 4 "... rice engraving agent ... engraving solution can be used. The roughening treatment liquid for the conductor circuit is sprayed and washed on the conductor circuit using the etching solution Surface &quot; hereinafter referred to as two: f or 疋 is performed by the above J and the above silver engraving solution ... hereinafter referred to as the foaming method under the conditions of bubbing.) Use electricity :: treatment to make oxygen coexist In the etching solution, a chemical reaction shown in the following formula (&quot; or. (2)) is performed for the remainder.

Cu + Cu (II) An-2Cu (I) An / 2 ... (1)

I

2Cu (I) An / 2 + n / 4 〇2 + nAH ^ 2Cu (II) An + n / 2 H2 0 ... (2) (where A is a dissertation agent (used as a coupling agent) 'η As the coordination number is as shown in the above chemical formula, the produced first steel complex is dissolved 'reusing oxygen to oxidize to a second copper complex' by the action of acid to facilitate the oxidation of copper. The degree to be etched by the above etching solution is preferably such that the depth of the etching portion can reach 10 mm. If the degree of money engraving exceeds the above range, the roughened surface and the medium will be formed Contact between hole conductors

V. Description of the invention (73) Bad phenomenon. After roughening the surface of the conductor circuit by the above method, an interlayer resin insulating layer can be formed on the conductor circuit. The interlayer resin insulating layer 'formed in the third embodiment is preferably formed of a thermosetting resin, a thermoplastic resin, or a composite resin as described above. As the above thermosetting resin, for example, a polyolefin resin, an epoxy resin, a polyimide resin, a phenol resin, and a bismaleic anhydride imine selected from a thermosetting type or a thermoplastic type can be used. -Triazine resin is preferably at least one component. As for the above-mentioned thermoplastic resins, polymethylpentene (PMP), polystyrene (PS), polyether stele (PES), polyphenyleneether (PPF), and Engineering plastics such as polyphenylene terephthalate (PPS) are preferred. As the interlayer resin insulating layer in the third embodiment, it is preferable to use the above-mentioned thermosetting type or thermoplastic type polyolefin resin. Examples of the above-mentioned thermosetting or thermoplastic polyolefin resins include polyethylene, polypropylene, polyisobutylene, polybutadiene, polyisoprene, and resin copolymers of the foregoing and the like. . As the commercially available product of the above-mentioned polyolefin-based resin, for example, the product name of Sumitomo Corporation is: 1592. In addition, for a commercially available product of a thermoplastic polyolefin resin having a melting point of 200 or more, for example, a trade name manufactured by Mitsui Petrochemical Co., Ltd .: TPX (melting point 24 (rc) and Idemitsu Petrochemical)

Page 77 407453 V. Description of the invention (74) Trade name of Xue Industry Co., Ltd .: SPS (melting point 270 ° C), etc. The interlayer resin insulating layer can be formed by laminating a thin film resin by applying an unhardened liquid while applying heat to the film. After that, the interlayer resin insulating layer is irradiated with laser light to provide an opening for a via hole. At this time, in terms of the laser light used, for example, a carbon dioxide gas (C02) laser, an ultraviolet laser, an electron-excitation laser, etc., and a carbon dioxide gas laser with a short pulse is preferred. Because the short pulse of carbonic acid gas laser can reduce the resin residue in the mouth, and the damage to the resin around the opening (damage) is also very small. The pulse interval of the carbonic acid gas laser is more preferably from 14 to 10 and 8 seconds. In addition, the laser irradiation time for forming an opening is preferably from 0 to 5 and 0 seconds. In addition, it is preferable to perform processing with an emission amount of 10 times under the conditions of a beam diameter of 20 to 20 colors and a multi-mode (including a so-called top hat mode). This is because in multi-mode, the energy irradiated by the laser light has a dense energy density of one, so it will not get a large opening, but can form a near-real circle. The opening for the interstitial hole with less ridges of grease. In addition, in order to make the shape of the spot of the laser light close to the shape ′, the laser light passes through a true circular hole called a mask, and the diameter is preferably about 0.1 to 2 mm. When the perforation is performed with carbon dioxide gas laser light, it is better to perform a residue removal treatment. The above-mentioned decrustation treatment can be performed using an oxidizing agent composed of water such as chromic acid, permanganate, and the like. Alternatively, an oxygen plasma, CF, and oxygen can also be used.

407453 V. Description of invention (75) The mixed plasma or corona discharge is used for processing. In addition, the effect of surface modification can be achieved by using a low-pressure mercury lamp for ultraviolet irradiation. After that, an electroless ore treatment or an energized clock treatment, as described later, can be used to form an upper conductor circuit including a via hole on the above conductor circuit. An example of a method for manufacturing a multilayer printed wiring board according to the third embodiment will be described below. (1) First, a circuit substrate having a lower-layer conductor circuit is fabricated under the surface of a resin substrate. As the resin substrate, a resin substrate having inorganic fibers is preferred. Specific examples thereof include a glass cloth epoxy substrate, a glass cloth polyimide substrate, a glass cloth bismaleic anhydride imine-triazine resin substrate, and a glass cloth fluororesin substrate. It is also possible to use a copper-plated laminate in which copper foil is attached to both surfaces of the resin substrate. Usually, a through-hole is provided with a drill on the resin substrate, and a through-hole is formed by applying electroless plating to a wall surface of the through-hole and a copper foil surface. Electroless plating is preferably steel plating. Furthermore, in order to provide a thick coating of copper foil, it is also possible to perform electroplating. The electroplating is preferably steel plating. After that, the inner wall of the through hole may be roughened, and then the through hole may be filled with a resin solder paste or the like, and a conductive layer covering the surface thereof may be formed by electroless plating or current plating. After the above process, the photolithography can be used on the beta pattern of copper that has been formed on the entire surface of the substrate.

Page 79 407453 Description of the invention (76) Method to form an etched photoresist 'and then forming an underlying conductor circuit by performing etching. (2) Secondly, a roughening process is performed on the lower conductor circuit. That is, an etching solution containing a second steel complex and an organic acid is used to form a roughened surface on the lower conductor circuit by a spray washing method or a foaming method. (3) Then, 'on both surfaces of the circuit board having the lower-layer conductor circuit prepared in the above (2), the above-mentioned interlayer resin insulating layer made of a polyolefin resin or the like is coated with an unhardened liquid or a film The resin is laminated by hot pressing. On the formed interlayer resin insulation layer,

The layer-to-layer conductor circuits are electrically connected, so laser light is used to illuminate the openings for the vias. P ^) Secondly, the surface of the interlayer resin insulating layer can be roughened by subjecting it to an electric treatment or an acid treatment. '' In the plasma treatment, in order to ensure the close adhesion between the conductor circuit and the interlayer resin insulation layer used as the upper layer, Ni, Ti, Pd, etc. can also have excellent adhesion to the interlayer resin insulation layer. Formed for the middle layer. The intermediate layer composed of the above-mentioned metal is shaped by physical vapor deposition (pvD) using sputtering or the like. The thickness of the intermediate layer is preferably 0.1 to 2.0 / ζιη. (5) Deplating is performed on the substrate obtained through the process of (4) above. . Ding Wuding Electroless ore is most suitable for steel plating. The non-electrolytic thickness is preferably 0.1 to 5 / zm. The film thickness in the above range is to prevent the damage of its function as a conductive electroplated conductive layer during the step of the air inlet film.

Page 80 407453 V. Description of the invention (77) It can be removed by etching. In addition, this electroless plating process is not an essential step, so it can be omitted. (6) A plating photoresist is formed on the electroless plated film formed in the above (5). This shovel photoresist is formed by laminating a photosensitive dry film and then performing an exposure and development process. (7) Next, a thick coating of a non-electrolytic plated film or the like is performed on the conductor circuit by conducting electroplating. The thickness of the electroplating is preferably 5 ~ 30 # m. At this time, the openings for vias can also be charged into the via structure by using electroplating. (8) After forming the electroplated film, the electroplated photoresist is peeled off, and the electroless plated film existing under the key photoresist and the intermediate layer are removed by etching to form a separate conductor circuit. The above electroplating is preferably copper plating. In terms of rice cooking solution, for example, an aqueous solution of sulfuric acid-hydrogen peroxide, an aqueous solution of persulfate such as persulfate, sodium persulfate, and potassium persulfate, an aqueous solution of ferric chloride, a gasified second copper solution, and hydrochloric acid , Nitric acid and hot dilute sulfuric acid. It is also possible to use the above-mentioned etching solution containing the second copper complex and an organic acid to perform etching between conductor circuits while forming a roughened surface. (9) Afterwards, the same step as in the above (2), using an etching solution containing a second copper complex and an organic acid, to form a roughened surface on the upper conductor circuit by a spray washing method or a foaming method "(10 ) Further, repeatedly operate the processes of (3) to (9) above to set the upper-layer upper-layer conductor circuit, and then, for example, 6 layers and 2 I circles with 3 layers on one side can be obtained.

Page 81 407453 V. Description of the invention (78) &quot; Multilayer printed wiring board. Hereinafter, a method for manufacturing a multilayer printed wiring board according to the third embodiment will be described with reference to the drawings. C 1) is formed by laminating 1 8 # ni copper foil 332 on both sides of a substrate 33 with a thickness of 1 mm and made of glass epoxy resin or bis (maleic anhydride imine diazine) resin. A steel-clad laminate is used as a starting material (see Fig. Lj (A)). First, “drill the copper-clad laminate with a drill bit, and then form an electroplated photoresist, and then apply electroless copper plating to the substrate to form a through-hole 33 6. Furthermore, according to the general method, the copper foil is patterned and shaped. Etching is performed, and an inner layer copper pattern (lower conductor circuit) 334 is formed on both surfaces of the substrate. (2) After the substrate on which the lower-layer conductor circuit 334 has been formed is washed and dried, the substrate surface of the lower-layer conductor circuit 334 and the ridge surface of the through-hole 3 36 are sprayed on the two surfaces of the substrate with a shower head using an etchant. The inner wall is engraved with money to form a roughened surface 3 38 on the entire surface of the lower-layer conductor circuit 334 (see FIG. 17 (B)). This etching solution is a mixture of 10 parts by weight of copper (II) imidazole complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium vaporization, and 78 parts by weight of ion-exchanged water.

(3) A resin filler 3 4 〇 containing epoxy resin as a main component is coated on both sides of the substrate by a printer to fill the filler between the lower conductor circuits 3 34 or the through-holes 336. Then, heating and drying β is performed, that is, by this process, the resin filler 340 can be filled between the lower conductor circuits 334 or the through holes 336 (refer to FIG. 17 (c)) S. (4) The surface of the substrate that has been processed by (3) above is used by

Page 82 V. Description of the invention (79)-Grinding with a belt sander of a belt-shaped abrasive paper (manufactured by Sankyo Ricoh Chemical Co., Ltd.). In this polishing, the surface of the lower conductor circuit 334 and the ridge surface of the through hole 336 are polished. Polish until the resin filler 34 (3) does not remain, and then perform polishing to remove the flaws caused by the polishing of the belt sander. The other substrates are also polished as described above. Then, the filled Zhiyue 1 Filler 3 4 0 Heat hardened (refer to Figure 17 (D)). (5) Secondly, use "2" on both sides of the substrate that has been processed in (4) above as used in (2) above. The coin etching solution is spray-washed by a nozzle, and a rough surface is formed on the entire surface of the lower-layer conductor circuit 334 by etching the surface of the lower-layer conductor circuit 334 and the surface of the ridge of the through-hole 33 6 'once flattened. Surface 342 (refer to FIG. 18 (A &gt;). Thereafter, the roughened surface 342 is tin-plated, and an Sn layer having a thickness of 0.3 is provided on the surface. However, the Sn layer is not shown. (6 ) Next, on both sides of the substrate processed by the above process, a thickness of 50 / zm heat-curable polyresin-based resin sheet (manufactured by Sumitomo 3M Co., Ltd .: 1592)-a layer that is heated and pressurized at a pressure of 10 kg / cm2 while heating to 50 to 180 ° C Press to provide an interlayer resin insulating layer 3 50 (refer to FIG. 18 (B)) made of a polyolefin resin. (7) Next, use a C02 gas laser with a wavelength of 10. 4 / zro, and Under the conditions of a beam diameter of 5mm, a top hat mode, a pulse interval of 50 // seconds, a diameter of the curtain cover of 0.5mm, and three times of emission, etc., a diameter of 80 Am was set on the interlayer resin insulation layer 350 made of a polyolefin resin. Opening 348 for the via of the interposer (refer to FIG. 18 (C)). After that, the residue is removed by using an oxygen plasma.

Page 83 V. Description of the invention (80) (8) Next, use SV-4540 manufactured by Japan Vacuum Co., Ltd. to perform an electric glaze treatment to roughen the surface of the interlayer resin insulating layer 3 50 (see FIG. 18 (D )). In this case, argon of inert gas can be used at 200W power, 0.6 Pa pressure, and 70 temperature. Under the condition of 0, plasma treatment was performed for 2 minutes. (9) Secondly, after using the same device to exchange the internal argon gas, the pressure was 0.6 Pa and the temperature was 80. 0. The sputtering of Ni to the target is performed under the conditions of 200 W of power and 5 minutes of time, and a Ni metal layer 351 is formed on the surface of the interlayer resin insulating layer 350. At this time, the thickness of the Ni metal layer 351 formed was 0.1 V m. Further, a copper metal layer 352 having a thickness of 0.1 to 10 m was formed on the Ni metal layer 3 5 1: under the same conditions using sputtering. (10) Furthermore, on the substrate having the metal layer 351 and the intermediate layer 352 formed in (9), electroless plating under the conditions described in (1) above is performed to form a thickness of 0.7 · m Electroless plated film 353 (see FIG. 19 (A)). In addition, since FIG. 19 (B), since the Ni metal layer 351, the intermediate metal layer 352, and the electroless plated film 353 are difficult to be clearly described individually, the three layers are combined into one layer and described. Marked with 3 5 2 symbol. (11) A commercially-available photosensitive dry film is attached to both sides of the substrate after the above-mentioned treatment is completed, a photomask film is mounted, exposed at 100 mJ / cm2, and then 0.8% carbonic acid is used. Sodium is developed to form a pattern of a plated photoresist 354 with a thickness of 15 // m (refer to FIG. 19 (B) (1 2). Then, energization is performed under the same conditions as in the first embodiment.

Page 84 V. Description of the invention (81) Electroplating to form an electroplated film 356 with a thickness of 15 # π. In addition, with this energized plating film 356, a thick coating used as a part of the conductor circuit 358 and a plating fill used as a part of the via 360 in a process described later can be performed. (1 3) Next, an electroless nickel bath immersed in an aqueous solution (90 ° C) of nickel chloride (30 g / 1), sodium hypophosphite (10 g / 1), and sodium citrate (10 gA) Medium 'and a nickel film 357 having a thickness of .2 / ζιη is formed on the current-coated copper plating film (see FIG. 19 (C)). (14) Then, after removing the plating photoresist 35 4 at 5% KOH, the Ni metal layer 351, the intermediate metal layer 3 5 2 and the electroless plating film 3 5 existing under the plating photoresist 3 54 are removed. (3) The mixed solution of nitric acid, sulfuric acid and hydrogen peroxide is used to dissolve and remove the coins, and a conductive circuit 358 (including via 360) is formed with a thickness of 16 # π, which is composed of a conductive copper plating film 356 and the like. Figure 19 (D)). (15) After that, although not shown in the drawings, the single-sided, three-layer multilayering is performed by the processes of (5) to (i4) repeatedly. After that, after the formation of the solder resist layer with the openings, the formation of the nickel plating film and the gold plating film ', the solder bumps are formed again, and a multilayer printed wiring board having solder bumps can be obtained.

[Heating test and thermal cycle test] The obtained multilayer printed wiring board was subjected to a heat treatment test at 128 ° C for 48 hours and a heat cycle test at -55 ° C to 125 ° C. Then, after each test, the peeling rate between the interlayer resin insulating layer and the underlying conductor circuit and the resistance change rate of the via hole portion were measured. the result

5. Description of the invention (82) As shown in the table on the 57th circle. Ϊ V) Explained with (3f, Example, and the first modification. The condition 'that is, except that the foaming method is used in the lower layer :: J, and the following steps are used except: The upper layer is formed on the surface: Roughen the layer by brushing the circuit board, and make a multilayer printing and thermal cycle test based on the same result. The results are as follows; == 2 heating for the heating test example) 7 (1 = ' #First immerse the conductor circuit in the #etching solution used in the third embodiment, and then use hair / packaging to order the roughening treatment of increasing and decreasing. (Comparative Example 3) Between (2) and (5 In the manufacturing process, Cu_Ni_p plating method is used, and the following conditions are used, except that a roughened layer composed of a Cu-Ni-P alloy is formed on the surface of the lower-layer conductor circuit 334, and the other steps are the same as those in the third embodiment described above. Then, a multilayer printed wiring board was manufactured, and a heating test and a thermal cycle test were performed on the obtained multilayer printed wiring board. The results are shown in the table in FIG. 57. When the roughened layer is formed, the substrate is firstly formed. After degreasing with alkali, soft etching is performed, and then a catalyst composed of palladium chloride and organic acid is used. The solution is treated, and then the Pd catalyst is given and the catalyst is activated c. Next, electroless plating is performed on the substrate to form a roughened layer made of Cu_Ni-p alloy on the entire surface of the conductor circuit β The electroless shovel is made of copper acid bowl (3, 2x10-2m00l / l), nickel sulfate (2.4 × 10-3m00l / 1), and citric acid (5.2x1 0-2m). 〇l / 1), sodium hypophosphite

Page 86 5 'Description of the invention (83) --- (2. 7 X 10-1 mol / l), boric acid (5. 〇χ 1〇_lm〇1 / 1) and interfacial active steeping agent (Nissei Chemical Industrial Corporation, surf; [n〇i465) (i. 0g / i) and other aqueous solutions of pH = 9 electroless plating bath. (Comparative Example 4) The blackening-reduction treatment method was used in the processes of (2) and (5), and the following conditions were used, except that the roughening layer was formed on the surface of the conductor circuit, and the rest of the steps were performed in the third embodiment described above. The examples are the same, a multilayer printed wiring board is manufactured, and a heating test and a thermal cycle test are performed on the obtained multilayer printed wiring board. The results are shown in the table in Figure 5-7. For roughening, NaOH (10gn),

Aqueous solutions of NaCl〇2 (40 g / l) and Na3po4 (6 g / i) were used as oxidized oxidized black bath), and aqueous solutions containing NaOH (10 g / l) and NaBH4 (6 g / l) were used as The reduction bath is subjected to a redox treatment to form a roughened surface with a depth of 3 Am. (Comparative Example 5) In the processes of (2) and (5), except for forming a roughened layer on the surface of a conductor circuit by a soft etching method using a mixed aqueous solution of hydrogen peroxide and sulfuric acid as an etching solution, the rest The steps are the same as in the third embodiment described above, a multilayer printed wiring board is manufactured, and a heating test and a thermal cycle test are performed on the obtained multilayer printed wiring board. The results are shown in Figure 5-7. (Comparative Example 6) In the process of (2) and (5), the friction method is used, and the conditions are used, that is, the steps other than the formation of a roughened layer on the surface of a conductor circuit are used.

Page 87 V. Description of the invention (84) The steps are the same as in the third embodiment described above, 'a multilayer printed wiring board is manufactured' and a heating test and a thermal cycle test are performed on the obtained multilayer printed wiring board. The results are shown in the table in Figure 57. … When performing the roughening treatment ', the alumina abrasive (average particle size) is formed into a roughened surface with a depth of 21 # ^ at a pressure of 1 kg / mm2. ΛΛ

It is obvious from the results in the above table that even after the multilayer printed wiring board of the third embodiment is subjected to a heating test and a thermal cycle test, the change rate of the impedance between the conductor circuit and the via of the via is still small. It was observed that there was peeling between the conductor circuit and the interlayer resin insulation layer. In comparison, the comparatively large number of multilayer printed wiring boards had a large rate of change in impedance, and peeling also occurred after the test. According to the above description, if the multilayer printed wiring board manufacturing method according to the third embodiment is used, a laser light can be used to provide an opening for a via hole in the interlayer resin insulation layer, and the conductor circuit and the A multilayer printed wiring board having high adhesion between the interlayer resin insulating layers thereon, and also increasing the adhesion between the conductor circuit and the via hole formed on the conductor circuit.

'The multilayer printed green tower board of the third embodiment has excellent adhesion between the conductor circuit including the layered hole portion and the interlayer resin insulation layer, and the conductor circuit and the intermediate circuit formed on the conductor circuit. The adhesion is also very good β [Fourth Embodiment] A circuit board and the following are described with reference to drawings for a method for manufacturing a multilayer printed wire according to a fourth embodiment of the present invention.

Page 88 V. Description of the invention (85) First, the structure of the multilayer printed wiring board of the fourth embodiment will be described with reference to FIGS. 27 and 28. Figure 27 shows a cross-section, diagram of a multilayer printed wiring board before IC chip mounting, and Figure 28 shows a 1C chip 90 'mounted on the multilayer printed wiring board 10 in Figure 27. The circuit board is mounted on a dot matrix board (dotbard) 94. In the printed circuit board 10 shown in Fig. 27, through-holes 36 are formed in the core substrate 30, and conductor circuits 34 are formed on both sides of the core substrate 30. An interlayer resin insulating layer 50 is formed on the core substrate 30 above the via hole and the lower side of the conductor circuit 58. On the lower interlayer resin insulating layer 50, an upper interlayer resin insulating layer 150 having a via hole 160 and a conductor circuit Kg formed thereon is arranged. 2. On the upper side of the multilayer printed circuit board as shown in FIG. 28, solder is provided at the opening 71 u of the resistance 70, and a ridge 9 2 1 solder bump for connecting the IC chip 9 0 is provided. Block 7 6 U. A solder bump 76D for connecting the ridge 96 of the point IV board 94 is provided at the opening 71D on the lower surface side. The solder bump 76U is connected to the through-hole 36 through a via hole 60 formed in the interlayer resin insulating layer 150 and a via hole 60 formed in the interlayer resin insulating layer 50. On the other hand, the fresh tin bump 76 D is connected to the through-hole 36 through the via hole 160 formed in the interlayer resin insulating layer 丨 50 and the via hole 60 formed in the interlayer resin insulating layer 50. . The via hole 60 is formed by penetrating through-holes 48 in the interlayer resin insulating layer 50 and depositing an electroless plated film 52 and an electrolytic plated film 56 on the through-holes 48. In the fourth embodiment, since the through hole 48 is made of carbonic acid gas,

407453

5. Description of the invention (86) The laser is formed through the laser, so it can form a fine diameter (60 / im). Furthermore, in the case of laser penetration, the stripe-shaped unevenness is formed on the side wall of the through-hole 48 by the interference of the laser as described later, so that the electroless forged film 52 can be made denser. Dryness increases the reliability of the vias. On the other hand, the solder bumps 76ϋ and 76D are the conductor circuits 158 and the vias 160 under the openings 71U and 71D through which the solder resist 70 passes through the nickel electric clock layer 72 and the gold plating layer 74. Provisioning. Opening of solder resist 70, ηυ,

Ή The D series is worn by laser. That is, in the fourth embodiment, since a laser is used to pass through the opening at the solder resist 70, a variety of materials having excellent electrical characteristics when used as a corner solder resist can be used without being limited to photosensitivity. Resin. In addition, in the case of laser penetrating, the stripe-like irregularities are formed on the side walls of the through holes (openings) 7 1 ϋ and 7 1D by laser interference as described later, so that the nickel plating layer can be formed. 72 is more tightly adhered to improve the reliability of the solder bumps 76ϋ and 76D. Hereinafter, the multilayer printed wiring board and its manufacturing method according to the fourth embodiment will be described with reference to the drawings. Here, the schematic structure of an acid-breaking gas laser device having a through-hole in an interlayer resin insulating layer and a solder resist is described with reference to FIG. 34. FIG. 34 shows a schematic configuration of a laser device for penetrating through-holes in a multilayer printing line in the fourth embodiment. With this laser device, Mitsubishi Electric's ML505GT can be used. In addition, in the case of the c02 laser transmitter 180, when the through-hole (60 v ^) 48 of the interlayer resin insulation layer is formed and when the IC chip connection on the upper side of the solder resist is formed, the penetration is used.

Page 90 407453 V. Description of the invention (87) The hole (133jizm) 71U was the ML50 03D using Mitsubishi electric mechanism, and it was in place. The mother board on the underside of the Jin · Tin photoresistor had two holes (650 / ini) 71D uses Mitsubishi Electric's ML5 0 03D2. The light emitted from the laser oscillator 1 80 is incident on the electromagnetic cover (not to be 31 ¥ 311〇1163 (1) 170) through a transfer mask 1 82 to make the focus on the substrate more vivid. The electromagnetic shield 170 is composed of an electromagnetic mirror 174X that scans laser light in the other direction and an electromagnetic mirror 174Y that scans laser light in the Y direction. The two mirrors 174X and 174Y are used. The motors 172 X and 172Y are used for control. The motors 172 X and 1 7 2 Y can be adjusted at the same time in response to a + control command issued by a control device (not shown). The factory adjusts the angles of the mirrors 174X and 174Y, and The inspection signal from the built-in encoder j (encoder) can be sent to the calculation side. The laser light is scanned through the electromagnetic mirrors 174X and 174Y in the X-γ direction and passed through the f-Θ lens 176 as described below. Openings (via holes) 48 for via holes are formed in the interlayer resin insulating layer of the substrate 30. Similarly, openings (through holes) for solder bumps 71U, 71D are also formed in the solder resist 70. The base plate 30 is mounted on a χ-γ table (XY table) that can be moved in the χ_γ direction. 1 9 0. "Next, the manufacturing method of the multilayer printed wiring board will be described. Here, in the manufacturing method of the multilayer printed circuit board of the fourth embodiment, A. Electroless plating adhesive, B Interlayer resin insulating agent, c. Resin filler, D. Solder photoresist composition will be described. A. Raw material composition for preparing adhesive for electroless plating (adhesive for upper layer)

V. Description of the invention (88) [Resin composition ①] is a resin in which a 25% propylene compound of a cresol novolac solid epoxy resin (molecular weight 2500 manufactured by Nippon Kayaku Co., Ltd.) is dissolved at a concentration of 80% by weight. 3 parts by weight of liquid, photosensitive monomers ('7 t? Yy ^ made by Toa Kosei ^ M 3 1 5) 3 · 1 5 parts by weight, defoamers (made by 廿 yy ^ 3, S — 6 5 ) 0. 5 parts by weight and NMP3.6 parts by weight. If necessary, it can correspond to polyvalent propylene monomer (R604 made by Benwa Pharmaceutical Co., Ltd.) mixed with photosensitive monomers. [Resin composition ②] Polyether 1 (PES) 1 2 parts by weight, epoxy resin particles (Sanyo Chemically produced, polymer electrode (polymer polymer) with an average particle size of I _ 〇 m m 7.2 weight part and an average particle size of _ 5 3. 09 weight part after mixing, and then further add NMP30 weight part , And use a particle mill (beads mi 11) to get rid of the mixture. [Hardener composition ③] 2 parts by weight of Kosho hardener (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ_CN), photoinitiator, by Koji Fangiu 2 7 1-907) Made by Nippon Kayaku, DETX_S) 〇, 2 parts by weight and NMp 1.5 parts by weight. B. Raw material composition for preparing interlayer resin insulator (adhesive for lower layer) [Resin composition ①] ^ 25% propylene of cresol novolac solid epoxy resin (made by Nippon Kayaku, molecular weight 2500) The compound is dissolved at a concentration of 80% by weight in 跗 "in page 92 0

_ 407453 V. Description of the invention (89) 35 parts by weight of the resin solution, photosensitive monomers (manufactured by Toa Synthetic, 7 t? Π eve and m3 1 5) 4 parts by weight, defoaming agent (廿 V / 文3 system, S -65) 0.5 parts by weight and NMP3.6 parts by weight. [Resin Composition ②] After mixing polyether fluorene (PES) 1 2 parts by weight and epoxy resin particles (manufactured by Sanyo Kasei, polymer pole) with an average particle diameter of 0.5 1 4. 49 parts by weight , Further adding NMP30 weight part, and mixing with a particle mill to obtain. [Hardener composition ③] 2 parts by weight of imidazole hardener (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN), photoinitiator (manufactured by Shanghai Yifang Fangyi Fengyi Co., Ltd., and 7 2-907) Photosensitizer (DETX-S, manufactured by Nippon Kayaku Co., Ltd.) 0.2 parts by weight and 1.5 parts by weight of NMP. C. Raw material composition for resin filler preparation The same composition as in the second example was used. D. Soldering and tin photoresist composition is an oligomer that imparts sensitivity to 50% cresol novolac solid epoxy resin (manufactured by Benhwa Pharmaceutical Co., Ltd.) which is dissolved in DMDG at 60% by weight. (〇1 i gomer) (molecular weight 4000) 46.67 g, double weight A type epoxy resin (80% by weight) dissolved in methyl ethyl ketone (Oilization &gt; Koki, EPCOAT1001) 15.0 grams, 1.6 grams of imidazole hardener (Shikoku Kasei Co., Ltd., 2E4MZ-CN), polyvalent propylene monomer of photosensitive monomer (manufactured by Benhua Pharmaceutical Co., Ltd., R6 04), 3 grams, polyvalent propylene of the same type

P.93 Fifth 'Invention description (90)' Women's monomers (produced by Kyoeisha Chemical Co., Ltd., DPE6A) 1 · 5 g and dispersing defoamers (L &gt; y ^ 3 company, S -65) 0. Π Grams were mixed, and 2 g of benzophenone (manufactured by Kanto Chemical) as a photoinitiator and 0.2 g of mirenone (manufactured by Kanto Chemical) as a photosensitizer were further added to the mixture. OPa. S solder resist composition adjusted at 25 t: In addition, the 'viscosity measurement uses a B-type viscometer (Tokyo meter, DVL-B type)' at 60 rpm using a rotor (rotor) No. 4, and at 6 rpm using a rotor (r 〇t〇r) No. 4 〇 Next, the manufacturing system of the multilayer printed wiring board of the fourth embodiment will be described with reference to FIGS. 22 to 27. In this fourth embodiment, the multilayer printed wiring board is formed by a semi-additive process. (1) The two surfaces of the substrate 30 having a thickness of 0.8raro as shown in FIG. 22 (A) and made of glass epoxy resin or BT (bismaleic anhydride imine triazine) resin are layered on both surfaces. A copper-clad laminate 30A formed by pressing 12 # πι steel foil 32 was used as a starting material. First, the copper plated laminate 30a is drilled with a drill bit, and then subjected to electroless plating treatment, and the through-hole 36 and the conductor circuit 34 are formed by etching according to the pattern shape to form as shown in FIG. 22 (B). The mold is shown in FIG. (^) The substrate 30 having the conductor circuit 34 and the through hole 36 formed thereon

And dried 'by using NaOHdOg / i), NaC102 (40 g / 1), Na3po4 (6 g / i) on an oxidation bath (blackening bath), and NaOHdOg / i on a reduction bath) , NaBH4 (6g / 1) oxidation-reduction treatment, in

Page 94 407453

% Body) The surface of Dianguang 4 and the through-hole 36 is roughened. (Refer to Fig. 22 (3). The raw material composition for preparing the resin filler of C is mixed and kneaded to obtain a resin filler. (4) By coating the resin filler 40 obtained in the above (3) with the roller coater on both sides of the substrate ⑽ within 24 hours after the preparation, the conductor circuit 34 and the conductor circuit 34 and the through-hole 36 may be filled. Then, it is dried at 70 C for 20 minutes, and the other surfaces are filled with the resin filler 40 between the conductor circuits 34 or the through holes 36 in the same manner as above, and dried at 70 C for 20 minutes (see section (Fig. 22 (D)). (5) One side of the substrate 30, which has been subjected to the above-mentioned (4) treatment, is polished with a belt sander using # 6 0 0 belt-shaped abrasive paper (manufactured by Sankyo Ricoh Chemical Co., Ltd.) to grind the conductor. The surface of the circuit 34 and the surface of the ridge 36a of the through-hole 36 are polished so that no resin filler remains, and then polishing is performed to remove the flaws caused by the polishing of the belt sander. The surface of other substrates is also polished. Carry out the same polishing as above (refer to Figure 23 (E)) »

Then, a heat treatment is performed at 100 ° C for 1 hour, 120 hours for 3 hours, 150 ° C for 1 hour, and 180 ° C for 7 hours to harden the resin filler 40. As described above, the resin filler is obtained by smoothing the substrate 30 to both sides by removing the surface layer portion of the agent 40 and the roughened layer 38 on the conductor circuit 34 by removing the resin filler filled in the through holes 36 and the like. 4 0 and the conductor circuit 3 4 are firmly adhered to the side surface by the roughened layer 38 and the inner wall surface of the through-hole 36 and the resin filler 40 are strongly adhered to the printed circuit by the roughened layer 38

_407453 V. Description of the invention (92) board. That is, by this process, the surface of the resin filler 40 and the surface of the conductor circuit 34 become the same plane. (6) Carved on the substrate 30 on which the conductor circuit 34 has been formed, the soft money is engraved with a catalyst solution consisting of palladium chloride and an organic acid, followed by treatment with a Pd catalyst, and the catalyst is activated. After the conversion, in the copper sulfate 3.2 x 10_2πιο1 / 1, nickel sulfate 3. 9 X 1 0_3mol / 1, the ambiguous agent 5. 4 X l0-2mol / l, sodium hypophosphite 3. 3 X10-1 mol / 1, boric acid 5.0 X 1 0-1 mo 1/1 and surfactant (manufactured by Nissin Chemical Industry Co., Ltd., Surf Inol 465) 0. lg / l and ph = 9 Soak in liquid and perform vertical and horizontal vibration once every 4 seconds after soaking for 1 minute to set the surface of the conductor circuit 34, the ridge 36a of the through hole 36, and the bottom 60a of the via hole. A needle-like alloy coating layer and a roughened layer 42 made of Ni-P (see FIG. 23 (F)). Here again, cu-Sn substitution reaction is performed under conditions of smashing tin O.luiol / 1, thiourea 1.0mol / 1, temperature 35 ° C, and pH = 1.2 to set the surface of the roughened layer Sn layer (not shown) with a thickness of 0.3 mm. (7) The raw material composition for preparing the interlayer resin insulating agent of B is stirred and mixed 'to obtain an interlayer resin insulating agent (for the lower layer) having a viscosity adjusted to 1.5 p a · s. Next, "the raw material composition for the preparation of the adhesive for electroless plating of A was blended and mixed" to obtain a binder solution (for the upper layer) for an electroless clock whose viscosity was adjusted to 7 pa · s. (8) The interlayer resin insulating agent (for the lower layer) 44 having a viscosity of 1.5 Pa · s obtained in the aforementioned (?) Was 44 on both sides of the substrate of the aforementioned (6).

Page 96 V. Description of the invention (93) Use a roller coater for coating within 2 to 4 hours after preparation, and leave it for 20 minutes in a horizontal state, and then dry it at 60 ° C for 30 minutes (prebake) ), And then 'apply the photosensitive adhesive solution (for the upper layer) 46 having a viscosity of 7 Pa. S obtained in (7) above, and apply it using a roller coater within 24 hours after preparation, and leave it in a horizontal state. After 20 minutes, it is dried at 60 ° C for 30 minutes (touch drying) to form an adhesive layer 5 0α having a thickness of 35 μm (see FIG. 23 (G)). (9) The PET film 51 is closely adhered to both sides of the substrate 30 on which the adhesive layer has been formed in the above (8) (Fig. 24 (i)), and exposed at 500 mJ / cni2 using an ultra-high pressure mercury lamp. Furthermore, the substrate 30 was exposed to 300raj / cm2 using an ultra-high pressure mercury lamp, and was applied at 100 ° C for 1 hour 'at 120 ° T for 1 hour and thereafter at 150 ° C. Heat treatment (postbake) for 3 hours to form an interlayer resin insulating layer (two-layer structure) 50 with a thickness of 35 / zm. Thereafter, the PET film 51 is peeled off 6 (10), and the substrate 30 on which the interlayer resin insulating layer 50 has been formed is mounted on the χ_γ table 19 of the laser device with reference to FIG. 34, and the carbon dioxide gas is passed through Laser irradiation forms through-holes 48 (Fig. 24 (I)). In addition, a portion of the tin plating layer (not shown) is exposed at the through hole 48 which is a via hole. Here, in order to form a through hole with a diameter of 60 // ιη, ML5 003D is used as the laser oscillator of the laser device, and the pulse mode is short pulse (burst), multimode, and Carbon dioxide gas with a wavelength of 10, 6 / Zm is irradiated with 1 pulse energy

V. Description of the invention (94) Irradiation 3 times under the conditions of 0.3 m J, pulse interval 5 0 // s e c, and screen diameter 0.5 mm. Here, the enlarged view of Part C in Figure 24 (I) is shown in Figure 29. In the multilayer printed wiring board of the fourth embodiment, by directing a carbon dioxide gas laser beam to the conductor circuit 34 under the interlayer resin insulation layer 50, the light is reflected vertically and the reflected wave from the conductor circuit is reflected. The incident wave is dried up, and a stripe-like unevenness 49 is formed on the side wall 48 a of the electroless plated film 48 on the through hole 48. That is, every half wavelength (5 # m) 'of the carbonic acid gas laser can generate overlapping antinodes, in which relatively high heat will be generated, and the side walls 4 8 a will be etched in a wave shape. The depth D of the etched part is 0, bu 5 degree. ′ # M Figures 30 (A) and 30 (β) are enlarged photographs of through-holes 48 inserted in the interlayer resin insulation layer 50 with a carbon dioxide gas laser. Here, Fig. 30 (A) is a state viewed obliquely from above the through hole, and Fig. 30 (B) is a state viewed from directly above. Here, as the interlayer resin insulating layer, it is preferable to use a thermosetting resin or a composite of a thermosetting resin and a thermoplastic resin. This is because it is easier to form striped unevenness by laser interference. This thermosetting resin or a composite of a thermosetting resin and a thermoplastic resin is most suitable for those containing a propylene-based monomer. That is, by adding a propylene-based monomer, it can be more compatible with the “plasma” and can inhibit the resin (11) in the through-holes from continuing to the acid for 19 minutes. By immersing the substrate 30 in which the through-holes 48 have been formed, the The epoxy present on the surface of the interlayer resin insulation layer 50

Page 98 V. Description of the invention (95) Resin particles are dissolved and removed 'and at the same time the surface of the interlayer resin insulation layer 50 is roughened (see Fig. 24 (J)). After that, the obtained substrate was immersed in a neutralization solution (&gt; P &lt; Durby), and then washed with water. (12) On the surface of the base plate 30 that has been roughened by the process of (10) above, the catalyst core is attached to the surface of the interlayer resin insulation layer 50 by the application of a palladium catalyst (manufactured by 7). on. Thereafter, the substrate 30 was immersed in an electroless steel plating bath under the same conditions as in the first embodiment to form an electroless plated film 52 having an overall thickness of 0.6 μm (refer to FIG. 24 (K)). In the fourth embodiment, since the stripe-shaped unevenness is formed on the side wall 48a of the through-hole 48 of the interlayer resin insulating layer 50 by the interference of laser light, the electroless plated film 52 can be closely adhered to the side (13) A commercially-available photosensitive dry film is attached to the electroless copper plating film 52 formed in the above (11), then a curtain cover is installed, and exposure is performed at 1000 mJ / cm2. 0. 8% sodium carbonate is subjected to a development treatment, and a plating resist 54 having a thickness of 15 era is provided (refer to FIG. 24 (L)). (14) Next, the same operation as in the first embodiment is performed on the portion where the photoresist is not formed. Electrolytic copper plating was performed under the conditions to form an electrolytic copper plating film 56 having a thickness of 15 (see FIG. 25). (1 5) After the electroplating photoresist 54 is stripped and removed at 5% KOH, the electroless copper keypad film 52 under the electroplating photoresist is subjected to a name-cut treatment with a mixed solution of sulfuric acid and hydrogen peroxide to dissolve and remove to form Conductor circuit 58 having a thickness of is composed of electroless copper plating film 52 and electrolytic steel plating film 56 and

Page 99 V. Description of the invention (96) Interstitial hole 60 (Figure 25 (N)). (16) Perform the same steps as in (6), and form a roughened surface 62 made of Cu-Ni-P on the surfaces of the conductor circuit 58 and the via 60, and further perform Sn substitution on the surface ( (See Figure 25 (0)). (17) Through the process of repeated operations (7) to (16) to further form the upper interlayer resin insulation layer 150, the interlayer hole 160 and the conductor circuit 158, to complete the manufacture of the multilayer printed wiring board (Refer to Figure 25 (p)). In addition, in the process of forming the upper-layer conductor circuit, Sn is not substituted. R j is 3 μm. (18) Then, a solder bump &amp; block is formed on the above-mentioned multilayer printed wiring board. On both sides of the substrate obtained in the above (16), the solder resist composition described in D · described above was applied at a thickness of 45. Secondly, after drying at 70 ° C for 20 minutes and drying at 70 ° C for 30 minutes (touch drying), the PET film (not shown) is tightly adhered, and then it is irradiated with 1000 mJ / cm2 of ultraviolet light. Exposure 'and further further "peel off the PET film after applying heat treatment under the conditions of" one hour at 100 ° C, one hour at 100 ° C, one hour at 120 ° C, and three hours at 150 ° C " Then, a solder resist layer (thickness 20) 70 (Fig. 26 (Q)) is formed. (19) After that, the substrate 30 for which solder resist 70 has been formed is installed on the above-mentioned laser device with reference to Fig. 34. On XY table 90, through holes (openings) 71U, 71D are formed by the irradiation of acid gas ^ body laser irradiation (Figure 26 (R)) β Here 'in order to be on the upper side (for connection 丨c side of the wafer) through hole 711J with a diameter of 133 / zm, so ML5003D is used as the laser device

Page 407453

jML5 0 5GT) laser oscillator, and in the pulse mode is short pulse and set to multi-mode, the carbon dioxide gas with a wavelength of 10. 6βπ is irradiated with 1 pulse energy 2. OraJ, pulse interval 50 sec, curtain Irradiated twice under the condition of a diameter of 2.0 miR. 0 Here, part A in Fig. 26 (R), that is, the through hole 71U on the connection side of the IC chip, the enlarged view is as shown in Fig. 31 (a). Show. In the multilayer printed wiring board of the fourth embodiment, a carbon dioxide gas laser is irradiated perpendicularly to the conductor circuit 158 under the solder resist 70 to cause interference between the reflected wave and the incident wave reflected from the conductor circuit. 'And a stripe-shaped unevenness is formed on the side wall 71 a of the through hole 71 u along the hole direction of the hole. That is to say, every half wavelength (5 #m) of the acid-breaking gas laser can produce overlapping antinodes, and relatively high heat will be generated in this part, and the side walls 71 &amp; The depth of the wounded part is about 0.1 to 5 m. In addition, the interval between projections and depressions (the distance between the projections and projections) is about 5.5 from m. In the fourth embodiment, since a multi-mode laser capable of reducing the beam diameter is used for irradiation, it is possible to form a relatively small-diameter (50 to 300 // in) through-hole corresponding to a bump used for IC chip connection. Figures 32 (A) and 32 (B) are enlarged photos of the through holes (upper side) * 7 through the carbon dioxide laser on the solder resist 70. Here, Fig. 32 (A) shows the state viewed obliquely from above the through hole ill, and Fig. 32 (B) shows the state viewed from directly above. Here, the enlarged view of part B in FIG. 26 (R), that is, the through hole 71D on the lower side (mother board connection side) is shown in FIG. 31 (B). In order to form a through hole 71D with a diameter of 65 ohms on the lower side, ML5003D2 is used

Page 101 407453

V. Description of the invention (98) As a laser oscillator of a laser device (ML505GT), with a pulse mode of a short pulse and a single mode, a carbon dioxide gas with a wavelength of 1.0 m is irradiated to the f pulse. The conditions were 14 m J, pulse interval 16 # sec, and screen diameter 1 0.0 mm, and irradiation was performed 5 times. In the multi-layer printed wiring board of the fourth embodiment, by applying a carbon dioxide laser to the conductor circuit under the solder resist 70, the radiation is reflected vertically from the conductor circuit, and the reflected wave from the conductor circuit can be reflected. Interference with the incident wave occurs, and stripe-shaped unevenness (1 interference fringe) is formed on the side wall 71a of the perforation 71D by interference. The depth of the portion etched by the interference fringes is about 0.005 ^. In the fourth embodiment, since the laser beam is irradiated with a variable large beam diameter, it is possible to form a through hole having a relatively large diameter (300 to 65 νπι) corresponding to the bumps used for the motherboard. Figures 33 (A), 33 (B), and 33 (c) are enlarged photographs of the thorium spheres worn by the carbon dioxide laser on the solder resist 70. Here, Fig. 33 (A) shows the state of J from directly above. Fig. 33 (B) shows the side wall of the through-hole from the side, and Fig. 33 (C) shows the state of the through-hole from diagonally above. . = In the fourth embodiment, 'as the laser photoresist is used at the solder resist: through:', various materials which can be used as solder resist can be used. Also: In the conventional technology, lithography is used to pass through the solid substrate. A photosensitive resin can be used as the solder resist. However, in the fourth embodiment, since a laser is used, it can be used in Excellent electrical insulation on the electrical properties using the same thunder-to-silicon layer: = layer may =

407453 V. Description of the invention (99) A multilayer printed wiring board was manufactured. In addition, in terms of solder resist, it is preferable to use a thermosetting resin or a composite of a thermosetting resin and a thermoplastic resin. This is because the above materials are more likely to form stripe-like irregularities by laser interference. "(20) Secondly, the substrate 30 is immersed in a chlorinated chain 2.31 X 1 0-1 mol / 1 'hypophosphite. Sodium 2.8 X 1 〇-1 m〇i / 1 and sodium citrate 1, x lO ^ mol / l in a non-electrolytic nickel plating solution of ρη = 4.5, for 20 minutes, and in the opening 71U, A thick nickel plating layer 72 is formed on 71D. Next, the substrate was further set at 80. (: Under the conditions of immersion in potassium cyanide 4.g xlO-2mol / I, ammonium chloride 1.87 xl0-im〇i / i, sodium citrate !. 16 x: 10_1111〇1 / 1 And an electroless gold plating solution composed of sodium hypophosphite 1. 7 X 1 0-imol / 丨 for 7 minutes and 20 seconds to form a thickness of 0.03 on the nickel electroplating layer. A solder pad 75 is formed on the via 160 and the conductor circuit 58 (refer to FIG. 26 (S)). (21) Then, by opening 7111, 71D in the solder resist layer 70 The solder paste of low melting point metal is printed on it and reflowed at 200 to form solder bumps (solder objects) 76U, 76D, and the manufacturing of the multilayer printed wiring board 10 is completed (see FIG. 27) In the fourth embodiment, 'the solder is filled through the nickel plating layer 72 and the gold plating layer 74 to form solder bumps 7613 and 760. Therefore, the nickel plating layer 72 and the gold plating layer 74 form a stripe shape by The concave and convex through holes 71U and 71D are tightly adhered, so that the solder bumps 7 6ϋ and 7 6D can be firmly connected to the conductor circuit 1 58. The solder on the completed multilayer printed wiring board 10 Pins 92 of the 1C chip 90 are mounted on the bumps 76U and re-welded to mount the IC chip 90.

407458 V. Description of the invention (〖〇〇） The IC chip 90 as many as will be installed # such as t ^ u &lt; the printed circuit board 10 correspondingly mounted on the daughter board 94 side projection $ ^ On the daughter board 94. On the bump 96, 'combined and re-welded to install: the printed circuit board obtained is heated under heating for 48 hours)' to investigate the impedance change of the interstitial hole portion; 1.21 = outside, the 1C chip is actually installed Repeatedly run the test for 30 minutes at 10,000 H25C and 30 minutes at 55t / in, 隹 — = one t. For comparison, the printed circuit board of the example is also ordered the same For the test, the printed circuit board of the above embodiment is provided with through-holes after exposing the solder resist to ultraviolet exposure and then developing treatment with diethylene glycol dimethyl ether. ^ As a result, the printed circuit board of the fourth example has a resistance change rate of only 1% whether it is subjected to a heating test or a TS§ test. In comparison, the resistance change rate of the comparative example is 5%. As can be seen from the above description, the printed wiring board of the fourth embodiment is very excellent in connection reliability of fine via holes. On the other hand, the obtained printed wiring board was actually mounted with an IC chip to perform a HAST test (relative humidity 100%, applied voltage 1.3V, and left at a temperature of 121 ° C for 48 hours), and used A fluorescent X-ray analyzer CRigaku RIX 2100) cross-cuts the Pb ^ diffused in the solder resist layer. In addition, the 'repeated operation TS test (30 minutes at -125eC and 30 minutes at 55 t) was performed 10,000 times' to investigate whether the Ni / Ali layer was peeled and the solder resist cracked.

Page 104 V. Description of the invention (101)-"Further, for the sake of comparison," the printed circuit board of the embodiment is also subjected to the same test ", and the printed circuit board of the above embodiment is subjected to a solder photoresist layer. After the ultraviolet exposure, a development process is performed with diethylene glycol dimethyl ether to provide a through hole. As a result, the printed wiring board of the fourth embodiment has almost no p b migration. In comparison, the printed circuit board of the comparative example has proved to have many shortcomings during laser shots, and the phenomenon of "diffusion" also occurs. In addition, after the TS test, the examples confirmed that there would be no peeling or cracking. In contrast, in the comparative example, in addition to the bumps peeling from the Ni layer, cracks also occurred in the solder photoresist layer. As can be seen from the above description, the printing of the fourth embodiment In addition to preventing the peeling of the Ni plating film, the circuit board can prevent the metal ions from being diffused from the bumps. In addition, it can also suppress cracking of the solder resist layer. [Fifth Embodiment] Hereinafter, the fifth aspect of the present invention will be described. The multilayer printed wiring board of the embodiment will be described in the first modification. (1) A copper-clad laminate (Panasonic R5715) with a thickness of 0.6 mm on both sides is prepared, and the copper-clad laminate is attached to the substrate 130. Thickness 12 (β ra copper foil 1 3 2 (refer to Fig. 35 (A)). (2) The steel foil 丨 32 is etched with sulfuric acid-hydrogen peroxide aqueous solution to a thickness of (refer to Fig. 35 (B) ). (3) Using a carbon dioxide gas laser (Mitsubishi Electric ML605GTL)

Page 105 V. Description of the invention (102) A diameter of 150 kernels m (upper diameter D1: 160 / im, lower #) is set on a copper plated laminated plate 13 0A on both sides and irradiated 10 times with a pulse condition of 30mJ, 52 X 10-6 seconds. ) 2: Hole 116 (140 cone) (Figure 35 (C)). Therefore, it is possible to make holes in the substrate 130 by using the laser to penetrate the 5 #m copper foil 132. (4) Electroless copper plating is performed in the holes 116 to form plated through holes 136 (Fig. 35 (D)). The second modification (1) quasi-injuries a two-sided copper submersible plate with a thickness of 0.6 mm (Panasonic R5715) 2 30A, and the copper-clad laminate is attached with a copper foil 232 with a thickness of 12 on the substrate 230 (refer to 36 (A)). (2) The copper foil 232 is etched with a sulfuric acid-hydrogen peroxide aqueous solution to a thickness of 9 / zm (see FIG. 36 (B)). (3) The diameter of the carbon dioxide gas laser (Mitsubishi Electric ML605GTL) was irradiated 15 times on the two-sided copper laminate 2 3 0 A with pulse conditions of 30 m J, 5 2 X 1 0-6 seconds, and the diameter was set. 150 / zm (conical shape with upper diameter D1: 160 yin and lower diameter D2: 140 // m) (Figure 36 (C)). Therefore, it is possible to make holes in the substrate 2 30 by using the copper foil 232 with a laser penetrating 9 / zra. (4) The same procedure as in the first modification is carried out, and electroless steel plating is performed to form plated through holes 236 (Fig. 36 (D)). Third Modification (1) A copper-clad laminate (Panasonic R5715) 330A with a thickness of 0.6 mm is prepared on both sides, and the copper-clad laminate is attached with a copper foil 332 having a thickness of 12 on a substrate 3 30 (refer to FIG. 37). (A)). (2) The copper foil 332 is etched with a sulfuric acid-hydrogen peroxide aqueous solution to form

P.106 5. Description of the invention (103) The thickness is 5 m (refer to Fig. 37 (B)). (3) The carbon dioxide gas laser (Mitsubishi Electric ML6 0 5GTL) was irradiated on the double-sided copper-clad laminate 330A 15 times from the surface and the inside 15 times with a pulse condition of 30mJ, 52 X 10-6 seconds, and the diameter was set to 5. &quot; m (the maximum diameter D3: 1 60 m, the minimum diameter D 4: 1 4 0 # m) of the hole 31 6. The cross section of the hole 3 1 6 is bank-shaped (Fig. 37 (C)). (4) The same procedure as in the first modification is performed, and electroless copper plating is performed to form a plated through hole 336 (Fig. 37 (D)). In the fourth modified example, since the laser light is irradiated from the surface and the inside, through-holes can be formed even if the substrate is thick. Comparative Example 7 (1) A double-sided mineral copper laminate (Panasonic R5715) having a thickness of 0-6 mm was prepared, and the steel-plated laminate was attached with a copper pig of a thickness. (2) A carbon dioxide gas laser (Mitsubishi Electric ML60 5GTL) was used to irradiate the steel-clad laminate on both sides with pulses of 30mJ, 52 X 1 0-6 seconds for 15 times, but the result was that perforation was impossible. From this example, it can be seen that if the thickness of the copper foil exceeds 12αm, a through hole cannot be formed. Fourth Modified Example Next, a fourth modified example of forming a multilayer printed wiring board by using a laser to form a through hole will be described with reference to FIGS. 38 to 44. First, with reference to the structure of the multilayer printed circuit board of the fourth modified example, λλ, ΜΜ 闾, ～ Ming Shicheng, and the composition of the circuit board 10; 5θ: r Αα / plate is formed on the surface of the core substrate 30, and the stack is formed inside. Build up the line layers 80A, 80β. The circuit layer 80A is formed by the interlayer resin of the via hole 60 and the conductor &quot; long conductor circuit 58.

Page 107 V. Description of the invention (104) The insulating layer 50 and the interlayer resin insulating layer 150 having the via hole 160 and the conductor circuit 158 formed thereon. In addition, the superimposed circuit layer 80B is composed of an interlayer resin insulating layer 50 having a via hole 60 and a conductive circuit 58, and an interlayer resin insulating layer 150 having a via hole 160 and a conductor circuit 158 formed. A solder bump 7 6 U is provided on the upper surface side of the multilayer printed wiring board 10 to connect a ridge (not shown) of the IC chip. The solder bump 7 6U is connected to the through-hole 36 through the via hole 160 and the via hole 60 "On the other hand, a solder bump (not shown) for connecting the daughter board with a ridge (not shown) is arranged on the lower side" 76D. The solder bump 76D is connected to the through-hole 36 through the via hole 160 and the via hole 60. Next, a method for manufacturing the multilayer printed wiring board 10 will be described. Manufacture of printed wiring board (1) A steel-plated laminated board 30a formed by laminating i2 # m steel foil 32 on both sides of a substrate 30 having a thickness of 0.6 mm and made of glass epoxy resin as a starting material ( Refer to Figure 38 (A)). This was etched to adjust the thickness to 5 μm (Fig. 38 (B)). (2) A carbon dioxide gas laser (Mitsubishi Electric ML605GTL) was used to irradiate the mineral steel laminate 300A with pulses of 30 m J and 5 2 X 1 0-6 seconds for 15 times, and a diameter of 100 Am was set. (The upper diameter D1: 1 10 # ιη, the lower diameter D2: 90 mm cone shape) of the through hole 16 (Fig. 38 (C)). Next, "implement electroless plating and electrolytic plating (Fig. 38 (D))", and further, copper foils are engraved in accordance with the pattern and shape according to a general method, to form a thick inner layer copper pattern (lower conductor layer) on both sides of the substrate. Circuit) 34 and through hole 36 (Fig. 38 (E)).

407453 V. Description of Invention (105) —- Secondly, a roughened layer 38 is separately provided on the surface of the inner copper pattern 34 and between the surface of the ridge 36a of the through hole 36 and the inner wall to manufacture a circuit board (Fig. 38 ( F)). The roughened surface 38 is formed on the surface of the inner copper pattern 34 and between the surface of the ridge 36a and the inner wall of the through-hole 36 after the substrate 30 is washed and dried with an etchant, and then both sides of the substrate are spray-washed with a shower head.刻 formation. This etching solution is a mixture of 10 parts by weight of copper imidazole (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride, and 78 parts by weight of ion-exchanged water. (3) Next, the resin layer 40 is provided between the inner layer copper patterns 34 of the circuit board and inside the through-holes 36 (Fig. 38 (g)). The resin layer 4 ′ is a resin filler prepared in advance and the same as that of the fourth embodiment is applied on both sides of the circuit substrate by a roller coater to fill it between the inner steel pattern and the through-holes, and then Formed by heat treatment. (4) One side of the substrate 30 obtained by the process (3) is polished with a belt-shaped sander. In this polishing, the surface of the roughened surface 38 of the inner layer copper pattern 34 and the ridge 36a of the through-hole 36 was polished using a strip-shaped abrasive paper (manufactured by Sankyo Ricoh Chemical Co., Ltd.) of # 6 0 0 to leave no resin filler 40 ( Figure 39 (Η)). Next, polishing is performed to remove a flaw caused by the grinding of the belt sander. (5) Further, the exposed inner layer steel pattern 34 and the ridge 36a of the through hole 36 are roughened by using the etching treatment of (2) to form Rough surface 42 at depth 3 (Fig. 39 (I)).

Page 407 407453 V. Description of the invention (106) The roughened surface 42 is subjected to tin instead of electroplating to provide a Sn layer (not shown) with a thickness of 0.3 m. The replacement plating system was tin borofluoride 〇. 丨 m〇 丨 / 丨, thiourea 1.00 rool / 1, and temperature 50. (: And conditions of pH = 1.2, the roughened surface is subjected to a C u -_S η substitution reaction. (6) Two roller coaters are applied to both sides of the circuit substrate 30 to obtain the coating and In the fourth embodiment, the same adhesive for electroless plating was used. After the adhesive was left horizontal for 20 minutes on the substrate and dried at 60 for 30 minutes, an adhesive layer 5 having a thickness of 35 / zm was formed. 〇 ((J)). (7) Both sides of the paid circuit board 3 〇 were exposed at 500 mJ / cm2 using an ultra-high pressure mercury lamp, and heated at 150 ° F. for 5 hours. (8) The obtained The substrate 3 was immersed in chromic acid for one minute, thereby dissolving and removing the epoxy resin particles existing on the surface of the adhesive layer 50. By this treatment, roughening can be formed on the surface of the adhesive layer 50. However, the obtained substrate 30 was immersed in a neutralization solution company and then washed with water (Fig. 39 (K)). (9) Next, a thickness of 0.06 was formed on the entire surface of the substrate 30. Electrolytic copper plating film 44 (Fig. 40 (l)). (1 0) is not engraved with a photoresist (not shown), and sulfuric acid-peroxidation = etching is used. The interstitial holes of the electrolytic copper plating film 44 are formed into the opening 44a (FIG. 40 (M)). (11) The above electroless steel plating film 44 is used as a uniform cover and a short pulse is used ( 10-4 seconds) of laser light (Mitsubishi Electric ML6〇5gtl)

Page 110 407453 V. Description of the invention (107) Remove the adhesive layer 50 under the opening 44a and provide an opening 48 for the interlayer hole (Fig. 40 (N)). Further, on the surface of the circuit substrate 30, A catalyst core (made of a palladium catalyst) is applied, and a catalyst core is attached to the surface of the electroless plated film 44 and the roughened surface of the via 48 for the via hole. (12) The obtained substrate 30 is immersed in an electroless copper plating bath, and an electroless copper key film 52 having a thickness of ι · 6 is formed on the entire substrate 30 (Fig. 40 (0)). (13) Next, a commercially-available photosensitive dry film (not shown) is attached to the electroless copper plating film 52, and a curtain film having a printed pattern is mounted thereon. The factory then exposed the substrate 30 at 100 mJ / cm2, and then developed it with 08% sodium carbonate, and set up a plating resist 54 with a thickness of 15 jC / in (Fig. 40 (P)). 0 (14 ) Next, electrolytic copper plating is performed on the obtained substrate to form an electrolytic copper plating film 56 with a thickness of 15 / ^ m (Fig. 40 (Q)) »(15) The plating photoresist 54 is stripped and removed at 5% KO. After that, the electroless copper plating film 52 under the electroplating photoresist is subjected to silver engraving treatment with a mixed solution of sulfuric acid and hydrogen peroxide to dissolve and remove, thereby obtaining copper foil 32, electroless plating film 44, electroless steel plating film. The conductor circuit 58 and the interlayer hole 60 formed by the 52 and the electrolytic copper plating film 56 with a thickness of 18 # ια (10 μm to 30 in.m.) (FIG. C 41 (R)). Here, by forming the thickness between 10 m to 30 / zrn ', it is possible to achieve both fine pitch and connection reliability. Going further ’immersed the substrate in 70 g of chromic acid for 3 minutes at 70 ° C

Page 111 407453 Description of the invention (108) The surface of the adhesive layer 50 for electroless plating between the conductor circuits 58 is etched by 1 μm to remove the palladium catalyst on the surface. (16) Perform the same process as in step (5) above, and form a roughened surface 62 'composed of _ {^ _? On the surfaces of the conductor circuit 58 and the via 60, and further replace the surface with 仏(Refer to Figure 41 (s) (17) By repeatedly operating the processes (6) to (16) above, the upper interlayer resin insulation layer 15o, the interlayer hole 16o, and the conductor circuit 158 can be further formed. Further 'Open on the surface of the via 16 and the conductor circuit 158 &gt; to form a roughened layer 162' to complete a multilayer printed wiring board (Fig. 41 (τ λ ')). In addition, No Sn substitution is performed during the forming process. (18) Then, a solder bump is formed on the multilayer printed wiring board described above. On both sides of the substrate 30 obtained in the above (17), a thickness of 45 m is applied. The same solder photoresist composition as in Example 4. Next, after a drying process was performed at 70 ° C for 20 minutes and 70 ° C for 30 minutes, a light with a circular pattern (curtain pattern) was drawn with a thickness of 5 mm. The cover film (not shown) is attached tightly, and then exposed to ultraviolet light of 1 000 mJ / cm2, and then executed. "Development processing. Then, it is performed at 80 ° C for 1 hour,} 〇 〇 1 hour,

Heat treatment under conditions such as 1 hour at 20 ° C, 3 hours at 150 ° C, etc., and the solder foot portion (including the interlayer hole and its ridge portion) is formed with (opening diameter 20). The solder resist layer (i.e., 22% thick) of i ”i has? F (Picture 42 (u)). (1.9) Secondly, a nickel plating layer 72 is formed. Further, by further

Page 112

0.03 layer holes 160 and conductor circuits 158 are formed on the brocade plating layer

Mm gold plating layer 74 is formed at the soldering pin 75 (see Figure 42 (V) (.20)) at the intermediary. Then, the sintering is performed at the left side of p. On the opening 71 of the tin photoresist layer Printing is known to be tin-poor and to 200. (: Perform ® calibration such as I, 7fin, 7fiT, order to melt and form solder bumps (solder) ft) U 76D 1 that is Yuan Cheng Duo Gong Ji 丨 (w) ). Manufacturing of θ p brush circuit board 10 (refer to FIG. 42 (the fifth modification)) The procedure is the same as that in the fourth modification, and the obtained board has a through-hole 3 3 6 board. However, the one obtained in the third modification is used instead. The through-hole forming substrate 330 is used as the core base (6th modification) The structure of the multilayer printed wiring board in the sixth modification is not shown in FIG. 44. In this printed wiring board, the through-holes 16 of the through-holes 36 The diameter]) is formed by laser to 100 ~ 200. In this example, the through hole 16 is not provided in a tapered shape. Then, in the multilayer printed wiring board, the via hole 60 is formed so as to plug the through hole 16 formed in the through hole 36 formed on the core substrate 30, and the via hole 60 is disposed in Directly above the through hole 36. In this way, the wiring length in the multilayer printed wiring board can be minimized, and the speed of the iC chip can be increased. In addition, 'the dead space can be eliminated by using the area directly above the through hole 36 as a function of the inner foot'. Moreover, because it is not necessary to use the inner layer from the through-hole 36 to the connection via hole 60! The line between the bits ’, so the shape of the ridge 36a of the through hole 36 can be formed to be true

P. 113 V. Description of the invention (110) The result of the circle ° can improve the arrangement progress of the through holes 36 provided in the multilayer core substrate 30. In addition, in this embodiment, as long as 20% to 50% of the bottom surface of the wide hole 60 is in contact with the ridge 36a of the through hole 36, a sufficient electrical connection effect can be achieved. As described above, in the fifth embodiment, since a carbon dioxide gas laser can be used for perforation directly on a copper-clad laminate, fine through holes can be formed at low cost. [Sixth embodiment] Hereinafter, a multilayer printed wiring board according to a sixth embodiment of the present invention will be described. Manufacture of printed wiring board (1) Electrician R5715 ′ D 2: 190 under a substrate of thickness 0.6 mm and made of glass epoxy resin. (:) A copper-clad laminate 30a formed by laminating 12 # 111 copper and metallurgy 32 on both sides of 30 was used as a starting material (Fig. 45 (A)). It was engraved with money to adjust it to a thickness of 5 m (Fig. 45 (B)) ° (2) Carbon dioxide gas laser (Mitsubishi Electric ML60 5GTL) was used on the copper-clad laminate 30A at 30 mJ, 52 X 1 A pulse condition of 15 seconds was irradiated 15 'and a through-hole 16 having a diameter D: 100 was set (FIG. 45 (C)). The through hole 16 is non-tapered. Next, electroless plating and electrolytic plating are performed (Fig. 45 (D)), and "the copper foil is etched in accordance with the general method according to the pattern shape" to form a thick inner layer copper pattern on both sides of the substrate (lower conductor circuit ) 34 and through-hole 36 (Figure 45 (E)).

P.114 407453__ V. Description of the invention (111) The roughened layer 38 is provided on the surface of the inner layer copper pattern 34 and between the surface of the ridge 36a and the inner wall of the through hole 36 to manufacture a circuit board (No. 46 circle (F)). The roughened surface 38 is the surface of the inner layer copper pattern 34 and the surface of the ridge 36a and the inner wall of the through-hole 36 after the substrate 30 is washed with water and dried, and then both sides of the substrate are spray-washed with a shower head. Touch formation. This etching solution is a mixture of imidazole steel (π) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride, and μ parts by weight of ion-exchanged water. C3) Come again 'The resin layer 40 is provided between the inner layer copper patterns 34 of the circuit board and inside the through holes 36 (Fig. 46 (G)). Resin layer A 'is a resin filler previously prepared in the same manner as in the fourth embodiment, and is applied on both sides of the circuit substrate with a roller coater to fill it between the inner copper pattern and the through hole. It is hardened by heat treatment for 1 hour at 1 hour, 3 hours at 120 ° C, 150 T; 1 hour at 7 hours and 7 hours at 180 ° C. (4) One side of the substrate 30 obtained by the process (3) is polished with a belt-shaped sander. In this polishing, the surface of the roughened surface 38 of the inner layer steel pattern 34 and the ridge 36a of the through-hole 36 was polished using a strip-shaped abrasive paper (manufactured by Sankyo Chemical Co., Ltd.) of # 60 0 to leave no resin filler 40 (No. Figure 46 (H)). Next, polishing polishing is performed to remove the flaws caused by the polishing of the belt-shaped sander, and polishing is performed on the surface of other substrates in the same manner as above. (5) Furthermore, the exposed inner layer copper pattern 34 and the ridge 36a of the through hole 36 are roughened by using the etching treatment of (2) to form a deep layer.

Page 115 407453 V. Description of the invention (112) Roughened surface 42 (Figure 46 (I)). The roughened surface 42 is subjected to tin instead of electroplating to provide a Sn layer (not shown) having a thickness of 0.3 / zm. Substitute electroplating under conditions of 0.1 mol / l of borofluoride, 1.0 mol of thiourea, temperature of 50 ° C, and pH of 1.2, subjecting the roughened surface to a Cu-Sn substitution reaction . (6) On both sides of the obtained circuit board 30, the same adhesive for electroless plating as in the fourth embodiment was applied using a roller coater. After the adhesive was left for 20 minutes in a horizontal state of the substrate, and dried for 30 minutes at 60 ° C, an adhesive layer 50 having a thickness of 35 was formed (Fig. 46 (J)) ΰ

(7) Both sides of the obtained circuit board 30 were exposed at 500 mJ / cm2 using an ultra-high pressure mercury lamp, and then heated for 5 hours. (8) The obtained substrate 30 is immersed in chromic acid for 1 minute, and the epoxy resin particles existing on the surface of the adhesive layer 50 by the net are dissolved and removed. With the driving treatment, a roughened surface can be formed on the surface of the adhesive layer 50. Then, the obtained substrate 3 is immersed in a neutralization solution p &lt; and then washed with water (Fig. 46 (K)) P (9). Next, a thickness of 6 is formed on the entire surface of the substrate 30. No electrolysis Steel plating film 44 (Fig. 47 (L)). . β

^ 〇) Yan Shi set an etching photoresist (not shown) and used sulfuric acid-peroxide for the rest of the time: the hole shape of the interlayer in the electroless copper electroplated film 44, and Shao Shang sighed the opening 050m in diameter 44a ( (Figure 47)). ⑴) Use the above electroless copper electro-membrane film 44 as a uniform cover

Page 116 407453 Description of the 5 'invention (113) and using a short pulse (10_4 seconds) of laser light (Mitsubishi Electric ML605GTL) to remove the adhesive layer 50 under the opening 44a and set the opening for the interlayer hole 4 8 ( (Figure 47 (N)). Furthermore, on the surface of the circuit substrate 30, a catalyst core (manufactured by Toyo Chiba) is applied to attach a catalyst core to the surface of the electroless clock film 44 and the opening 48 for the interlayer hole. Roughened surface. (1 2) The obtained substrate 30 is immersed in an electroless copper plating bath, and an electroless copper plating film 52 having a thickness of 1.6 is formed on the entire substrate 30 (FIG. 47 (0)). (13) Next, a commercially available photosensitive dry film (not shown) is attached to the electroless copper plating film 52, and a curtain film having a printed pattern is mounted thereon. γ Next, the substrate 30 is exposed at 100 m J / cm2, and then developed with 0.8% sodium carboxylate to establish a plating resist 5 4 (Figure 47 (P )). (1 4) Next, an electrolytic copper electric bond is performed on the obtained substrate to form an electrolytic copper plating film 56 having a thickness of 15 / zm (Fig. 48 (Q)). (1 5) After stripping and removing the plating photoresist 54 at 5% KOH, the electroless copper plating film 52 under the plating photoresist is subjected to #etching treatment with a mixed solution of sulfuric acid and hydrogen peroxide to dissolve and remove, thereby obtaining Conductor circuit 58 having a thickness 9 made of copper foil 32, electroless plated film 44, electroless copper plated film 52, and electrolytic copper plated film 56 (10em ~ 30 from PD) and via hole 60 (p. 48) (R)). Here, by forming the thickness between 10gra and 30Mni ', both the fine pitch and the connection reliability can be taken into consideration at the same time.

Page 117 407453 V. Description of the invention (114) Further, the substrate was immersed in chromic acid at 80 g / l for 3 minutes at 70 ° C, so as to bond the conductive layer 5 to the electroless plating between the conductor circuits 5 to 8 The surface of 〇 is subjected to a 1 / zm epitaxial treatment to remove the surface period catalyst. (16) Perform the same process as in step (5) above, and form a roughened surface 62 'composed of Cu-Ni-P on the surfaces of the conductor circuit 58 and the via 60, and further substitute Sn on the surface. (Refer to Fig. 48 (S) (17). By repeatedly operating the processes of (6) to (16) above, the interlayer resin insulation layer 150, the interlayer hole 160, and the conductor circuit of the upper layer can be further formed. 158. Furthermore, a roughened layer 1 62 is formed on the surface of the via hole 160 and the conductor circuit 158 to complete a multilayer printed wiring board (Fig. 47 (τ 〇)). In addition, the upper conductor circuit No Sn generation is performed in the formation process. (18) Then, a solder bump is formed on the multilayer printed wiring board described above. On both sides of the substrate 30 obtained in the above (17), 45 vm and 4th are coated. Example of the same solder photoresist composition. Next, two exposures. Development 'M in the solder foot portion (including the interlayer hole and its two grooves) to form a solder having an opening (opening diameter 2000_) 71. Tin photoresistance is 20 ym) 70 (Figure 49 (υ)). θ (thickness 0 (19) ^ times, forming a thickness of 5 "72 at the opening 71. Further:-Step: Forming a thickness by further depositing on the power recording ore layer. · 〇3: plating gold plating layer Via hole 16 and conductor pin 75 (Figure 49 (V)). The above 'tin (20) is

And then printed on the opening 71 of the solder photoresist layer 70

Page 118 407453 V. Description of the invention (Π5) Solder paste and re-soldering at 200 C to form solder bumps (solder objects) 76U, 76D, that is, the manufacture of multilayer printed wiring boards is completed (see section 5). Figure Comparative Example 8 A double-sided copper-clad laminate composed of R-1 7 50 (FR-4 grade: Tg point 1 65 ° C) manufactured by Matsushita Electric Works was used as the starting material for the core substrate. A multilayer printed wiring board was manufactured according to the steps of the example. The HAST, S, EA, and TS tests were performed corresponding to the multilayer printed wiring board of the sixth example and the multilayer printed wiring board of the comparative example. The results are shown in Figure 5 8 The table in the figure.

Here, the HAST s-type inspection system is applied to 10 multilayer printed wiring boards under the conditions of 130 ° C, 85% Rh, 1.3 atm, and a voltage of 1.8V is applied and maintained for 100 hours in this state. , Measure the insulation resistance between its plated through-holes. On the other hand, the STEAM test was performed on 10 multilayer printed wiring boards under conditions of 121 ° C, 100% Rh, and 2.1 atm for 336 hours, and then the insulation resistance between the plated through-holes was measured. In other aspects, the TS test is performed on 10 multilayer printed wiring boards, which are repeatedly heated for 3 minutes at -55 ° C and 3 minutes at 125 ° C. After 1,000 cooling steps, the electrical ship through-hole chain is measured. hole chain) Cj). In addition, the so-called plated through-hole chain is, as shown in FIG. 45 (E,), the adjacent through-holes 36 are in a chain shape between the conductor circuit 34 on the surface side of the core substrate and the conductor circuit 34 on the back side. Electrical continuity

Page 119 407453

5. Description of the invention (116) As shown in the results of the table in Fig. 58, the insulation properties of the multilayer printed wiring board of the comparative example are greatly reduced. In addition, in the sixth embodiment, the reliability required for a multilayer printed wiring board is obtained by using Panasonic Electric Works R5715 (Tg: 19 ° C) as the substrate 30. In addition, the glass epoxy substrates (1) to (4) with a Tg point of 190 ° C or higher similar to the sixth embodiment are as follows. When the above HAST, STEAM, and TS tests are performed, the same results as in the sixth embodiment can be obtained. Reliability. Therefore, it can be seen from the results that the necessary reliability can be obtained by using a glass epoxy plate having a Tg: i 90 or higher. (1) Mitsubishi Gas Chemical HL83 0 (Tg point 217 ° C) (2) Mitsubishi Gas Chemical HL830FC (Tg point 212 ° C) (3) Hitachi Chemical Industry mCL_e_679ld (Tg point 205 ~ 215.) (4) Hitachi Chemical Industries MCL-E-679F (Tg point 20 5 ~ 2 Π t) As explained above, in the sixth embodiment, a cheap glass ring and a core material made of a substrate are used as the core substrate, and It has sufficient functions in terms of insulation resistance and thermal cycle characteristics between plated through-holes. [Seventh embodiment] Hereinafter, a printed wiring board and a manufacturing method thereof according to a seventh embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 53 (B), the printed wiring board 7 of the seventh embodiment is formed by a subtractive method and has a conductive pattern 2 and a plated through-hole 7 on the surface of the insulating substrate 704. The so-called two panels. That is, the printed board 7jl has two conductor layers. As for the insulating substrate 704, for example, a% oxygen resin, a polyimide resin, a BT (bismaleic anhydride imine triazine) can be used.

P.120 407453 V. Description of the invention (117) Impregnated resin and other materials in glass cloth substrate. In the seventh embodiment, a base material (so-called glass epoxy material) impregnated with a relatively inexpensive epoxy resin is selected. The insulating base material 704 is derived from a copper-clad laminate 705 as a metal-clad laminate. The conductive pattern 70 2 formed on the surface of the insulating base material 70 4 is a copper base layer 706 having a thickness of 0.2 to 3.0 / zm and serving as a base layer, a thin coated copper plating layer 707 formed on the copper base layer 706, and a thin layer A thick copper-plated copper layer 708 on the copper-plated copper layer 707 is formed. That is, the conductor pattern 702 is composed of a three-layer structure. In addition, the copper underlayer 706 is an ultra-thin copper foil 70 9 derived from an ultra-thin conductive metal foil. Here, the space between adjacent conductor patterns &amp; 702 is set to about 35 μm, and the line width (the width of the top portion) of the conductor pattern 702 Y is set to Set it to about 70. The conductive patterns 70 2 formed on the front and back surfaces of the insulating base material 70 4 are electrically connected to each other through plated through holes 703 formed through the insulating base material 704. The conductor layer in the plated through-hole 703 is a thin-coated copper plating layer 007 formed on the inner wall surface of the through-hole forming hole 710 and a thick-coated copper plating formed on the thin-coated copper plating layer 707. Layer 708 is composed. That is, the conductor layer in the 'plated through-hole 703' has a two-layer structure. The ridge 3a of the plated through-hole 703 is the same as the structure of the conductor pattern 702, that is, it is composed of a three-layer structure. Next, a procedure for manufacturing a printed wiring board 701 of the seventh embodiment will be described. First, prepare copper-clad laminates for use as metal-clad laminates

407453

V. Description of the invention (118) = 5. As shown in Fig. 51 (A), extremely thin copper cymbals 9 are attached to both surfaces of the insulating base material 704 of the steel-clad laminate 7Q5. Specifically, the thickness of copper Jim is preferably ο. 5_ ~ 7 · 0, and ι 〇_ ~ 3 {^ m is particularly preferred. If the thickness of copper f | 709 is too thick, the thickness component that should be removed by etching in the second-patterning process of the conductor pattern described later will be insufficient. Therefore, here you use gn copper foil 709 (thickness 99.8% or more electrolytic copper foil) with a thickness of 3.0 β m. For example, aluminum foil, tin can be used. However, if it is cheap and etched, it is selected as the seventh embodiment.

Considering that metal foils other than copper foil 709 have excellent etchability, such as foil, gold foil, silver foil, platinum foil, and nickel foil, copper box 709 is also preferable. In the next perforation process, a drill is used to form a diameter at a predetermined position of the copper-clad laminate to be prepared. The diameter is 0. 〖Dragon ~ 〇. 2 # m: through-hole formation hole 710 (refer to Section 51 (B)). If it is desired to form a through-hole forming hole 71 of 2 diameter, it is replaced by laser processing. If the perforating process is performed as described above, a residual seat will be generated in the through hole 71 a due to heat generation. Therefore, the generated residues should be dissolved and removed. Therefore, the residue-removing liquid is used to treat the steel-clad laminate 705 β. In addition, the plasma method can also be used to perform the residue-removing treatment. The above-mentioned residue removal process is based on the condition that the ultra-thin copper foil 709 is not eliminated, and specifically, the thickness of the copper foil 709 can be reduced to 1/10 to 1 of the original thickness. The degree of / 2 was used as a condition to remove the residual '-liquid. In this case, sulfuric acid, chromic acid, basic permanganese can be used

Page 122 407453 V. Description of the invention (119) Acid solution and so on. In the seventh embodiment, a sodium permanganate solution having a low oxidizing power at 30 was used. 〇 70. (: 5 minutes to 20 minutes for the next treatment. The residue is almost completely removed by the residue removal treatment as described above, and the thickness of the copper box 709 is also reduced to about 1/3 of the original thickness. As a result, as shown in FIG. 51 (CB), forming a bottom layer 706 derived from a very thin copper foil 709 with a thickness of about 0.1 m. The thickness of the bottom layer 706 is preferably in a range of 0.2 / zm to 3.0. After the shallow-removal process, 'the second step is to provide a catalyst core for plating deposition on the inner wall surface of the through-hole forming hole 71o', and then to activate the catalyst core. In the provision of the catalyst core, noble metal ions, noble metal colloids, and the like can be used. Generally, 9 palladium chloride or palladium colloids are used. After the catalyst nucleation is performed and the activation process is performed, a thin-coated steel plating layer 707 is formed by electroless copper plating on the entire surface of the bottom layer 706 and the inner wall surface of the through-hole forming hole 710 (see FIG. 51 (C)) ° The first plating process uses an electroless copper plating bath, which is one of the electroless plating baths, and uses it to form a thin-coated copper plating layer with a thickness of 0 5 &quot; 111 ~ 2.5 # 111. In the example, the thickness of the same layer 707 is set to about 1.0 μm. If this layer 707 is too thin, the entire inner wall surface of the through-hole forming hole 7 10 in the subsequent electroplating process cannot be accurately deposited by electrolytic forging. Therefore, the conduction of the plated through hole 703 is good, and sufficient reliability cannot be sought upward. Conversely, if the formation of 707 is too thick, it will lead to lower productivity and higher costs.

5. Description of the invention (120) 'a-At the same time, the thickness component that should be removed by etching in the process of separating and disconnecting conductor patterns will not be sufficiently reduced. After the first plating process, a predetermined curtain 7n is formed on the thin-coated copper plating layer 707 as a photoresist. In this case, the curtain cover 71 1 can also be formed into β using a commercially available dry film photoresist because the use of a photosensitive material can increase the precision of pattern formation. Then, the dry film photoresist laminated as described above is exposed and developed in accordance with a general method. As a result, as shown in FIG. 52 (A), a curtain cover 711 having a thickness of 35 em having an opening portion 712 is formed at a predetermined position. After the curtain forming process, an electrolytic copper electrode, which is one of electrolytic plating, is used.

The money bath forms a thick-coated steel plating layer 708 V at a position exposed from the opening (see FIG. 52 (B)). If the copper-plated copper plating layer 708 is formed as thick as described above, it is possible to selectively thicken only the portion where the conductor pattern 702 should be formed thereafter. In the above-mentioned electrolytic steel plating bath, a copper sulfate plating bath is used in the seventh embodiment. As a result of the second electroplating, a thick copper-plated copper plating layer 708 having a thickness of about 50 to "111" was formed on the thin copper-plated copper plating layer 707 located at the exposed position. In addition, if the same layer 708 is too thin, it will not be ensured that the finally obtained conductor pattern 702 has a sufficient thickness. Conversely, if the same layer 708 is too thick, it will result in reduced productivity and increased cost. In the seventh embodiment, the thickness of the thick-coated copper plating layer 708 is set to about 20 μm // m 〇 After the second plating process, the unnecessary curtain cover 711 is peeled off so as to be located below it. The thin coated copper plating layer 707 is exposed (see FIG. 53). Then, an etchant obtained by dissolving copper is used for etching treatment, and the

Page 124 407453 V. Description of the invention (121) The thin copper-plated copper plating layer 707 and the copper bottom layer 70 6 are completely removed. Here, 'Because it is attached to the thick-coated copper electric clock layer 7 008, it is specially treated without setting a photoresist, so the surface layer of the thick-coated copper electroplating layer 708 is also engraved with money about 2 # m degree. Then, the conductor patterns 7 0 2 are separated and disconnected from each other by the above process, and the printed wiring board 7 1 1 as shown in FIG. 53 (β) is completed. Therefore, if it is based on the seventh embodiment, the following effects can be obtained.

(1) A thin copper-plated copper plating layer 7 07 and a steel base layer 7 0 6 are formed together with an extremely thin thickness. Accordingly, it is possible to reduce the thickness component that should be removed by the engraving in the process of separating and breaking the conductor pattern to about 2 / zm, which is considerably less than the conventional one. Therefore, the conductive pattern 702 which can be separated and separated in the same process, that is, it is not easy to form a shape with a widened lower portion, and a fine pattern with excellent shape can be accurately formed. (2) A printed wiring board 701 is manufactured by using an electroless copper plating bath in the first plating process and an electrolytic copper electroforging bath in the second electric ore process. In other words, the electroforged precipitation leaves are applied to the inner wall surface of the through-hole forming hole 71o only using an electroless copper electroplating bath ', and then an electrolytic copper electroplating bath that is extremely inexpensive and has a fast recording speed. Accordingly, cost performance and productivity can be further improved. Furthermore, since an extremely thin and thin copper-plated copper plating layer is formed, the amount of thickness that should be removed by etching in the process of separating the conductor patterns is also very small. Therefore, the selection of the above-mentioned electroplating baths does indeed further improve the accuracy of forming fine patterns with excellent shapes, which has a great effect.

407453 V. Description of the invention (122) (3) The conductor pattern separation and disconnection process in the seventh embodiment is performed without providing an etching photoresist on the thick-coated copper plating layer 708. Therefore, in this process, it is basically unnecessary to perform an etching photoresist formation and peeling process. As a result, the total number of working hours can be reduced and productivity can be further improved. In addition, the thickness of the thick-coated copper electroplated layer removed with the etching at this time is also approximately 2 m. Accordingly, "when the above-mentioned etching is performed", it does not adversely affect the precision and cost of pattern formation. C 4) The printed circuit board 700 obtained by the above manufacturing method, and the structure of the conductor pattern 702 includes: a copper bottom layer 706 derived from a copper foil 709 with a thickness of about &amp; 1.0 Vm; Approximately ο thin jaw-coated copper plating layer | 707; and thick-coated copper plating layer 20 with a thickness of 708 ^ In addition, the metal system forming the above three layers is the same metal (ie, steel) β, and then, as described above The general conductor pattern 702, in addition to having a sufficient thickness when used as a conductive portion, can ensure its shape and conductivity, etc., and can also ensure high reliability in connection ^ (5) in the seventh embodiment A printed wiring board is manufactured by using a copper-clad laminate 705 formed by attaching copper foil 709 with a thickness of 0.5em to 7.0 on both sides of an insulating base material 704_. When this copper-plated laminate 705 is used, the residue can be substantially completely removed (^) by a soft residue-removing treatment, and a copper bottom layer 706 of an appropriate thickness can be easily and surely formed. Therefore, the steel-clad laminate 705 is an extremely suitable material when the above-mentioned manufacturing method is used to obtain an excellent printed wiring board 701. In addition, the seventh embodiment can be modified as follows.

P.126 407453 V. Description of the Invention (123) This is the embodiment of the seventh embodiment. For example, the two panels in the embodiment of the embodiment can be used not only as a board, but also the circuit board 701 shown in FIG. 54 can be used as the core-based circuit board 21 ^ In addition, the same as the first change An exemplary multilayer printed board is used to produce the same circuit board as shown in FIG. 9 as the basic base board 3 丨. In addition to the modified multi-layer printing line, in addition to copper-plated laminate 705, tin boxes, gold boxes, silver boxes, platinum and Λ use bells such as Ming box, Μ ^, and platinum Various metal-plated I plates of metals such as nickel foil are used to manufacture printed wiring boards 700i. The residue method described in the seventh embodiment can be performed by a dry method such as the electric method and the like. In the first plating process, a thin coating can also be formed by using an electroless plating bath other than an electroless copper plating bath, such as an electroless solder plating layer, an electroless gold electroplating layer, and an electroless palladium plating layer. In the second plating process, a thick coating can also be formed by using an electrolytic electroforging bath other than the electrolytic copper electroforging bath, such as an electrolytic recording chain layer, an electrolytic chromium bond layer, and an electrolytic gold plating layer. The thin-coated electroless plated layer, the thick-coated electrolytic plated layer, and the bottom layer do not need to be composed of the same kind of metal as in the embodiment, and they also call for a combination of dissimilar metals. Such as using subtraction

Next, in addition to the technical ideas described in the scope of the patent application, the technical ideas summarized in the above-mentioned embodiments are necessary to list the corresponding effects as follows as follows. (1) On a printed circuit board with a conductor pattern Page 127 407453 V. Description of the invention (124)

The medium is characterized in that the above-mentioned conductor pattern is composed of the following. A copper having a thickness of 0.2 vm to 2.5 〆m, which is derived from a copper box with a thickness of G attached to an insulating substrate, is formed on the above. The thin copper layer on the copper base layer has a thickness of 0.2 # 111 ~ 2.5 / ^ and a thin steel electroplated layer; and a thick coated electrolytic steel plated layer having a thickness of 8. or more formed on the thin coated electroless copper electroplated layer. Therefore, "two words based on the invention described in the second technical idea 1" can provide a printed wiring board having extremely high reliability and high pattern density in terms of reliability, formability, and precision in pattern formation. (2) A multilayer printed wiring board is constructed by using one of the printed wiring boards as described in the technical idea 1 as the core substrate. Therefore, according to the invention described in the technical idea 2, it is possible to provide a high-functionality and high-density printed wiring board β that is excellent in reliability, cost performance, and precision in pattern formation. (3) Use such as One of the printed wiring boards described in the technical idea 1 serves as a base substrate to constitute a laminated multilayer printed wiring board. Therefore, according to the invention described in the technical idea 3, it is possible to provide a printed wiring board which is excellent in reliability, cost performance, and precision in pattern formation, and has high performance and high density. (4) A copper-plated laminate composed of a copper foil having a thickness of 0.5 βm to 7.0 μm is attached to both sides of the insulating substrate. Therefore, according to the invention described in the technical idea 4, it is possible to provide an appropriate material for implementing the above-mentioned manufacturing method to obtain an excellent printed wiring board. (5) Glass with impregnated epoxy resin, polyimide resin or BT resin

Page 128 V. Description of the invention (125) Both sides of the base material of the glass filling cloth are bonded with a steel sheet made of copper with a thickness of 10 mm. Therefore, 'if it is based on the invention described in the technical idea 5', an appropriate material can be provided for implementing the above-mentioned manufacturing method to obtain an excellent printed wiring board. (6) In one of the technical thoughts 1 and 2, the residue removal process is carried out with a residue removal liquid on the condition that the conductive metal foil does not disappear. (7) The residue removal process is performed by using a residue removal liquid on the condition that the thickness of the conductive metal foil is reduced to about 1/1/10 to 1/2 of the original thickness.

(8) The printed wiring board having a conductor pattern formed by the subtractive method is characterized in that the above-mentioned conductor pattern has a structure including: derived from an extremely thin conductive metal foil adhered to an insulating substrate And a plating layer formed on the above bottom layer. (9) In a printed circuit board having a conductor pattern formed by using a subtractive layer, 'characterized in that: said conductor pattern has a constitution including: from a thick sound adhered to an insulating substrate, n With a conductivity of 0.5 to 5.0, the thickness derived from the foil is 0.2, on ^ ^. M. B Wm ~ 2.0 // ΙΠ the bottom layer, a thin coating recording layer formed on the bottom layer of the upper,坫 address treatment ^ w, and a thick coating plating layer formed on the thin coating plating (μ). Text &amp;

Chapter 129

Claims (1)

407453 VI. Application Patent Scope 1. A method for manufacturing a multilayer printed wiring board, which includes at least the following processes (1) to (5): (1) The squeezing process is used to form an interlayer resin insulation layer on which a metal film has been formed. The resin is pressure-bonded on the conductor circuit forming substrate; (2) &gt; The specialization process' is to thin the above-mentioned metal film by using the last name engraving. (3) The opening setting process is to set an opening on the metal film; (4) The opening setting process for the formation of the via hole is to set the opening for the formation of the via hole by using laser irradiation to remove the resin for the interlayer resin insulation layer exposed from the opening; and (5) the process of forming the via hole, The above-mentioned openings for the formation of the via holes deposit a plated conductor to form via holes. 2. A method for manufacturing a multilayer printed wiring board, which includes at least the following processes (1) to (8): (1) Pressure bonding process is a process of forming an interlayer resin insulation layer on which a metal film has been formed, and then bonding the resin to a conductor circuit. Formed on the substrate; (2) Thinning process' refers to thinning the above metal film by etching: (3) Opening process, which provides openings on the metal film; (4) Opening process for formation of via holes Is to use laser light to remove the interlayer resin insulating layer forming resin exposed by the opening and set the opening for the formation of the interlayer hole; (5) the electroless plating film forming process is based on the above-mentioned conductor electric honeycomb forming substrate Forming electroless plating film; Page 130 VI. Application for Patent Range 蜢 077 3> (6) Electroplating photoresist forming process is to form electroplating photoresist on the above-mentioned conductor circuit forming substrate; (7) Electrolytic plating process is based on the above electroplating photoresist The unformed part of the resistance is subjected to electrolytic plating; and (8) the removal process is to remove the above-mentioned plating photoresist first, and then remove the metal film and electroless copper plating film under the resistance of the electric mine by etching. 3. The method for manufacturing a multilayer printed wiring board according to item 1 or item 2 of the scope of the patent application, wherein the metal film is a copper foil. 4. The method for manufacturing a multilayer printed wiring board according to item 1 or item 2 of the scope of the patent application, wherein the thickness of the metal film in the process of thinning the metal film by etching is 5 to 0.5 # tn. 5. A method for manufacturing a multilayer printed wiring board, including at least the following processes (1) to (4): (1) pressure bonding process, which is to form an interlayer resin insulation layer of a metal film having a thickness of 5 to 0.5 The resin for forming is adhered to the conductor circuit forming substrate; (2) the opening setting process is to set an opening on the metal film; (3) the opening setting process for the formation of the via hole is to use laser irradiation to remove the opening. The exposed interlayer resin insulating layer forming resin is provided with an opening for forming an interlayer hole; and (4) the interlayer hole forming process is to deposit a plated conductor at the above-mentioned opening for forming an interlayer hole to form an interlayer hole. 6. A method for manufacturing a multilayer printed wiring board, the multilayer printed wiring board is formed by forming a lower-layer conductor circuit on a substrate, and Page 131 407453 6. Scope of patent application '--- An insulating resin layer and an upper conductor circuit are arranged on the upper side, and the above lower conductor circuit and the above upper conductor circuit are connected with each other via vias, and the manufacturing method includes the following steps: u The above-mentioned lower-layer conductor circuit is formed on the substrate, followed by providing the above-mentioned insulating resin layer on the above-mentioned lower-layer conductor circuit, and at the same time forming a roughened surface on the surface of the above-mentioned insulating resin layer, and then forming a portion provided to expose the roughened surface. After opening the metal layer, and irradiating the roughened surface exposed by the opening with laser light to remove the insulating resin layer to form an opening for a via hole, the upper conductor circuit and the via hole are provided: 7. For example, the method of manufacturing a multilayer printed wiring board as described in item 6 of the scope of the patent application, wherein the above-mentioned insulating resin layer contains particles that can be dissolved by an acid or an oxidizing agent, and the particles can be dissolved by using the above-mentioned acid or the oxidizing agent to The roughened surface is provided on the surface of the insulating resin layer. 8 · A method for manufacturing a multilayer printed wiring board, the multilayer printed wiring board is for forming a lower-layer conductor circuit on a substrate, and an insulating resin layer and an upper-layer conductor circuit are provided on the lower-layer conductor circuit, and the above-mentioned lower-layer conductor circuit and the above-mentioned The upper conductor circuits are connected by via holes. The manufacturing method includes the following steps: forming the lower conductor circuit on the substrate; secondly, a roughened layer is provided on one side and the insulation is formed on the roughened layer. The metal and resin foils of the resin layer are laminated by bringing the above-mentioned insulating resin layer into contact with the above-mentioned lower conductor circuit and integrating them by heating and compression, and then forming a part of the above-mentioned metal foil by etching. Opening to expose the roughened surface of the insulating resin layer, and to use the roughened surface exposed through the opening Page 132 407453 VI. Scope of patent application ^ -------- After the laser light is irradiated to remove the above-mentioned insulation opening, the above-mentioned upper conductor circuit and the via hole are described. 9. The manufacturing method of multilayer printed wiring according to item 7 or item 8 of the patent scope, wherein the roughened surface has a maximum roughness (R j) of 0.001 to 5 # m. 10. The method for manufacturing a multilayer printed wiring board according to item 6, 7, or 8 of the scope of Shen Qing's patent, wherein the above-mentioned laser light is a carbon dioxide gas laser. 11. The method for manufacturing a multilayer printed wiring board according to item 6, 7, or 8 of the scope of application for a patent, wherein a roughened surface 8 0 1 2. — A multilayer printed wiring board is provided on the surface of the above-mentioned lower-layer conductor circuit. Its structure is to form a conductor circuit on a substrate, and provide an interlayer resin insulation layer on the conductor circuit. At the same time, an opening for a via hole is formed on the interlayer resin insulation layer. The other conductor circuit of the via hole is characterized in that: the surface of the conductor circuit is roughened by using an etching solution containing a second network complex and an organic acid, and at the same time, an inner wall of the opening for the via hole is formed. Streaks are formed. 13. —A method for manufacturing a multilayer printed wiring board 'includes the following steps ① a process of forming a conductor circuit; ② a process of providing an interlayer resin insulating layer' is to provide an 'interlayer resin insulating layer' on the above-mentioned conductor circuit; ③ a via hole is provided The process of opening is performed by irradiating laser light. 407453 VI. Scope of patent application-/ The above-mentioned interlayer resin insulation layer is provided with openings for interlayer holes; and ④ formation: the process of other conductor circuits with interlayer holes is to form a dielectric layer on the above interlayer resin insulation layer The other conductor circuit of the hole is characterized in that: before carrying out the process described in ②, the surface of the conductor circuit is roughened by using a etch solution containing a second copper complex and an organic acid. 1 4 · The method for manufacturing a multilayer printed wiring board as described in item 2 of the M Patent Fanyuan, wherein the roughening treatment performed on the surface of the conductor circuit is based on the second steel complex and organic The acid etching solution is spray-washed on the surface of the conductive circuit, or is the conductive circuit contained in the foaming condition? Text in the above shoe engraving solution. 1 j. A type of multilayer printed wiring board is formed by laminating an interlayer resin insulation layer and a conductive layer i f &quot;, and is formed by forming a metal film on a bayonet hole formed by the interlayer resin insulation layer. The interlayer hole is used to connect between the layers, and is characterized in that a stripe-shaped unevenness is formed on the side wall of the through hole. Basin 16 ‘The multilayer printed wiring board described in item 15 of the scope of the patent application, the above-mentioned interlayer resin insulation layer is composed of a thermosetting resin or a composite of a thermosetting resin and a thermopure resin. 17. Multi-layer printing according to item 15 or item 16 of the scope of patent application ¢), road board ', wherein the above-mentioned interlayer resin insulating layer contains a propylene-based monomer. 18 · A method for manufacturing a multilayer printed wiring board, including at least the following processes (a) to (d): (a) a process for forming a conductor circuit; Chapter 134 --- 407453____ Sixth patent application scope (b) The process of coating resin is to coat the above-mentioned conductor circuit; (C) The process of forming stripe-shaped unevenness is formed by irradiating the resin with carbon dioxide gas laser It can be passed to the process of filling the through hole of the conductor circuit by 'irradiating the side carbon dioxide gas laser perpendicularly to the above conductor circuit under the resin' and by the interference generated by the reflected wave and incident wave reflected by the conductor circuit ' Stripe-shaped unevenness is formed on the side wall of the through hole; and (d) a process of forming a via hole, which is covered with a metal on the through hole to form a via hole. 19 · The multilayer printed wiring board according to item 18 of the scope of the patent application, wherein the resin is composed of a thermosetting resin or a composite of a thermosetting resin and a thermoplastic resin. 20 * The multilayer printed wiring board described in item 18 or item 19 of the scope of the patent application, wherein the above-mentioned process for forming a via hole includes applying a non-electrolytic steel plating film to the through hole, and then forming a photoresist, A process of forming an electrolytic plating film on the non-formed portion of the photoresist by energizing the electroless electro-ore film. 2 1 · The multi-layer printed 'road board' as described in item 18 or item 19 of the scope of patent application, wherein the interlayer resin insulating layer contains an acrylic monomer. 22. A method of manufacturing a printed wiring board, including at least the following processes (&amp; A, C b): The process of forming a solder photoresist layer is to form a solder photoresist layer on the surface of a substrate on which a conductor has been formed; and (b) The process of penetrating through holes is to use laser to irradiate the welding Page 135 4Q7453_____ VI. Scope of patent application The tin photoresist layer is provided with a through-hole that can pass to the above-mentioned conductor circuit. d ice 23. The method of manufacturing a printed circuit board as described in item 22 of the scope of patent application, wherein the surface of said conductor circuit contains a roughened metal layer. 24. The printed circuit board system described in item 22 of the scope of patent application = method, wherein after the above-mentioned process (b), 'the process of setting a bump made of a low-melting-point metal on the above-mentioned through hole (c ) °, 2 5. The method of assembling printed wiring boards as described in item 22 of the scope of patent application, wherein in the above-mentioned process of forming the through-holes, a single-mode light is irradiated to form a diameter of 300 / zm ~ 650 through holes. 26. The method of making a printed circuit board as described in item 22 of the scope of the patent application, wherein in the above-mentioned process of forming the through-holes, 'multi-mode laser irradiation is used to form a diameter of 5 0 # m ~ 3 0 0 m through hole. 27. The method for manufacturing a printed circuit board according to item 22, 23, 24, 25, or 26 of the scope of patent application, wherein in the system f for forming the above-mentioned through hole, the carbon dioxide gas laser is directed vertically toward the solder photoresist The above-mentioned conductive circuit under the layer is irradiated, and by the interference of the reflected wave and the incident wave reflected by the conductor circuit, a striped unevenness is formed on the side wall of the through hole. 28. The method for manufacturing a printed circuit board according to item 27 of the scope of the patent application, wherein the process of forming the bumps is to set a metal film on the through-holes in which stripe-shaped unevenness has been formed on the side wall, and then fill the low Melting point metal. 2 9. —A printed wiring board is formed by forming a solder photoresist on the surface of a substrate on which a conductor circuit has been provided, and is characterized in that: a side wall of a through hole provided through the solder photoresist layer is formed; Striped bumps. Page 136 6. The scope of patent application '** ^ 30. The printed circuit board as described in item 29 of the scope of patent application, wherein a low-melting-point metal is formed by a metal film located in the aforementioned through hole. Bump. 31. The printed wiring board according to item 29 or item 30 of the scope of patent application, wherein the solder resist layer is made of a thermosetting resin or a composite of a thermosetting resin and a thermoplastic resin. 32. The printed wiring board according to claim 29 or 30, wherein a roughened layer is formed on the surface of the conductor circuit. 3 3 · The printed circuit board as described in the scope of patent application No. 24, 28 or 30, wherein the above-mentioned low melting point metal can be selected from at least 1 of Sn / Pb, Ag / Sn and Ag / Sn / Cu. Species. 34. A method for manufacturing a multilayer printed wiring board is to set a through-hole by laser processing on both sides of a copper-clad laminate, and conduct the through-hole to conduct electricity to form a core substrate with a through-hole. An interlayer resin insulation layer and a conductor circuit are formed on the core substrate, which are characterized in that the thickness of the copper foil on the two-sided copper-clad laminate is less than 12 in.m. 35. The method for manufacturing a multilayer printed wiring board according to item 34 of the scope of the patent application, wherein the above laser processing uses a carbon dioxide gas laser. 36. The method for manufacturing a multilayer printed wiring board according to item 34 or item 35 of the patent application park, wherein the above laser processing uses a short pulse carbonic acid gas laser of 40mj, 10-4 to 10_8 seconds . 37 · —A substrate for forming a through-hole ’The substrate is formed with through-holes on both sides of a copper-clad laminate and the through-holes are conductively formed, and are characterized by: 〃 Page 137 407453 VI. Patent application scope The above through-holes are formed in a cone shape ° 38. The poorly perforated formation substrate as described in item 37 of the application for patent scope, wherein the above-mentioned cone shape is oriented toward the substrate with the aperture of the through-hole Formed in such a way that one direction becomes larger. 39. The through-hole forming substrate according to item 37 of the scope of the patent application, wherein the above-mentioned cone shape is formed in such a manner that the cross-section of the through-hole is bank-shaped. 4 0. A multilayer printed wiring board having through-holes on both sides of a copper-clad laminate and forming an interlayer resin insulation layer and a conductor circuit on at least one side of a substrate on which a through-hole having been electrically conductive is formed. It is characterized in that the above through-holes are formed in a cone shape β 41. The multilayer printed bug circuit board described in item 40 of the scope of the patent application, wherein the thickness of the copper foil and the electroplated layer of the copper-clad laminate is 10 to 30 μm ° 4 2. The multilayer printed wiring board according to item 40 or item 41 of the patent application scope, wherein the taper is formed in such a manner that the hole diameter of the through hole becomes larger in one direction of the substrate. 4 3. The multilayer printed wiring board according to item 40 or item 41 of the scope of the patent application, wherein the above-mentioned tapered shape is formed in such a manner that the cross section of the through hole is bank-shaped. 44. The multilayer printed wiring board according to item 40 or 41 of the scope of the patent application, wherein the through hole is filled with a filler. 45. — A multilayer printed wiring board, which is formed by interlayer resin insulation, layer and conductor circuit interaction layer on a substrate on which a through-hole and a conductor circuit have been formed. Page 138 407453 6. The scope of the patent application is superimposed. The conductor circuits of the different layers are electrically connected to each other through the interlayer holes provided in the interlayer resin insulation layer, which is characterized in that the above substrate is made of Tg Glass epoxy substrate made of epoxy resin with a temperature above 190 ° C. 4 6 · — A method for manufacturing a printed wiring board, the printed wiring board having a plated through hole and a conductor pattern formed by a subtractive method, including the following steps: 〇 · a process of forming a through hole for forming a through hole, It is formed at a predetermined position of a key metal laminate formed by bonding a conductive metal foil with a thickness of 0 · 5 // m to 7.0 μm to both sides of an insulating base material to form a through-hole. The process of forming holes; the process of removing residues is to dissolve and remove the residues in the holes for forming through-holes; the first electroplating process is based on the bottom layer derived from the conductive metal foil and the inner wall surface of the holes for forming through-holes A thin coating plating layer is formed on the substrate; a second plating process is to form a thick coating plating layer at the exposed portion of the same curtain cover after the curtain is formed on the thin coating plating layer; and The conductive patterns are separated from each other by peeling the above-mentioned mask and then performing a single engraving 'to remove the thin coating plating layer and the bottom layer located under the same-mask. Ni, Sn 'Au' Ag, Pt 4 for printed circuit boards 7. The method according to item 46 of the scope of patent application, wherein the metal foil is prepared by selecting at least one of CU 'and A1 . 139 Yin 407453 VI. Patent Application Fanyuan 4 8. The manufacturing method of the printed circuit board described in item 46 of the scope of the patent application 'wherein the electroless mineral bath is used in the above first clock process' and In the second electroplating process, an electrolytic electron microscope bath is used. 4 9. The method for manufacturing a printed wiring board according to item 46 of the scope of the patent application, wherein in the above-mentioned first electroplating process, an electroless copper electroplating bath is used to form a copper electroplating having a thickness of 0.2ym to 2.5 / zm. In the second electro-diagnosis process, an electrolytic copper plating bath is used to form a copper plating layer having a thickness of 8.Oym or more. 50. The method for manufacturing a printed wiring board according to item 46, 47, 48, or 49 of the scope of the patent application, wherein the above-mentioned process of separating and disconnecting the conductor pattern by etching is performed in a thickness formed by the above-mentioned second plating process. This was performed in a state where the photoresist was not provided on the S layer of the covered electron microscope. 51. — Kind of printed wiring board 'The printed wiring board has a conductor which is characterized by: an intermediary system' an upper conductor pattern which comprises: a thickness provided on an insulating substrate ^ 〇 · 2 ~ 3. 0 / Z m 的 金属The bottom layer and the metal bottom formed on the above: a plating layer. -Zhangshang 52. — A printed wiring board having a conductor, which is characterized by: The above-mentioned conductor pattern has a constitution including: provided on an insulating substrate and having a thickness of 0 2 &quot; m ~ 2 5 ,, m —Human layer; 勹 1 &quot; &quot; A metal underplating layer of 2 · 5 · πι is formed on the above metal base layer with a thickness of 0 / zm 407453 6. Scope of patent application and plating layer with a thickness of 8.0 or more formed on the above plating layer BS1 Page 141