JP2009302588A - Multilayer printed wiring board, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To present a multilayer printed wiring board of which adhesive property between an interlayer resin insulating film and a conductor circuit, formability of a fine pattern, signal propagating property in a high frequency bandwidth, solder heat resistance, and further warping resistance and crack resistance for its substrate are excellent, and to provide a manufacturing method thereof. <P>SOLUTION: In the multilayer printed wiring board constituted by interlayer resin insulating layers and conductor circuits alternatively laminated on both the sides of the substrate, the conductor circuit on the top side and the conductor circuit on the bottom side are connected through via-holes. The multilayer printed wiring board is manufactured by forming a metal layer on at least a part of the surface of the conductor circuit on the top side or the bottom side, which is provided with one or more metals selected from Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Os, Ir, Pt, Au, Rf, Db, Sg, Bh, Hs, Mt, Ds, Rg, Al and Sn. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a multilayer printed wiring board using a resin substrate, in particular, excellent adhesion between an interlayer resin insulating layer and a conductor circuit, easy to form a fine pattern, signal propagation in a high frequency band, solder heat resistance. This is a proposal for a multilayer printed wiring board which is excellent in warpage and crack resistance of a substrate and a method for producing the same.

  In recent years, in the field of package substrates, with higher signal frequencies, low dielectric constants and low dielectric loss tangents have been demanded. Correspondingly, substrate materials have changed from conventional ceramics to resins. The reality is changing.

Under such a background, a printed wiring board using a resin substrate has been developed. For example, in Japanese Examined Patent Publication No. 4-55555, epoxy acrylate is used as an interlayer resin insulating layer on a glass epoxy substrate on which a circuit is formed, an opening for a via hole is provided by photolithography, and the inner wall surface of the opening is roughened. Discloses a method of forming a conductor circuit and a via hole by applying electroless plating after providing a plating resist.
However, since the interlayer resin insulation layer made of a resin such as epoxy acrylate has poor adhesion to a conductor circuit that is a metal, at least one of the surface of the insulation layer and the conductor circuit must be roughened. However, this means that when a high-frequency signal is propagated, the signal propagates only on the conductor circuit surface portion roughened by the skin effect. For this reason, there is a problem that noise is generated in the signal due to the unevenness of the surface. This problem is particularly remarkable when using a resin substrate having a low dielectric constant and a low dielectric loss tangent that can propagate a signal having a higher frequency than a ceramic substrate.

  In order to solve this problem, in Japanese Patent Laid-Open Nos. 7-45948 and 7-94865, a resin is applied to one side of a ceramic substrate or a resin substrate by spin coating or the like, and a conductive pattern is formed on the resin layer. A technique is disclosed in which a metal (chromium, nickel, titanium, or the like) for improving adhesion is provided, a copper thin film layer is provided on the metal layer, and a conductor circuit is formed on the copper thin film layer.

  However, these conventional techniques are techniques for forming a resin and a conductor pattern only on one side of the substrate. For this reason, if these conventional techniques are directly applied to the resin substrate, the substrate is warped during a heat cycle or the like, and there is a problem that cracks occur near the interface between the conductor circuit and the resin insulating layer.

  The present invention has been made in order to solve the above-described problems of the resin substrate for multilayer printed wiring boards, and its main purpose is excellent adhesion between the interlayer resin insulation layer and the conductor circuit, and a fine pattern. It is an object of the present invention to provide a multilayer printed wiring board that is easy to form, excellent in signal propagation in a high frequency band, excellent in solder heat resistance, and excellent in warping and crack resistance of a substrate, and a method for manufacturing the same.

As a result of intensive research aimed at realizing the above-mentioned object, the inventors have arrived at the present invention having the following contents. That is, the present invention
Interlayer resin insulation layers and conductor circuits are alternately stacked, and have a build-up layer in which conductor circuits located above and below are connected to each other through via holes , on the uppermost interlayer resin insulation layer and on the uppermost layer On the conductor circuit, in a multilayer printed wiring board in which a solder resist layer having an opening is formed ,
The uppermost conductor circuit includes an electroless plating film formed on the uppermost interlayer resin insulation layer by a semi-additive method, and an electrolytic plating film on the electroless plating film. A metal layer made of Sn is formed on at least a side surface of the upper conductor circuit, and a solder bump is formed on the uppermost conductor circuit exposed from the opening of the solder resist layer. A multilayer printed wiring board.

The multilayer printed wiring board, the uppermost interlayer resin insulation layer, a step of the conductor circuit of the uppermost layer made of the electroless plated film and the electrolytic plated film is formed by a semi-additive method, the uppermost conductor circuit Forming a metal layer made of Sn on at least the side without roughening the surface;
Forming a solder resist layer so as to cover the metal layer formed on the uppermost conductor circuit, and forming an opening in the solder resist layer to expose a part of the surface of the uppermost conductor circuit; And a step of forming solder bumps on the surface of the uppermost conductive circuit exposed from the opening .

In the present invention, the uppermost conductor circuit is preferably connected to a lower conductor circuit through a via hole, and the electroless plating film and the electrolytic plating film forming the uppermost conductor circuit Is preferably made of copper.
Further, the surface of the uppermost conductor circuit is preferably flat, and the surface of the uppermost conductor circuit is preferably not roughened.
Moreover, it is preferable that the said soldering resist layer contains an epoxy resin.
Contact name the applicant earlier, the Japanese Patent Laid-Open No. 7-147483, for example by a coating formed by spin coating resin on one surface of the ceramic substrate or a resin substrate, and forming a conductor circuit on the resin layer, the conductor circuit on Although a technique for forming a Ni layer or the like has been proposed, the technique for forming a resin layer or the like only on one side of the substrate is different from the present invention.

  As described above, according to the multilayer printed wiring board of the present invention, it is possible to provide a printed wiring board that is excellent in signal propagation in a high frequency band by flattening the conductor circuit without reducing the adhesion strength of the conductor circuit. it can. In addition, the occurrence of cracks can be suppressed and the reliability of the wiring can be improved. Furthermore, finer wiring can be realized.

(a)-(f) is a figure which shows a part of process of manufacturing the multilayer printed wiring board of Example 1. FIG. (a)-(e) is a figure which shows a part of process of manufacturing the multilayer printed wiring board of Example 1. FIG. (a)-(d) is a figure which shows a part of process of manufacturing the multilayer printed wiring board of Example 1. FIG. (a), (b) is a figure which shows a part of process of manufacturing the multilayer printed wiring board of Example 1. FIG. (a), (b) is a figure which shows a part of process of manufacturing the multilayer printed wiring board of the comparative example 1. FIG.

The multilayer printed wiring board according to the present invention has a build-up layer in which interlayer resin insulation layers and conductor circuits are alternately laminated, and conductor circuits located above and below are connected via via holes , and the uppermost layer In the multilayer printed wiring board in which a solder resist layer having an opening is formed on the interlayer resin insulation layer and the uppermost conductor circuit, the uppermost conductor circuit is the uppermost interlayer resin insulation layer. An electroless plating film formed using a semi-additive method and an electroplating film on the electroless plating film, and a metal layer made of Sn is formed on at least the side surface of the uppermost conductor circuit. A solder bump is formed on the uppermost conductor circuit exposed from the opening of the solder resist layer.

Metal layer made of the Sn is excellent in adhesion to the layer insulating resin. Therefore, even when the resin substrate is warped, the conductor circuit and the interlayer insulating resin do not peel off. Moreover, since such a structure is formed symmetrically on both sides of the resin substrate, the amount of warpage of the substrate itself is reduced, and therefore occurs near the interface between the conductor circuit and the interlayer insulating resin even during a heat cycle. It is possible to prevent cracking.
Furthermore, if a metal layer made of Sn is formed, the necessary adhesion to the upper layer conductor circuit can be ensured without providing a roughened layer on the surface of the conductor circuit. As a result, signals in the high frequency band can be propagated. However, there is an effect that no propagation delay occurs.
When the conductor circuit is formed by etching, the metal layer described above acts as an etching resist and contributes to the formation of a fine pattern.

  In addition, as for the thickness of the said metal layer, 0.02 micrometer-0.2 micrometer are desirable. The reason for this is that by setting the thickness to 0.02 μm or more, the adhesion between the interlayer resin insulation layer and the conductor circuit can be secured, and by setting the thickness to 0.2 μm or less, the stress when forming the metal layer by sputtering. This is because it is possible not only to prevent cracks caused by the above, but also to easily remove the metal layer between the conductor circuits which becomes unnecessary after the conductor circuits are formed.

  Another type of metal layer may be further formed on the metal layer as necessary. For example, by forming a nickel layer on the interlayer resin insulation layer and providing a copper layer thereon, non-deposition of plating when forming a conductor circuit can be prevented. These metal layers are formed by methods such as electroless plating, electrolytic plating, sputtering, vapor deposition, and CVD.

  In general, unlike a ceramic substrate or a metal substrate, the resin substrate used in the present invention is easily warped, has poor heat dissipation, and is likely to cause copper migration due to heat storage. In this regard, in the present invention, the metal layer serves as a barrier for preventing migration of copper ions from the copper conductor circuit, and insulation between the layers can be ensured even under humid conditions.

The interlayer resin insulation layer in the present invention is preferably composed of a thermosetting resin, a thermoplastic resin, or a composite resin thereof. As the thermosetting resin, it is desirable to use one or more selected from thermosetting polyolefin resin, epoxy resin, polyimide resin, phenol resin, bismaleimide toazine resin and the like.
As the thermoplastic resin, it is desirable to use engineering plastics such as polymethylpentene (PMP), polystyrene (PS), polyether sulfone (PES), polyphenylene ether (PPE), and polyphenylene sulfide (PPS).

（２）．下記構造式で示される繰り返し単位のうちの異なる２種類以上が共重合したものからなる樹脂。

（３）．下記構造式で示される繰り返し単位を有し、その分子主鎖中には、二重結合、オキシド構造、ラクトン構造、モノもしくはポリシクロペンタジエン構造を有する樹脂。

（４）．前記（１），（２），（３）の群から選ばれる２種以上の樹脂を混合した混合樹脂、前記（１），（２），（３）の群から選ばれる樹脂と熱硬化性樹脂との混合樹脂、または前記（１），（２），（３）の群から選ばれる樹脂が互いに架橋した樹脂。なお、本発明で「樹脂」という場合は、いわゆる「ポリマー」および「オリゴマー」を包括する概念である。 In the present invention, it is most preferable to use a polyolefin-based resin having a structure as shown in the following (1) to (4) as the interlayer resin insulating layer.
(1). A resin comprising one type of repeating unit represented by the following structural formula.

(2). A resin comprising a copolymer of two or more different types of repeating units represented by the following structural formula.

(3). A resin having a repeating unit represented by the following structural formula and having a double bond, an oxide structure, a lactone structure, a mono- or polycyclopentadiene structure in the molecular main chain.

(4). A mixed resin obtained by mixing two or more resins selected from the group of (1), (2), and (3), a resin selected from the group of (1), (2), and (3) and thermosetting. Resin mixed with resin, or resin in which resins selected from the group of (1), (2) and (3) are cross-linked with each other. In the present invention, “resin” is a concept encompassing so-called “polymer” and “oligomer”.

Hereinafter, the resins (1) to (4) will be described in more detail.
a. In the resins (1) to (3), the alkyl group employed as X in the repeating unit is selected from methyl group, ethyl group, propyl group, isopropyl group, butyl group, isobutyl group, and t-butyl group. It is desirable that it is at least one or more.
b. Examples of the unsaturated hydrocarbon C2~C3 employed as X in the repeating _{unit, CH 2 = CH-, CH 3} CH = CH-, CH 2 = C (CH 3) -, at least selected from acetylene group One or more types are desirable.
c. The oxide group employed as X in the repeating unit is preferably an epoxy group or a propoxy group, and the lactone group is at least one selected from a β-lactone group, a γ-lactone group, and a δ-lactone group. It is desirable to be.

  The reason why the C2 to C3 unsaturated hydrocarbon, oxide group, lactone group and hydroxyl group are employed as X in the repeating unit is high in reactivity, and resins (in this case, oligomers) containing these reactive groups It is because it is easy to bridge | crosslink. Furthermore, the reason why n is 1 to 10,000 is that when n exceeds 10,000, the solvent becomes insoluble and difficult to handle.

In the resin of (3), as the double bond structure in the main chain of the molecule, the repeating unit represented by the following structural _{formula, - (CH = CH) m} - or _{- (CH 2 -CH = CH-} CH 2 ) It is preferable that m- repeating units are copolymerized. Here, m is 1 to 10000.

  In this resin (3), the oxide structure of the molecular main chain is preferably an epoxy structure. Further, the lactone structure of the molecular main chain is preferably a β-lactone or γ-lactone structure. Furthermore, it is desirable to adopt a structure selected from cyclopentadiene and bicyclopentadiene as the mono- and polycyclopentadiene of the molecular main chain.

  In the copolymerization, when the repeating unit is alternately copolymerized as ABAB ..., when the repeating unit is randomly copolymerized as ABAABAAAAB ..., or when block copolymer is used as AAAAABBBB ... There is.

Next, the resin (4) will be described. The resin (4) is a mixed resin obtained by mixing two or more kinds of resins selected from the group (1), (2), (3), and the group (1), (2), (3). A resin selected from the group consisting of a thermosetting resin and a resin selected from the group of (1), (2), and (3) are cross-linked resins.
Among these, when two or more kinds of resins selected from the group of (1), (2) and (3) are mixed, the resin powder is dissolved in an organic solvent or mixed by hot melting.
Also, when a resin selected from the group of (1), (2), and (3) and a thermosetting resin are mixed, the resin powder is dissolved in an organic solvent and mixed. As the thermosetting resin to be mixed in this case, it is preferable to use at least one selected from thermosetting polyolefin resin, epoxy resin, phenol resin, polyimide resin, and bismaleimide triazine (BT) resin.
Further, when the resins selected from the group of (1), (2), and (3) are cross-linked to each other, C2 to C3 unsaturated hydrocarbon, oxide group, lactone group, hydroxyl group, and two in the molecular main chain. A double bond, an oxide structure, or a lactone structure is used as a bond for crosslinking.

  In addition, as an example of the thermosetting polyolefin resin employed in the present invention, trade name 1592 manufactured by Sumitomo 3M Ltd. can be used. Moreover, as an example of a thermoplastic polyolefin resin having a melting point of 200 ° C. or higher, trade name TPX (melting point 240 ° C.) manufactured by Mitsui Chemicals, trade name SPS (melting point 270 ° C.) manufactured by Idemitsu Petrochemical, etc. can be used. TPX is a resin in which X in the repeating unit is an isobutyl group, and SPS is a resin having a syndiotactic structure where X is a phenyl group.

Since such a polyolefin-based resin is excellent in adhesiveness with a conductor circuit, it is not necessary to roughen the surface of the underlying conductor circuit, so that a flat conductor circuit can be formed.
This polyolefin resin has a dielectric constant of 3 or less and a dielectric loss tangent of 0.05 or less, which is lower than that of an epoxy resin, and has no propagation delay even with a high frequency signal. In addition, this polyolefin resin is not inferior in heat resistance to the epoxy resin, and the conductor circuit is not peeled even at the solder melting temperature. In addition, since the fracture toughness value is large, cracks starting from the boundary between the conductor circuit and the interlayer resin insulation layer do not occur during the heat cycle.

Next, an example in which the method for producing a multilayer printed wiring board of the present invention is applied to the production of a multilayer printed wiring board will be described.
(1) First, a wiring board in which a lower conductor circuit is formed on the surface of a resin board is manufactured. As the resin substrate, it is desirable to use a resin substrate containing inorganic fibers, such as a glass cloth epoxy substrate, a glass cloth polyimide substrate, a glass cloth bismaleide-triazine resin substrate, a glass cloth fluororesin substrate, or the like. Is preferred.
The lower conductor circuit is formed by etching a copper clad laminate having copper foils on both sides of the resin substrate. Then, a through-hole is drilled in the substrate, and electroless plating is applied to the wall surface of the through-hole and the copper foil surface to form a through-hole provided with a conductor. Here, copper plating is preferable as the electroless plating method. Note that a substrate such as a fluororesin substrate with poor plating coverage is subjected to surface modification such as treatment with a pretreatment liquid made of organometallic sodium and plasma treatment.

Next, electrolytic plating is performed for thickening. As this electrolytic plating, copper plating is preferable.
The inner wall of the through hole and the surface of the electrolytic plating film may be roughened to form an interlayer insulating layer surface. Examples of the roughening treatment include blackening (oxidation) -reduction treatment, spray treatment with a mixed aqueous solution of an organic acid and a cupric complex, and treatment with copper-nickel-phosphorous needle-like alloy plating.
Moreover, it is also possible to fill the through holes with a conductive paste as necessary, and to form a conductor layer covering the conductive paste by electroless plating or electrolytic plating.

(2) A resin insulating layer is formed on both surfaces of the wiring board produced in (1). This resin insulation layer functions as an interlayer resin insulation layer below the multilayer printed wiring board. This resin insulation layer is formed by applying an uncured liquid or laminating a film-like resin by hot pressing.

(3) Next, an opening is provided in the lower interlayer resin insulation layer to ensure electrical connection with the lower conductor circuit. The opening is made by laser light or exposure development processing. Examples of the laser light used at this time include a carbon dioxide laser, an ultraviolet laser, and an excimer laser. And after drilling with a laser beam, a desmear process is performed. The desmear treatment can be performed by using an oxidizing agent made of an aqueous solution such as chromic acid or permanganate, or may be treated by oxygen plasma, a mixed plasma of CF ₄ and oxygen, corona discharge, or the like. Further, the surface can be modified by irradiating with ultraviolet rays using a low-pressure mercury lamp.
In particular, mixed plasma of CF ₄ and oxygen is advantageous because hydrophilic groups such as hydroxyl groups and carbonyl groups can be introduced on the resin surface, and subsequent CVD and PVD treatment is easy.

(4) On the surface of the lower interlayer resin insulation layer provided with the opening in (3) above, from the 4th to 7th group metals (excluding Cu), Al and Sn, from Group 4A to Group 1B A thin metal layer made of one or more selected metals is formed by a plating method, a PVD method, or a CVD method.
As the PVD method, vapor deposition methods such as sputtering and ion beam sputtering are effective. Further, as a CVD method, PE-CVD (Plasma Enhanced CVD) using an organic metal (MO) such as allylcyclopentadiphenylpalladium, dimethylgold acetylacetate, tin tetramethylacrylonitrile, dicobalt octacarbonylacrylonitrile, etc. Is preferred.

(5) Next, a metal layer of the same type as the electroless plating film in the next step is formed on the metal layer formed in (4) by sputtering or the like. This is to improve the affinity with the electroless plating film. Specifically, it is desirable to provide a copper layer by sputtering.

(6) Next, electroless plating is performed on the metal layer formed in (5) as necessary. Copper plating is most suitable as electroless plating. The film thickness of electroless plating is preferably 0.1 to 5 μm. The reason for this is to enable etching removal without impairing the function of the electroplating performed later as a conductive layer.
This electroless plating and / or the metals belonging to the 4th to 7th periods in the groups 4A to 1B (excluding Cu), Al,
A thin metal layer made of at least one metal selected from Sn serves as a conductor layer and functions as a plating lead.

(7) A plating resist is formed on the electroless plating film formed in (6). This plating resist is formed by laminating a photosensitive dry film, exposing and developing.

(8) Next, on the electroless plating film after finishing the treatment of (7), it is selected from Group 4A to Group 1B, metals of 4th to 7th period (except Cu), Al, Sn A metal layer made of at least one kind of metal is formed by the above-described plating method, PVD method, or CVD method.
The formation of the metal layer in this step is particularly preferably formed by an electroless plating method.
Thereafter, electroplating is performed using the electroless plating film and the metal layer as plating leads, and a conductor circuit is thickened. The thickness of the electroplated film in this treatment is preferably about 5 to 30 μm.

(9) Thereafter, after removing the plating resist, the electroless plating film and the metal layer immediately below the plating resist are removed by etching to form an independent upper conductor circuit. Etching solutions used in this step include sulfuric acid-hydrogen peroxide aqueous solution, persulfate aqueous solution such as ammonium persulfate, sodium persulfate, potassium persulfate, ferric chloride, cupric chloride aqueous solution, hydrochloric acid, nitric acid, heat Dilute sulfuric acid or the like can be used.
In this etching process, the metal layer functions as an etching resist and is useful for forming an independent conductor circuit such as L / S = 15/15 μm.

(10) Further, if necessary, a thin metal layer made of the above-mentioned metal is formed on the surface of the upper conductive circuit by plating, PVD, or CVD, and (2) to ( By repeating step 9), an upper interlayer resin insulation layer is formed on the upper conductor circuit, and the uppermost conductor circuit is further formed on the upper interlayer resin insulation layer. Get a board.

  In the above description, the semi-additive method is adopted as the method for forming the conductor circuit, but the full additive method can also be applied. In this full additive method, a thin metal layer is formed on the surface of the resin insulating layer by CVD or PVD processing, and then a photosensitive dry film is laminated, or a liquid photosensitive resin is applied, exposed and developed. A plating resist is provided and thickened by electroless plating to form a conductor circuit. Alternatively, after forming a plating resist on the surface of the resin insulation layer, a thin metal layer is provided by CVD or PVD treatment, and the metal layer adhering to the plating resist surface is removed by polishing or the plating resist itself is removed. The conductor circuit can also be formed by performing electroless plating using the metal layer as a catalyst.

(Example 1)
(1) As a core substrate, a BT resin copper-clad laminate (product manufactured by Mitsubishi Gas Chemical Co., Ltd.) in which 18 μm copper foil 2 is laminated on both sides of a 0.8 mm thick substrate 1 made of BT (Biz Maleimide Triazine) resin. Name: HL830-0.8T12D) was used (see FIG. 1 (a)). First, this copper-clad laminate is drilled to form a through hole (see FIG. 1 (b)), and then a palladium-tin colloid is adhered, and electroless plating is performed with an electroless plating aqueous solution having the following composition under the following conditions. Then, an electroless plating film having a thickness of 0.7 μm was formed on the entire surface of the substrate.
[Electroless plating aqueous solution]
EDTA 150g / l
Copper sulfate 20g / l
HCHO 30ml / l
NaOH 40g / l
α, α'-bipyridyl 80mg / l
PEG 0.1g / l
[Electroless plating conditions]
30 minutes at a liquid temperature of 70 ° C

Furthermore, electrolytic copper plating was performed with an electrolytic plating aqueous solution having the following composition under the following conditions to form a lower conductor circuit 2 and a through hole 3 made of an electrolytic copper plating film having a thickness of 15 μm (see FIG. 1C).
(Electrolytic plating aqueous solution)
Sulfuric acid 180 g / l
Copper sulfate 80 g / l
Additive (product name: Kaparaside GL, manufactured by Atotech Japan)
1 ml / l
[Electrolytic plating conditions]
Current density 1A / dm ²
Time 30 minutes Temperature Room temperature

(2) The substrate 1 thus formed with the underlying conductor circuit (including the through hole 3) is washed with water and dried, and then NaOH (20 g / l), NaClO2 (50 g / l) are used as an oxidation bath (blackening bath). ), An aqueous solution of Na ₃ PO ₄ (15.0 g / l), and subjected to an oxidation-reduction treatment using an aqueous solution of NaOH (2.7 g / l) and NaBH ₄ (1.0 g / l) as a reducing bath . A roughening layer 4 was provided on the entire surface of the conductor circuit 2 (including the through hole 3) (see FIG. 1 (d)).

(3) Next, the conductive paste 5 containing copper particles was filled into the through holes 3 by screen printing, and dried and cured. Then, the conductive paste 5 protruding from the roughened layer 4 and the through hole 3 on the upper surface of the lower conductor circuit 2 is removed by belt sander polishing using # 400 belt polishing paper (manufactured by Sankyo Rikagaku), and further this belt sander Buffing was performed to remove scratches caused by polishing, and the substrate surface was flattened (see FIG. 1 (e)).

(4) An electroless copper plating film 6 having a thickness of 0.6 μm was formed on the substrate surface flattened in (3) above by applying a palladium colloid catalyst according to a conventional method and then performing electroless plating (see FIG. 1 (f)).

(5) Next, subjected to an electrolytic copper plating under the following conditions to form an electrolytic copper plated film 7 having a thickness of 15 [mu] m (see FIG. 2 (a)), thickening of the portion serving upper layer of the conductor circuit 9, and through A portion to be a conductor layer (lid plating layer) 10 covering the conductive paste 5 filled in the hole 3 was formed (see FIG. 2B).
(Electrolytic plating aqueous solution)
Sulfuric acid 180 g / l
Copper sulfate 80 g / l
Additive (product name: Kaparaside GL, manufactured by Atotech Japan)
1 ml / l
[Electrolytic plating conditions]
Current density 1A / dm ²
Time 30 minutes Temperature Room temperature

(6) Commercially available photosensitive dry film is pasted on both sides of the substrate on which the conductor circuit 9 and conductor layer 10 are formed on the upper layer, a mask is placed, and exposure is performed at 100 mJ / cm ² , 0.8% hydrogen carbonate Development processing was performed with sodium to form an etching resist 8 having a thickness of 15 μm (see FIG. 2A).
(7) The portion of the plating film where the etching resist 8 is not formed is dissolved and removed by etching using a mixed solution of sulfuric acid and hydrogen peroxide, and the plating resist 8 is peeled off and removed with 5% KOH. A through-hole covering conductor layer (hereinafter referred to simply as “lid plating layer”) 10 covering the independent upper conductor circuit 9 and conductive paste 5 was formed (see FIG. 2 (b)). .

(8) Next, a 2.5 μm thick roughened layer (concave / convex layer) 11 made of Cu—Ni—P alloy is formed on the entire surface including the side surfaces of the upper conductor circuit 9 and the lid plating layer 10. An Sn layer having a thickness of 0.3 μm was provided on the surface of the roughened layer 11 (see FIG. 2C, the Sn layer is not shown).
The formation method is as follows. That is, the substrate is acid degreased and soft etched, then treated with a catalyst solution comprising palladium chloride and an organic acid to give a Pd catalyst, and after activating this catalyst, copper sulfate 8 g / l, nickel sulfate PH consisting of an aqueous solution of 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant (Nisshin Chemical Industries, Surfinol 465) 0.1 g / l = 9 was plated in an electroless plating bath, and a roughened layer 11 of Cu—Ni—P alloy was provided on the entire surface of the conductor circuit 9 and the lid plating layer 10. Then, using an aqueous solution of tin borofluoride 0.1 mol / l and thiourea 1.0 mol / l, a thickness of 0.3 is formed on the surface of the roughened layer 11 by a substitution reaction of Cu-Sn at a temperature of 50 ° C. and a pH = 1.2. A μm Sn layer was provided (the Sn layer is not shown).

(9) A thermosetting polyolefin resin sheet (manufactured by Sumitomo 3M, trade name: 1592) with a thickness of 50 μm is heated and pressed on both sides of the substrate at a pressure of 10 kg / cm ² while raising the temperature to 50 to 180 ° C. Then, an upper interlayer resin insulation layer 12 made of polyolefin resin was provided (see FIG. 2 (d)).

(10) Next, a via hole opening 13 having a diameter of 80 μm was provided in the upper resin insulating layer 12 made of polyolefin resin by a CO ₂ gas laser having a wavelength of 10.4 μm. Furthermore, the surface of the desmear and polyolefin resin insulation layers was modified by plasma treatment of CF ₄ and oxygen mixed gas. By this modification, hydrophilic groups such as OH groups, carbonyl groups, and COOH groups were confirmed on the surface (see FIG. 2 (e)).
The oxygen plasma treatment conditions are an electric power of 800 W, 500 mTorr, and 20 minutes.

(11) Next, sputtering is performed on the surface of the upper interlayer resin insulation layer 12 made of the polyolefin resin, with Ni as a target, under conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, and time 5 minutes. A thin film was formed. At this time, the thickness of the formed Ni metal layer was 0.1 μm. Further, as shown in FIG. 3 (a), a copper layer having a thickness of 0.1 μm was formed by sputtering on the lowermost Ni metal layer under the same conditions. Note that SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd. was used as an apparatus for sputtering.

(12) Then, the electroless plating of (1) is applied to the substrate after the processing of (11) to form an electroless plating film 14 having a thickness of 0.7 μm (see FIG. 3A). ).

(13) A commercially available photosensitive dry film is pasted on both sides of the substrate on which the electroless plating film 14 is formed in the above (12), and a photomask film is placed, exposed at 100 mJ / cm ² , 0.8% sodium carbonate And a plating resist 16 having a thickness of 15 μm was provided (see FIG. 3B).

(14) The electroplating of (1) was performed to form an electroplating film 15 having a thickness of 15 μm, and the upper conductor circuit 9 portion was thickened and the via hole 17 portion was filled with plating.
Furthermore, it is immersed for 1 minute in an electroless nickel plating solution having a pH of 5 consisting of an aqueous solution of nickel chloride 30 g / l, sodium hypophosphite 10 g / l, and sodium citrate 10 g / l, as shown in FIG. Thus, a nickel plating layer 19 having a thickness of 0.1 μm was formed on the upper part of the opening of the plating resist 16 .

(15) Further, after removing the plating resist 16 with 5% KOH, the Ni film and the electroless plating film 14 under the plating resist 16 are dissolved and removed by etching using a mixed solution of nitric acid and sulfuric acid / hydrogen peroxide. As a result , an upper conductor circuit (including via hole 17) made of Ni film, electroless copper plating film 14 and electrolytic copper plating film 15 is formed on the upper surface of the upper conductor circuit. A nickel plating layer 19 having a thickness of 0.1 μm was formed (see FIG. 3D).

(16) Furthermore, by repeating the steps (9) to (15) , an upper interlayer resin insulation layer is formed on the upper conductor circuit, and then the uppermost conductor is formed on the upper interlayer resin insulation layer. The circuit 9 was formed, and a nickel plated layer 19 was formed on the upper surface of the uppermost conductor circuit 9 to obtain a multilayer printed wiring board .
Thereafter , sputtering was performed on the surface of the multilayer printed wiring board under the condition (11) to form nickel layers on the side surfaces and the upper surface of the uppermost conductor circuit as shown in FIG.

(17) On the other hand, 46.67g of photosensitized oligomer (molecular weight 4000) obtained by acrylating 50% of the epoxy group of 60% by weight cresol novolac type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG, dissolved in methyl ethyl ketone. 80% by weight of bisphenol A epoxy resin (Oka Shell, Epicoat 1001) 15.0 g, imidazole curing agent (Shikoku Chemicals, 2E4MZ-CN) 1.6 g, polyvalent acrylic monomer (Nippon Kasei) 3 g of medicine, R604), 1.5 g of polyacrylic monomer (Kyoeisha Chemical Co., DPE6A) and 0.71 g of a dispersion antifoam (Sanopco, S-65) are mixed. 2 g of benzophenone (manufactured by Kanto Chemical Co., Ltd.) as an agent and 0.2 g of Michler ketone (manufactured by Kanto Chemical Co., Ltd.) as a photosensitizer, and a solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C. It was.
Viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type) with rotor No. 4 for 60 rpm and rotor No. 3 for 6 rpm.

(18) The multilayer printed wiring board obtained in the above (16) was sandwiched between a pair of application rolls of a roll coater in a vertically standing state, and a solder resist composition was applied to a thickness of 20 μm.
(19) Next, after drying at 70 ° C. for 30 minutes, the film was exposed to 1000 mJ / cm ² of ultraviolet light and DMTG developed. Furthermore, heat treatment was performed at 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours. (Aperture diameter 200 μm) A solder resist layer (thickness 20 μm) 18 was formed.

(20) Next, the substrate was placed in an electroless gold plating solution consisting of an aqueous solution of potassium gold cyanide 2 g / l, ammonium chloride 75 g / l, sodium citrate 50 g / l and sodium hypophosphite 10 g / l. A gold plating layer 20 having a thickness of 0.03 μm was formed on the nickel layer by dipping for 23 seconds under the condition of ° C.
(21) Then, a solder paste 21 was printed on the opening of the solder resist layer 18 and reflowed at 200 ° C. to form a solder bump 21, and a printed wiring board having the solder bump 21 was manufactured (FIG. 4B). )reference).

(Example 2)
In this example, TPX (trade name) manufactured by Mitsui Chemicals was used as the polyolefin resin, desmeared under the same oxygen plasma conditions as in Example 1, and then irradiated with ultraviolet rays for 30 to 60 seconds with a low-pressure mercury lamp. Then, surface modification was performed to introduce OH groups and carbonyl groups. In this example, Pd was further adhered to the polyolefin resin insulation layer and the conductor circuit surface at a thickness of 0.1 μm under the conditions of atmospheric pressure 0.6 Pa, temperature 100 ° C., power 200 W, and time 2 minutes. In the same manner as in Example 1, a multilayer printed wiring board was produced.

(Example 3)
In this example, SPS (trade name) manufactured by Idemitsu Petrochemical Co., Ltd. was used as the polyolefin resin, and Ti was used under the conditions of atmospheric pressure 0.6 Pa, temperature 100 ° C., power 200 W, time 5 minutes, A multilayer printed wiring board was produced in the same manner as in Example 1 except that it was adhered to the conductor circuit with a thickness of 0.1 μm.

(Example 4)
In this example, a multilayer printed wiring board was produced in the same manner as in Example 1 except that Cr, Sn, Mo, W, and Fe were sputtered instead of Ni. Sputtering was performed at a thickness of 0.1 μm on the surface of the polyolefin-based resin insulation layer and the conductor circuit under the conditions of atmospheric pressure 0.6 Pa, temperature 100 ° C., power 200 W, and time 2 minutes.

(Comparative Example 1)
(1) This comparative example uses a cresol novolak acrylate prepared by the method shown below instead of the polyolefin resin constituting the interlayer resin insulation layer, and a conductor circuit by the methods (2) to (10) described later. A multilayer printed wiring board was produced in the same manner as in Example 1 except that was formed.
(a). 35 parts by weight of 25% acrylated cresol novolac type epoxy resin (Nippon Kayaku, molecular weight 2500), 3.15 parts by weight of photosensitive monomer (Toa Gosei, Aronix M315), defoaming agent (Sanopco, S-65) 0.5 parts by weight and 3.6 parts by weight of NMP were mixed with stirring.
(b). After mixing 12 parts by weight of polyethersulfone (PES), 7.2 parts by weight of epoxy resin particles (manufactured by Sanyo Kasei, polymer pole) with an average particle diameter of 1.0 μm, and 3.09 parts by weight with an average particle diameter of 0.5 μm, Further, 30 parts by weight of NMP was added and stirred and mixed with a bead mill.
(c). 2 parts by weight of an imidazole curing agent (manufactured by Shikoku Chemicals, 2E4MZ-CN), 2 parts by weight of a photoinitiator (manufactured by Ciba Geigy, Irgacure I-907), 0.2 parts by weight of a photosensitizer (manufactured by Nippon Kayaku, DETX-S), 1.5 parts by weight of NMP was mixed with stirring. These were mixed to obtain an electroless plating adhesive.

(2) Apply the adhesive for electroless plating obtained in (1) above on the substrate prepared in (1) to (8) of Example 1 with a roll coater and leave it for 20 minutes in a horizontal state. Drying at 60 ° C for 30 minutes, applying an electroless plating adhesive using a roll coater, leaving it in a horizontal state for 20 minutes, drying at 60 ° C for 30 minutes, and bonding to a thickness of 40 µm An agent layer was formed.

(3) A photomask film on which a black circle of 85 μmφ was printed was brought into close contact with both surfaces of the substrate on which the adhesive layer was formed in the above (2), and was exposed at 500 mJ / cm ² with an ultrahigh pressure mercury lamp. This was spray-developed with a DMDG solution to form an opening serving as a via hole of 85 μmφ in the adhesive layer. Furthermore, the substrate is exposed to 3000 mJ / cm ² with an ultra-high pressure mercury lamp, and heated at 100 ° C. for 1 hour and then at 150 ° C. for 5 hours. An interlayer insulating material layer (adhesive layer) having a thickness of 35 μm having a via hole forming opening) was formed. Note that the tin plating layer was partially exposed in the opening serving as the via hole.

(4) The exposed substrate was spray-developed with a DMTG (triethyleneglycdimethylether) solution, thereby forming an opening to be a 100 μmφ via hole in the adhesive layer. Furthermore, the substrate is exposed at 3000 mJ / cm ² with an ultra-high pressure mercury lamp and heat-treated at 100 ° C. for 1 hour and then at 150 ° C. for 5 hours, resulting in excellent dimensional accuracy equivalent to that of a photomask film. An adhesive layer having a thickness of 50 μm having (a via hole forming opening) was formed. Note that the roughened layer is partially exposed in the opening serving as the via hole.

(5) The substrate on which the opening for forming a via hole is formed is immersed in chromic acid for 2 minutes to dissolve and remove the epoxy resin particles present on the surface of the adhesive layer, and then the surface of the adhesive layer is roughened. After immersing in a neutralized solution (manufactured by Shipley Co., Ltd.), it was washed with water.
(6) A catalyst core was imparted to the surface of the adhesive layer and the opening for the via hole by imparting a palladium catalyst (manufactured by Atotech) to the substrate subjected to the roughening treatment (roughening depth 5 μm).

(7) The substrate was immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film having a thickness of 0.6 μm on the entire rough surface. At this time, since the plating film was thin, unevenness was observed on the surface of the electroless plating film.
[Electroless plating aqueous solution]
EDTA 150g / l
Copper sulfate 20g / l
HCHO 30ml / l
NaOH 40g / l
α, α'-bipyridyl 80mg / l
PEG 0.1g / l
[Electroless plating conditions]
30 minutes at a liquid temperature of 70 ° C

(8) A commercially available photosensitive dry film was attached to the electroless copper plating film, a mask was placed, exposed at 100 mJ / cm ² , developed with 0.8% sodium carbonate, and a plating resist with a thickness of 15 μm was provided. .
(9) Next, after washing the substrate with water at 10 to 35 ° C., electrolytic copper plating was performed under the following conditions to form an electrolytic copper plating film having a thickness of 15 μm.
(Electrolytic plating aqueous solution)
Copper sulfate 180g / l
Copper sulfate 80g / l
Additive (product name: Kaparaside GL, manufactured by Atotech Japan)
1ml / l
[Electrolytic plating conditions]
Current density 1A / dm ²
Time 30 minutes Temperature Room temperature

(10) After removing the plating resist with 5% KOH, the electroless plating film under the plating resist is dissolved and removed by etching using a mixed solution of sulfuric acid and hydrogen peroxide. A multilayer printed wiring board was obtained by forming a conductor circuit (including via holes) having a thickness of 15 μm made of an electrolytic copper plating film (see FIG. 5A).
Then, it processed like Example 1 and manufactured the printed wiring board which has a solder bump (refer FIG.5 (b)).

(Comparative Example 2)
This comparative example is the same as Example 1, but a polyolefin resin was laminated only on one side.

(Reference Example 1)
A multilayer printed wiring board was produced in the same manner as in Comparative Example 1 except that an aluminum nitride substrate was used as the substrate.

(Reference Example 2)
A multilayer printed wiring board was produced in the same manner as in Comparative Example 1 except that a copper plate was used as the substrate.

The peel strength of the multilayer printed wiring boards according to Examples, Comparative Examples, and Reference Examples produced in this manner was measured.
Further, the circuit board was tested for 500 cycles at −55 ° C. to 125 ° C.
In addition, after mounting the IC chip, the presence or absence of migration after driving at room temperature for 1000 hours in an atmosphere with 100% relative humidity was evaluated. The presence or absence of migration was determined by the presence or absence of interlayer conduction. Further, the minimum L / S that can be produced was examined, and the results are shown in Table 1.

As is clear from the results shown in Table 1, the wiring boards according to the examples of the present invention ensured sufficient peel strength even though the roughened surface was not provided on the interlayer resin insulation layer. On the other hand, although the wiring board of Comparative Example 1 was provided with a roughened surface, its peel strength was as low as 1.0 kg / cm.
Moreover, although the wiring board according to the example of the present invention has poor heat dissipation, diffusion of copper is suppressed by a metal such as Ni or Pd, so that interlayer insulation is ensured without migration.
On the other hand, as can be understood from Comparative Example 2, cracks cannot be suppressed even if a polyolefin resin layer, a Ni layer and a copper plating layer, or a Ni layer of a copper plating layer is provided only on one side. Moreover, in the comparative example 1, although the buildup layer is formed in both surfaces, a crack cannot be suppressed.
That is, the build-up layers are formed on both surfaces of the resin substrate, and the metals of the 4th to 7th periods in the groups IVa to Ib of the periodic table provided on the surface of the conductor circuit are Cu. It can be seen that the effect of the present invention is achieved by forming at least one metal layer selected from the removed metals.
In the present invention, fine wiring with L / S = 15/15 μm can be formed.

  As is clear from the reference example, when a metal plate or a ceramic substrate is used as the substrate, cracks and migration do not occur in the first place, and the present invention solves a specific problem occurring in the resin substrate. I can say that.

DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Copper foil 3 Through hole 4,11 Roughening layer 5 Resin filler 6,14 Electroless plating film 7,15 Electroplating film 8 Etching resist 9 Conductor circuit 10 Conductor layer (lid plating layer)
12 Interlayer Resin Insulating Layer 13 Via Hole Opening 16 Plating Resist 17 Via Hole 18 Solder Resist Layer 19 Nickel Plating Layer 20 Gold Plating Layer 21 Solder Bump (Solder Body)

Claims (11)

In a multilayer printed wiring board in which interlayer resin insulation layers and conductor circuits are alternately laminated, and an upper conductor circuit and a lower conductor circuit are connected via via holes,
The upper or lower conductor circuit has Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Hf, Ta on at least a part of its surface. , W, Re, Os, Ir, Pt, Au, Rf, Db, Sg, Bh, Hs, Mt, Ds, Rg, Al and formed by applying one or more metals selected from Sn and Sn A multilayer printed wiring board comprising a metal layer. The multilayer printed wiring board according to claim 1, wherein a surface of the conductor circuit is flat. The multilayer printed wiring board according to claim 1, wherein a surface of the conductor circuit is not roughened. The multilayer printed wiring board according to claim 1, wherein the metal layer contains Sn. The multilayer printed wiring board according to claim 1, wherein the metal layer is formed by plating Sn on at least a part of the upper conductor circuit. The multilayer printed wiring board according to claim 1, wherein at least a part of the surface of the metal layer is flat. 2. The multilayer printed wiring board according to claim 1, wherein the interlayer resin insulating layer is made of either a thermosetting polyolefin resin or a thermoplastic polyolefin resin. A method for producing a multilayer printed wiring board in which an interlayer resin insulation layer and a conductor circuit are alternately laminated, and a via hole for connecting an upper layer conductor circuit and a lower layer conductor circuit is formed in the interlayer resin insulation layer. ,
Forming a conductor circuit on the interlayer resin insulation layer;
Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Os are formed on at least a part of the surface of the conductor circuit. Forming a metal layer composed of one or more metals selected from Ir, Pt, Au, Rf, Db, Sg, Bh, Hs, Mt, Ds, Rg, Al, and Sn;
Forming another interlayer resin insulation layer on the interlayer resin insulation layer in a state of covering the conductor circuit;
A method for producing a multilayer printed wiring board, comprising: The method for manufacturing a multilayer printed wiring board according to claim 8, wherein the conductor circuit is formed so that a surface thereof is flat. The method for manufacturing a multilayer printed wiring board according to claim 8, wherein the conductor circuit is formed without being roughened. The method for manufacturing a multilayer printed wiring board according to claim 8, wherein the metal layer is formed by plating Sn on at least a part of a surface of the conductor circuit.

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