TW396536B - Using damascene to form bit line - Google Patents
Using damascene to form bit line Download PDFInfo
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- TW396536B TW396536B TW087115641A TW87115641A TW396536B TW 396536 B TW396536 B TW 396536B TW 087115641 A TW087115641 A TW 087115641A TW 87115641 A TW87115641 A TW 87115641A TW 396536 B TW396536 B TW 396536B
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- dielectric layer
- bit line
- hard material
- forming
- layer
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- 239000000463 material Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 25
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 8
- 125000006850 spacer group Chemical group 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 14
- 239000010931 gold Substances 0.000 claims description 14
- 229910052737 gold Inorganic materials 0.000 claims description 14
- 230000002079 cooperative effect Effects 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000000835 fiber Substances 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 238000005192 partition Methods 0.000 claims 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Description
368 ltwf.doc/008 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明(>) 方法;以及 第4圖係顯示第3F圖之俯視圖。 其f,各圖標號之簡單說明如下: 100、300 :基底 102 :氧化物層 106、106a、l〇6b :複晶矽層 108、108a、l〇8b :矽化鎢 110、204、402 :位元線 112、316b:內連線 200、400 :節點接觸窗 302、310、31〇a、318 :介電層 304 :硬材料層 308 :導電層 314:硬材料間隙壁 316a :內連線 實施例 習知技藝中,爲使節點接觸窗具有較大的對準空間, 因此位兀線的內連線通常以較小的尺寸製作,然此卻造成 曝光的困難,而節點接觸窗的對準空間卻往往還是不夠 大,致使接點接觸窗與位元線接觸造成短路的現象。 因此本發明提出一種以嵌金法形成位元線接觸窗的方 法其係在以嵌金法形成位元線接觸窗開口後,在欲形成 位元線與內連線開口側邊形成一間隙壁,而位元線與內連 線之尺寸藉間隙壁而減小,不會如習知技藝受限於光源解 5 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210%297公釐〉 (讀先閱讀背面之注意事項再填寫本頁)
3681 twf.doc/008 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明u ) 析度,而使開口尺寸無法縮小。而間隙壁之存在,使得即 使在對準稍有偏差時,仍可以自動對準的方式蝕刻,而不 致因_位元線接觸而短路。本發明以一實施例說明如下, 如第3A圖至第3G圖所示,爲根據本發明以嵌金法形成字 元線之一較佳實施例。 請參照第3A圖,在一基底3〇〇上已形成有元件隔離結 構與字元線(未繪出)等,之後在基底3〇〇上形成—介電靥 3〇2,例如以化學氣相沉積法形成一氧化物層,而介電餍 302覆蓋住字元線等。接著,在介電層3〇2上形成一硬衬 料層304 ’例如以化學氣相沉積法沉積一氮化矽層。續以 微影触刻法在硬材料層3〇4與介電層3〇2中定義一位元線 接觸窗口 306,暴露出基底300,接著對暴露出的基底3〇0 進行離子植入的步驟,以降低後續塡入之導電層與基底 300 之接觸阻値(contact resistance)。 接著’在硬材料層3〇4上形成一導電層,塡入位元線 接觸窗開口 306並延伸至硬材料層3〇4上,再以硬材料層 ,軸刻終點,回蝕刻導電層,而暴露出硬材料層,形 成如第3B圖所示塡滿位元線接觸窗開口 3〇6之導電靥 308 ’而導電層308與基底3〇〇之接觸阻値可藉由上述之 離子植入步驟而降低。 之後’在硬材料層3〇4與導電層3〇8上形成一介電層 310 ’如第3C圖所示,例如沉積一氧化物層覆蓋住硬材料 層3〇4與導電層3〇8。接著,定義介電層31〇,在介電層 310中形成開口 3l2a與溝渠312b,其中開口 :312a暴露出 本紙張尺度適-— (請先閩讀背面之注意事^再填^本頁}
368 1 twf.doc/008 經濟、部中央標準局—工消費合作社印製 A7 B7 五、發明説明(ir ) 導電層308與部分硬材料層3〇4,開口312&作爲位元線接 觸窗上之位元線部分,而溝渠312b中暴露出基底300,係 作爲位元線與位元線連接之內連線部分。爲使之後形成的 節點接觸窗具有足夠的對準空間,所以作爲內連線之溝渠 312b寬度較小,此時,因位元線接觸窗開口已塡入導電層 3〇8,所以是在一較爲平坦的表面進行位元線開口 312a與 溝渠312b之曝光步驟,故在製作上較爲容易,且塡入後 之位元線沒有高低起伏的部分,故阻値也較習知爲低。 接著,再對基底300形成一硬材料層,並回蝕刻硬材 料層,而在開口 312a與溝渠312b側壁形成一硬材料間隙 壁314,其中開口 312a暴露出導電層308,而溝渠312b 暴露出硬材料層3〇4,如第3E圖所示。之後,對基底300 再沉積一導電層,並回蝕刻導電層,形成如第3F圖所示 沉積在導電層308上之導電層3 16a與沉積在溝渠中之導電 層316b,其中導電層316a作爲位元線接觸窗308上之位 元線,而導電層316b作爲內連線部分。導電層316a、316b _例如以低壓化學氣相沉積法(LPCVD)沉積一矽化鎢。 之後,請參照第3G圖,再對基底300形成一介電層 318,並加以平坦化,再進以回蝕刻到足夠的高度使其具 有定夠的隔離效果即可,介電層318例如爲硼磷矽玻璃 (BPSG)。 、 •:第4圖所示爲第3F圖之俯視圖,一般爲增加節點接觸 窗4〇0的對準空間,並避開位元線接觸窗308上的位元線 318a部分,內連線316b部分的尺寸通常定義的較窄,而 7 本紙張尺度適用中國國家標準(CNS ) A4规格(210 X 297公釐) 、τ (#先閱讀背面之注意事項再填寫本頁)
3681twf.doc/008 A7 B7 五、發明説明(l ) 使得曝光較爲困難。本發明以嵌金法的方式進行位元線 4〇2的製作,可增大位元線接觸窗上位元線3 16a曝光的空 間,使得之後在蝕刻節點接觸窗開口時,即使因對準誤差 而對偏也因遇到硬材料間隙壁,而不致短路。 另外’ 一般位元線在周邊電路區較爲稀疏,而在記憶 體區較爲稠密,因此在習知完成位元線並以介電層平坦化 後,記憶體區與周邊電路區便具有一高低落差,造成隨後 製程進行之困難。而本發明以嵌金法完成位元線之製作, 較無高低落差的問題,且具有較佳之平坦化。 習知作法中’位元線以複晶矽層與矽化鎢層組成,高 度較高,本發明提出之方法,以複晶矽層爲位元線接觸窗 材質,位元線只有矽化鎢層’因此使得位元線高度較低, 而記憶體的整體高度便可降低,亦可使高低落差的問題減 輕。 雖然本發明已以一較佳實施例揭露如上,然其並非用 以限疋本發明’任何熟習此技藝者,在不脫離本發明之精 神和範圍內’當可作各種之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (諳先閩讀背面之注意事項再填寫本頁〕 ----------—^訂·------ 經濟部中央標準局員工消費合作社印製
格 規 4 釐 公 7
Claims (1)
- 3 68 ltwf.doc/008 A8 B8 C8 D8 六、申請專利範圍 1. 一種以嵌金法形成位元線之製造方法,該製造方 法包括下列步驟: 提供具有一第一介電層之〜基底; 在該第一介電層上形成一第一硬材料層; 定義該第一硬材料層與該第一介電層,在該第一介電 層形成一位元線接觸窗開口,暴露出該基底; 在該位元線接觸窗開口中形成一第一導電層,作爲該 位元線接觸窗; 對該基底形成一第二介電層; 定義該第二介電層’在該位元線上方形成一開口,暴 露出該第一導電層與部分該第一硬材料層; 在該第二介電層側壁形成〜硬材料間隙壁;以及 在該開口中形成一第二導電層,形成該位元線。 2·如申請專利範_ 1 述以嵌金法形成位元線 之製造方法,其中該第一導電餍包括複晶矽層。 3·如申請專利範圍第1項所述以嵌金法形成位元線 之製造方法’其中該第二導電層包括矽化鎢。 4·如申請專利範圍第1項所述以嵌金法形成位元線 之製造方法,其中該第-硬材料層包括氮化政。 5、 ·如申請專利範圍第1項所述以嵌金法形成位元線 之製造方法’其中該硬材料卩雜壁包賴化賴隙壁。 6. 如申請專利範圍第1項所述以嵌金法形成位元線 之製造方法,其中在形成該位元線接觸窗開口後,更包括 對基底進行一離子植入的步驟。 9 本紙張尺度適用中國國家標準(CNS ) A4規格(210x297公釐) 裝 一 訂 (請先鬩讀背面之注再填寫本頁) 經濟部中央標準局員工消費合作社印製 3681twf.doc/008 A8 B8 C8 D8 、申請專利範圍 7·如申請專利範圍第1項 之製造方法,其中形成該硬析述以嵌金法形成位元線 對該基底形成-第二硬材隙壁更包括 以該第二介電層爲蝕刻終點 層,在該位元線接觸窗開口爾辟D_ J Β亥第二硬材料 8_ 一種以嵌錄形間隙壁。 法包括下列步驟: 線之製匕方法,該製造方 提供具有一第一介電層之〜基底. 在該第—介電層上依序形成-硬材料層與-第二介電 層, 第二介電層’在該第二介電層中形成,; 在_、二介電層側壁形成一硬材料間隙壁;以及 在5亥溝渠中形成-導電層,該導電層作爲該內連線。 9·如申請專利範圍第8項所述以嵌金法形成內連線 之製造方法,其中該導電層包栝一矽化鎢。 10.如申請專利_第8類述以嵌金法形成內連線 之製造方法,其中該硬材料層包括氮化矽。 11·如申請專纖圍第8觀述以㈣法形成內連線 之製造方法,其中硬材料間隙壁包括氮化矽。 12. —種以嵌金法形成位元線之製造方法,提供具有 一第一介電層之一基底,且該第一介電層中形成有一位元 線接觸窗’該基底上形成有一硬材料層,暴露出該位元線 接觸窗,該製造方法包括下列步驟: 在該第一介電層上形成一第二介電層; 1 0 私紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐) (詩先閔讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 -------^訂---------------^---------Il·-- A8 368 1 twf‘doc/008 B8 C8 D8 六、申請專利範圍 在該第二介電層中形成一開口與一溝渠,其中該開口 暴露出該位元線接觸窗與部分該硬材料層,該溝渠暴露出 該硬材料層; 在該開口與該溝渠側壁形成一硬材料間隙壁;以及 在該開口與該溝渠形成一導電層。 --------— (請先鬩讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製 \ 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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TW087115641A TW396536B (en) | 1998-09-19 | 1998-09-19 | Using damascene to form bit line |
US09/206,112 US6071804A (en) | 1998-09-19 | 1998-12-04 | Method of fabricating bit lines by damascene |
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TW087115641A TW396536B (en) | 1998-09-19 | 1998-09-19 | Using damascene to form bit line |
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TW087115641A TW396536B (en) | 1998-09-19 | 1998-09-19 | Using damascene to form bit line |
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Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US6066548A (en) | 1996-10-31 | 2000-05-23 | Micron Technology, Inc. | Advance metallization process |
US6255168B1 (en) * | 1999-09-13 | 2001-07-03 | United Microelectronics Corp. | Method for manufacturing bit line and bit line contact |
KR100578230B1 (ko) * | 2000-06-30 | 2006-05-12 | 주식회사 하이닉스반도체 | 듀얼다마신공정을 이용한 비트라인 형성 방법 |
US7081398B2 (en) * | 2001-10-12 | 2006-07-25 | Micron Technology, Inc. | Methods of forming a conductive line |
TW200507171A (en) * | 2003-08-05 | 2005-02-16 | Nanya Technology Corp | Method for preventing short-circuits of conducting wires |
US7118966B2 (en) * | 2004-08-23 | 2006-10-10 | Micron Technology, Inc. | Methods of forming conductive lines |
US9401304B2 (en) | 2014-04-24 | 2016-07-26 | Sandisk Technologies Llc | Patterning method for low-k inter-metal dielectrics and associated semiconductor device |
Family Cites Families (3)
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US5691238A (en) * | 1995-06-07 | 1997-11-25 | Advanced Micro Devices, Inc. | Subtractive dual damascene |
US5693568A (en) * | 1995-12-14 | 1997-12-02 | Advanced Micro Devices, Inc. | Reverse damascene via structures |
US5893748A (en) * | 1997-02-10 | 1999-04-13 | Advanced Micro Devices, Inc. | Method for producing semiconductor devices with small contacts, vias, or damascene trenches |
-
1998
- 1998-09-19 TW TW087115641A patent/TW396536B/zh not_active IP Right Cessation
- 1998-12-04 US US09/206,112 patent/US6071804A/en not_active Expired - Lifetime
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